Datasheet VT86C100A Datasheet (VIA)

VIA Technologies, Inc. Preliminary VT86C100A

VT86C100A

PCI FAST ETHERNET CONTROLLER

DATA SHEET

(Preliminary)

DATE : Aug 31, 1997

VIA TECHNOLOGIES, INC.

VIA Technologies, Inc. Preliminary VT86C100A

PRELIMINARY RELEASE

Please contact Via Technologies for the latest documentation.

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VIA Technologies, Inc. Preliminary VT86C100A

VT86C100A PCI FAST ETHERNET CONTROLLER FEATURES

* Single chip Fast Ethernet controller for PCI bus interface

-- compliant to PCI v2.1 with optional delay transaction and sub-vendor, sub-system- ID

-- Provides a direct connection to PCI bus

-- Supports two network ports : 10/100 M MII interface

* High performance PCI mastering structure

-- VIA self-define 128 bytes memory I/O or register I/O based command and status register

-- Software oriented chain structure description to minimize hardware complexity

-- Include on chip bus master DMA with programmable burst length for low CPU utilization

-- Dynamic transmit packet auto queuing for back auto queuing for bac for back to back transmissin

-- Programmable activity polling intervals for description DMA

-- Programmable DMA arbitration priority to minimize overflow under flow condition

-- Support early receive and early transmit interrupt for software parallel processing

-- Interrupt controllable by receive/transmit descriptor list for saving interrupt service time
* Provides standard 100-M bits MII interface

-- Support 100Base-TX with CAT5 UTP, STP and fiber cables

-- Support 100Base-T4 with CAT3, CAT4, CAT 5 UTP, STP
* 10/100Mhz full duplex, half duplex operation
* Contains two deeper 2K bytes FIFO for receive and transmit controller both supports bursts of

up to full Ethernet length

-- Programmable receive and transmit FIFO threshold control for optimize PCI throughput
* Flexible dynamically load EEPROM algorithm.

-- Load after power-up

-- Dynamic auto reload

-- Embedded programming for configure modification

-- Dynamic direct programming for manufacturing
* Support physical, Broadcast, Multicast address filtering using hashing function
* Support Magic packet and wake on address filtering
* Support external Bootrom up to 64K bytes no external address latch
* Software controllable power down feature
* Single +5V supply, 0.5um standard CMOS technology
* 128 pin PQFP package

VIA Technologies, Inc. Preliminary VT86C100A

PCI v2.1

AD[31:0]
PCICLK
PCIRST#
INTA#
CBE#[3:0]
IDSEL
FRAME#
IRDY#
TRDY#
DEVSEL#
STOP#
PAR

Boot
ROM

_MSRD,
_MSWR,
EECS

PCI
Bus

Interface

Unit

Config.

EEPROM

Configuration

Registers &

EEPROM Control

Tally Counters

Master
Registers

Machine
Mgmt.

PCI CFG

RxFIFO
2K bytes

&State
&Buffer

TxFIFO
2K bytes

10/100M

MAC Tx/Rx

Protocol

State

Figure 1: Application Diagram

MII

TXD[3:0],
RXD[3:0],
TX_EN
TX_ER, RX_ER
TX_CLK, RX_CLK
RX_DV, CRS, COL
MDIO

VIA Technologies, Inc. Preliminary VT86C100A

PIN DIAGRAM

MRXC

MRXDV

1
0
2

MTXC

MERR
1

0
0

VSS

VDD

MTXD0

MTXE

9
5

MTXD2

MTXD1

MCOL

MTXD3

TST

MCRS

9
0

VSS

VDD

NC2

MA11

MA12

MA13

MA14

MA15

GPIO1/AUXPME

8
5

8
0

MA9

MA10

VSS

RAMVSS

VDD

7
5

RAMVDD

MA7

MA8

MA6

MA5

7
0

MA4

MA3

MA2

VSS

VDD

6
5

MRXD0
MRXD1
MRXD2
MRXD3

VSS
VDD

MDC

MDIO

HDRST

M10TEN

INTA#

PCIRST#

PCICLK

VSS

VDD
GNT#
REQ#
PME#

AD31
AD30
AD29
AD28

VDD

VSS

AD27
AD26

103
105

110

115

120

125

128

1

AD25

AD24

CEB3#

5

AD23

IDSEL

VSS

AD22

AD21

1
0

VDD

AD20

VT86C100A

1
5

VSS

AD19

AD18

AD17

AD16

CBE2#

FRAME#

IRDY#

TRDY#

2
0

VDD

STOP#

DEVSEL#

VSS

PERR#

2
5

PAR

AD15

CBE1#

AD14

AD13

3
0

AD12

AD11

VSS

AD10

VDD

3
5

AD9

AD8

3
8

AD7

CBE0#

64

MA1
MA0
NC
NC

60

MD7
MD6
MD5
VSS
VDD

55

MD4
MD3
MD2
MD1
MD0

50

BPRD#
ECS
VSS
VDD
AD0

45

AD1
AD2
AD3
AD4
VSS
AD5

39

AD6

VIA Technologies, Inc. Preliminary VT86C100A

PIN DESCRIPTIONS

No. Name Type Description

PCI Bus Interface

121-

124,127-

128,1-

2,5,7-

9,11­14,27­32,35-

36,38,39-

40,42-46

115

113
114

3,16,26,37

4

17

18

19

20

21

AD31-0 I/O Address/Data are multiplexed on the same PCI pins. A bus transaction

consists of an address phase followed by one or more data phases. The
address phase is the clock cycle in which FRAME# is asserted. Write
data is stable and valid when IRDYB is asserted and read data is stable
and valid when TRDYB is asserted.

PCICLK I PCICLK provides timing for all transactions on PCI and is an input pin

to every PCI device.

INTA# OD INTA# is an asynchronous signal which is used to request an interrupt

PCIRST# I When PCIRST# is asserted low, the VT86C100A chip performs an

internal system hardware reset. PCIRST# may be asynchronous to CLK
when asserted or deasserted. It is recommended that the deassertion be
synchronous to guarantee clean and bounce free edge.

CBE#[3:0] I Bus Command/Byte Enables are multiplexed on the same PCI pins.

During the address phase of a transaction, CBE3-0B define the Bus
Command. Burring the data phase, CBE3-0B are used as Byte Enables.
The Byte Enables define which physical byte lanes carry meaningful
data. CBE0B applies to byte 0 and CBE3B applies to byte 3.

IDSEL I Used as a chip select during PCI configuration cycle.

FRAME# I/O Cycle Frame is driven by the current master to indicate the beginning

and duration of an access. FRAME# is asserted to indicate a bus
transaction is beginning. While FRAME# is asserted, data transfers
continue. When FRAME# is deasserted, the transaction is in the final
data phase.

IRDY# I/O Initiator Ready indicates the initiating agent's ability to complete the

current data phase of the transaction. IRDY# is used in conjunction with
TRDY#. A data phase is completed on any clock when both IRDY# and
TRDY# are asserted. During a write, IRDY# indicates that valid data is
present on AD31-0. During a read, it indicates the master is prepared to
accept data. Wait cycles are inserted until both IRDY# and TRDY# are
asserted simultaneously.

TRDY# I/O Target Ready indicates the target's agent's ability to complete the current

data phase of the transaction. TRDY# is used in conjunction with
IRDY#. A data phase is completed on any clock when both IRDY# and
TRDY# are asserted. During a read, TRDY# indicates that valid data is
present on AD31-0. During a write, it indicates the target is prepared to
accept data. Wait cycles are inserted until both IRDY# and TRDY# are
asserted simultaneously.

DEVSEL# I/O Device Select, when actively driven, indicates the driving device has

decoded its address as the target of the current access. As an input,
DEVSEL# indicates whether any device on the bus has been selected.

STOP# I/O VT86C100A drives STOP# to disconnect further traction.

VIA Technologies, Inc. Preliminary VT86C100A

25

PAR T/S Parity is even parity across AD31-0 and CBE3-0B. PAR is stable and

valid one clock after the address phase. For data phases PAR is stable
and valid one clock after either IRDY# is asserted on a write transaction
or TRDY# is asserted on a read transaction.

118

GNT# I Bus grant asserts to indicate to the VT86C100A that access to the bus is

granted.

119

REQ# O Bus request is asserted by the bus master indicate to the bus arbiter that

it wants to use the bus.

23
120
111

PERR# I/O Parity error asserts when a data parity error is detected

PME# O Power management event interrupt

HDRST O When PCIRST# is asserted low, the VT86C100A chip performs an

internal system hardware reset. Then HDRST is asserted high for
external device reset signal like PHY device.

Network Interface

91 MCOL I Collision detect when the external PHY device
90 MCRS I Carrier sense is asserted by the external PHY when the media is active

92-95 MTXD[3-0] O MII 4 parallel transmit data lines. This data be synchronized to assertion

by the MTXC signal

96 MTXEN O Transmit enable signals that the transmit is active in the MII port to an

external PHY device

99 MTXC I MII transmit clock supports the 25mhz or 2.5mhz transmit clock

supplied by the external PMD device. This clock should always be
active.

100 MERR I MII receive error asserts when a data decoding error is detected by

external PHY device.

101 MRXC I MII receive clock supports the 25mhz or 2.5mhz clock. This clock is

recovered by the PHY.

102 MRXDV I MII data valid

103-106 MRXD[0-3] I Four parallel receive data lines. This data be driven from external PHY

be synchronized with MRXC signal.

109 MDC O MII management data clock be soured by VT86C100A MDC bit

(MIIR:0) to the external PHY devices as timing reference for the
MDIO signal.

110 MDIO I/O MII management data input/output, read from MDI bit (MIIR:1) or

written from MDO bit (MIIR:2)

112 GPIO I/O GPIO

External Memory Support & General purpose I/O support

49 EECS O EEPROM Chip Select: Chip select signal for the external EEPROM

when a EEPROM is used to provide the configuration data and
Ethernet Address. A 100K pull-up resistor is connected.

50 BPRD# O Boot PROM Read: Read the Boot ROM on the memory support data

bus.

51 MD0/

EEDO

52 MD1/

EEDI

I/O Bootrom data 0

Serial ROM Data output

O/O Bootrom data 1

Serial ROM Data input

53 MD2/ EECLK O/O Bootrom data 2

Serial ROM Clock signal

54-55,58-

MD3-7 I/O Bootrom Data [3-7] :

60

VIA Technologies, Inc. Preliminary VT86C100A

63-64,67-

MA0-MA15 O Bootrom address line [0-15]

73,78-

84

85 GPIO1/AUXP

IO General purpose input and output 1 : usually as Magic key interrupt line

ME

112 GPIO2/LKC IO General purpose input and output 2, this pin usually as link change status

from external PHY device.

Power Supply & Ground

10,22,34,47,

56,65,76,
87,97,108

,117,125

6,15,24,33,

41,48,57
,66,75,7
7,88,98,
107,116,

126

VDD, VDDA P Positive 5V Supply: Supply power to Internal digital logic, Digital I/O

pads, and TD, TX pads. Double bonding may be required.

VSS, VSSA G Negative Supply: digital ground. Multiple bonding pads are

required to separate core and I/O pads ground.

VIA Technologies, Inc. Preliminary VT86C100A

FUNCTIONAL DESCRIPTIONS

1. GENERAL DESCRIPTION

The VT86C100A Rhine ACPI PCI bus master 100 M FAST Ethernet controller is CMOS VLSI designed for
easy implementation of CSMA/CD IEEE 802.3u 100M local area networks. Significant features include:
twisted-pair interface, PCI Plug&Play compatibility, 32 bit bus mastering, powerful buffer management and
Early Interrupt Receive/Transmit.

The VT86C100A integrates the entire bus interface of PCI systems. Setting hardware jumpers or software
configures the VT86C100A bus interface. The VT86C100A also complies with PCI specification v2.1.. The
VT86C100A supports the Media Independent Interface (MII) network interface.

1.1 FIFO AND CONTROL LOGIC

The VT86C100A incorporates two independent 2K bytes deeper FIFO for transmit or receive data from
system interface or to the network interface, providing temporary storage of data, free host system from the
real-time demands on network.
The VT86C100A enhanced the FIFO management logic to handle received data packets up to four packets
before transfer to system data buffer. This ability reduce the packets losing due to PCI bus mastering abrition
latency.

2. NETWORK INTERFACE

The VT86C100A Rhine ACPI support one MII interface

2.1 MII Interface

The MII interface is an IEEE 802.3 compliant interface that provides a simple and easy interconnection
between the MAC layer and PHY device. This interface has support the following characteristics :

• Support both 10M and 100M data rate.

• Contains data and synchronous clock

• 4-bit independent receive and transmit data.

• Uses TTL signal levels and compatibles with common CMOS processes.

VIA Technologies, Inc. Preliminary VT86C100A

3. EEPROM Interface and Programming

VT86C100A uses an 93C46 to store configuration data and Ethernet address.

3.1. EEPROM Contents

D15 D0

3FH

.
.
.
.
.
.

10H

0FH 73H 73H
0EH CFG_D CFG_C
0DH CFG_B CFG_A
0CH BCR1 BCR0
0BH MAX_LAT MIN_GNT
0AH Reserved Reserved

09H KEY5 KEY5

08H KEY3 KEY2

07H KEY1 KEY0

06H Reserved Reserved

05H SUBVID1 SUBVID0

04H SUBSID1 SUBSID0

03H Reserved Reserved

02H Ethernet Address 5 Ethernet Address 4

01H Ethernet Address 3 Ethernet Address 2

00H Ethernet Address 1 Ethernet Address 0

Note 1. The word on location 03H is optional to user's application requirement.
Note 2. Programming 73H into the upper address is required to protect the Ethernet address from being destroyed accidentally
Note 3. The word on location 04H, 05H is sub-System ID, sub-Vendor ID in PCI specification 2.1.

Reserved for 93C46

.
.
.
.
.
.
.

Reserved for 93C46

.
.
.
.
.
.
.

3.2. DIRECT PROGRAMMING OF EEPROM

The VT86C100A features a easy way to program external EEPROM in-situ. When the RESET is active and if
the upper byte of 0FH on EEPROM is not 73H, the EEPR bit will not be set to indicate that the current
EEPROM has not been programmed yet. This will allow the VT86C100A to enter Direct Programming mode
if EELOAD is also set. In this mode the user can directly control the EEPROM interface signals by writing to
the ECSR Port and the value on the EECS, ESK and EDI bits will be driven onto the EECS, SK(MD2), and
DI(MD1) outputs respectively. These outputs will be latched so the user can generate a clock on SK by
repetitively writing 1 then 0 to the appropriate bit. This can be used to generate the EEPROM signals as per
the 93C46 data sheet.

To read the EEPROM data, users have to generate EEPROM interface signals into EECS, DI and SK as
described above and in the mean time read the data from DO(MD0) input via pin SD0. Reading Data
Transfer Port during programming will not affect the latched data on EECS, SK, and DI outputs. When the

VIA Technologies, Inc. Preliminary VT86C100A

EEPROM has been programmed and verified (remember to program the upper byte of 0EH & 0FH with
73H), the user must give VT86C100A a power-on reset to return to normal operation and to read in the new
data.

The Direct Programming mode is mainly used for production to program every bit of the EEPROM. Once the
upper byte of 0EH has been programmed with 073H and a power-on reset has been performed, there is no
way to change the contents of EEPROM except Configuration Registers A, B, and C, which will be discussed
in the following paragraph. For more information, refer to EECSR.

3.3. EMBEDDED PROGRAMMING OF EEPROM

If the upper byte of 0FH of EEPROM has been programmed to 073H when VT86C100A is loading the
EEPROM data during power-on reset, the EEPR bit of Signature Register will be set to prohibit the Direct
Programming mode. However, the user can still program the configuration registers A, B, and C using the
Embedded Programming mode by following the routine specified in the pseudo code below. This operation
will work regardless of the value of EECONFIG. The setting of the EELOAD bit of Configuration Register B
starts the EEPROM write process. Care should be taken not to accidentally modify the POL and GDLNK bits
because these two bits return the value indifferent from the setting. This programming process is ended when
the EELOAD bit goes to zero.

EEPROM_EMB_PROG ( )

// defined constant: CONFIG_B, EELOAD
// declared register: value, config_for_A, config_for_B, config_for_C
// declared function: DISABLE_INTERRUPTS, ENABLE_INTERRUPTS, READ, WRITE, WAIT
DISABLE_INTERRUPTS ( );
value = READ (CONFIG_B);
value = value | EELOAD;
WRITE (CONFIG_B, value);
READ (CONFIG_B);
WRITE (CONFIG_B, config_for_A);
WRITE (CONFIG_B, config_for_B);
WRITE (CONFIG_B, config_for_C);
while (value || EELOAD)
{

value = READ (CONFIG_B);

WAIT ( );
}
ENABLE_INTERRUPTS ( );

VIA Technologies, Inc. Preliminary VT86C100A

4. PCI Configuration Space

Device ID

( 6100 )
STATUS

(DEVS1, DEVS0 ) = ( 1 , 0 )
CLASS CODE

( 02_00_00 )
BIST

( 00 )

Sub-System ID Sub-Vendor ID

EXP ROM BASE [ 31: 15 ]

Reserved Reserved

Max_LAT
( 00 )

MODE3 MODE2 FIFOTST MODE0 50H

Header type

( 00 )

CSR Memory Map Base Addr 000 0 0 0 1

CSR IO MAP SPACE 000 0 0 0 0

Min_GNT
( 00 )

Reserved Reserved

Vendor ID

( 1106 )
COMMAND

( MMSPACE, IOSPACE)

Revision ID

( 04 )

Latency Timer

( R/W )

ROM14 0000_0000_00000 EN

INT PIN
( 01 )

Cache Line

( R/W )

INTLINE

INTL [7:0]

00 h

04 h

08 h

0c h

10 h

14 h
2c h

30 h

3c h

5. MAGIC KEY FILTERING AND WAKE ON MAGIC KEY

The VT86C100A provides an one level power down mode. The BIOS or Network OS device driver can
configure Register A to diagnostic mode then set the Power-on bit of the diagnostic port to "on." When the
VT86C100A is in Power down mode, all power to the PCI interface is cut off and the chip clock is stopped.
Other registers are read only. Only the diagnostic port is read/writeable.
The VT86C100A can store one “Magic Key” (6 bytes Ethernet address) as external trigger event. When
VT86C100A received one Magic Key address packet, the PME# or GPIO1 will be generated to system.
These signal can be asserted to ATX power PS-ON (refere to ATX specification v2.01) or mother board wake
up interrupt line like ring-in.

VIA Technologies, Inc. Preliminary VT86C100A

6. BUFFER MANAGEMENT & HOST COMMUNICATION

The VT86C100A provides an simply and effective buffer management and host communication
method through the PCI Bus mastering : There are two descriptor lists, one for receive and one for transmit.
The base of these two list are pointed into the CRDA (18h) and CTDA (1ch) registers.

The descriptor list reside in the host physical memory address space with double word boundary.
And each descriptor lists just point to one single buffer, but a data buffer consists of either an entire frame or
part of a frame. Data chain can be enabled or disabled by DES1 C bit. Data buffer also reside in host physical
memory double word boundary space.

The device driver can make the last descriptors next link be point to first descriptor address, become
a ring buffer structure.

Buffer 1

Descriptor 0

Buffer 1

Descriptor 1

Next Descriptor

Figure 6-1 VT86C100A Buffer Management : Chain buffer Structure

6.1 DESCRIPTOR RING AND CHAIN STRUCTURE

6.1.1 RECEIVE DESCRIPTORS

Figure 6-2 shows the receive descriptor format :

Providing single buffer, one byte-count buffers, and next descriptor address. And Chain bit control
span multiple data buffers data chain to be compatible various types of memory management schemes..

VIA Technologies, Inc. Preliminary VT86C100A

31 23 15

O

RDES0

0 0 0 0

RDES1 Reserve Reserve C 0000
RDES2 Rx Data Buffer Start Address
RDES3 Next Descriptor Address

FIGURE 6-2 THE RECEIVE DESCRIPTOR FORMAT :

6.1.2. RECEIVE DESCRIPTOR 0 (RDES0)

RDES0 contain the received frame status, the frame length and the descriptor ownership information.

FLNG[10:0] RSR1 RSR0

Owner : This bit control by driver, 1 to identify this descriptor own by
VT86C100A controller, 0 means this descriptor be a free descriptor; Driver must
set this bit be zero when initialed.

Extend Frame Length : Extend byte count for no-normal size Ethernet frame
Frame Length : Received frame length,

RLNG[10:0]

Received OK : The VT86C100A received a good packet from network.
Multicast Address Received : VT86C100A MAC received multicast address

packet
Boardcast Address Received : VT86C100A MAC received boardcast address
packet

Physical Address Received : Physical address received
CHAIN : means of chain buffer,
Start of Packet : In descriptor ring structure, STP=EDP=1 single buffer

descriptor, or chained buffer structure be follows :
STP EDP Description
1 1 Single buffer descriptor
1 0 First buffer descriptor, further buffer chained
0 1 Chained buffer packet end
0 0 X

End of Packet : End of Packet buffer
Receive Status Register 0 :
Buffer Error : Receive Buffer Error
System bus error :
Runt Packet Received :
Long Packet Received :
FIFO Overflow :
Frame Align Error :
CRC Error : received frame CRC checksum error
Receive Error : this bit be set by CRC error or frame alignmnet error or FIFO

overflow or System bus error.

VIA Technologies, Inc. Preliminary VT86C100A

6.1.3. RECEIVE DESCRIPTOR 1 (RDES1)

RDES1 contain the interrupt control enable, the chained frame identical and the receive buffer
fragment size information.

Interrupt Control : This bit support for interrupt PACEing , set 1 mean the
VT86C100A received this descriptor will generate the interrupt.

Chain : Chain buffer , this bit be set to 1 means there are chained buffer in next
descriptor

Extend Fragment of Frame Length : must be zero now.
Rx buffer Size : Receive buffer size for this descriptor, the total byte count of

whole frame will be stored in last descriptors

6.2.1. TRANSMIT DESCRIPTORS

31 23 15

RDES0

O

RDES1 Reserve TCR C 0000
RDES2 Tx Data Buffer Start Address
RDES3 Next Descriptor Address

FIGURE 6-3 THE TRANSMIT DESCRIPTOR FORMAT

Reserve TSR1 TSR0

TLNG[10:0]

6.2.2. TRANSMIT DESCRIPTOR 0 (TDES0)

DES0 contain the received frame status, the frame length and the descriptor ownership information.

Owner : This bit control by driver, 1 to identify this descriptor own by
VT86C100A controller, 0 means this descriptor be a descriptor waiting for
transmit; Driver must set this bit be zero when initialed.

Transmit Status Register 1
Transmit OK : This bit be 1 for transmission error, the transmit include

following

- internal FIFO under-flow

- excessive collision (ABT)

- late collision (OWC)

- carrier sense lost (CRS)

14 JAB Jabber : This bit will set high if Jabber condition happens. Writing to this bit has

no effect
System Error : VT86C100A MAC experience error master abort, target abort,

parity error.
12 Reserve
11 Reserve

VIA Technologies, Inc. Preliminary VT86C100A

10 CRS
9 OWC Late Collisions : This bit is set when late collision occurred.
8 ABT Transmit Abort : transmit module abort after excessive collision.

7-0 TSR0

Carrier Sense lost bit is set when the carrier is lost during the transmission of a packet.

Transmit Status Register 0

CD heartbeat : this bit only effective in 10Base-T mode. When set, this bit

indicates a heartbeat collision check failure.

Collision retry count : this 4-bits counter indicates the number of collisions that

occurred

FIFO under-flow : this bit set indicates that the transmitter aborted by transmit

FIFO encountered an empty while transmitting a frame.

Deferred: When set, indicates that the VT86C100A had to defer while ready to

transmit a frame because carrier was asserted.

6.2.3. TRANSMIT DESCRIPTOR 1 (TDES1)

DES1 contain the transmit status, the frame length and the descriptor ownership information.

Transmit Configure Register

Interrupt Control : This bit support for interrupt PACEing , set 1 mean the

VT86C100A received this descriptor will generate the interrupt.

End of Packet : End of Packet buffer

Start of Packet : In descriptor ring structure, STP=EDP=1 single buffer

descriptor, or chained buffer structure be follows :

STP EDP Description

1 1 Single buffer descriptor

1 0 First buffer descriptor, further buffer chained

0 1 Chained buffer packet end

0 0 X

CRC disable : The VT86C100A transmitter will disable generated the CRC

when this set 1.

Chain : Chain buffer

Extend Fragment of Frame Length : must be zero now.

Transmit buffer size : the fragment of frame buffer size

6.3 Buffer Structure and Interrupt Control

data consists of an entire frame or part of a frame, but it cannot exceed a single Ethernet frame size. Buffers
contain only data; All buffer status is maintained in the descriptor . Data chaining can be enable or disable by
Chain bit in DES1[15]. The interrupt control also can be enable or disable by DES1[23]

VIA Technologies, Inc. Preliminary VT86C100A

6.3.1 Multiple Chained buffer structure

The VT86C100A can support multiple chain buffer for direct map to OS`s data buffer. The VT86C100A bus
mastering module will direct move the data from network to the OS`s data buffer or direct transmit the data in
OS`s buffer onto network not necessary move to a temperate data buffer. But the data buffer must be double
word aligned. In this multiple chained buffer structure, the first data buffer descriptor Chain

Simple Ring Buffer Structure

0

0

F0

F1

0

F2

Figure 6 : Ring buffer and multiple buffer structure

Multiple Buffer Frame

C

F0

C

F0

F0

0

C=DES1[15]

VIA Technologies, Inc. Preliminary VT86C100A

6.3.2 Interrupt Control

The VT86C100A can controllable the receive descriptors and transmit descriptor for what the interrupt
occurred.
The IC bit (DES1[23]) be set 1, the receive or transmit interrupt will be generate the interrupt no matter the
frame been complete received or transmitted. This feature will enable the OS pre-fetch the frame header or
saving the interrupt service overload.

C

I

ER Interrupt

Here

Interrupt
Here

C

0

0

F0

F0

F0

I

C

C

I

0

F1

F2

Interrupt
Here

Save this
interrupt

0

I

F3

Interrupt
Here

Figure 7. The Interrupt Control of VT86C100A

VIA Technologies, Inc. Preliminary VT86C100A

VT86C100A REGISTERS

Group 1 : Internal Command Status Register (CSR) Layout

NO byte3 byte2 byte1 byte0 type

PAR3/KEY3 PAR2/KEY2 PAR1/KEY1 PAR0/KEY0 RW

00
04
08
0c
10
14
18
1c
20
24
28
2c
30
34
38
3c
40
44
48
4c
50
54
58
5c
60
64
68
6c
70
74
78
7c

TCR RCR PAR5/KEY5 PAR4/KEY4 RW

CR1 CR0 RW

IMR2 IMR0 ISR1 ISR0 RW
MAR3 MAR2 MAR1 MAR0 RW
MAR7 MAR6 MAR5 MAR4 RW

Curr Rx Desc Addr RW
Curr Tx Desc Addr RW

Current Rx Desc 0 RO
Current Rx Desc 1 RO
Current Rx Desc 2 RO
Current Rx Desc 3 RO

Next Rx Desc 0 RO
Next Rx Desc 1 RO
Next Rx Desc 2 RO

Next Rx Desc 3 RO
Current Tx Desc 0 RO
Current Tx Desc 1 RO
Current Tx Desc 2 RO
Current Tx Desc 3 RO

Next Tx Desc 0 RO

Next Tx Desc 1 RO

Next Tx Desc 2 RO

Next Tx Desc 3 RO

Current Rx DMA Pointer RW
Current Tx DMA Pointer RW

Tally counter test port RW

BCR1 BCR0 MIISR PHY ADR

MII DATA REG MIIADR MIICR RW

GPIO TEST EECSR RW

CFGD CFGC CFGB CFGA RW

Tally counter_CRC Tally counter_MPA RW

VIA Technologies, Inc. Preliminary VT86C100A

Configuration and Diagnostic Registers

Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Read/

Write

Conf. B
Conf. C

Conf. D

EELOAD JUMPERMMIOENMIIOPT AUTO

QPKTDIS TPACENMRDM TXARBITRXARBITMWW

RES BROPT DLYEN DTSEL BTSEL BPS2 BPS1 BPS0
GPIOEN DIAG MRDLENMAGIC CRADOMCAP MBA BAKOPT

OPT

Note :

1. The shaded area denoted that those bits are also selective via external jumpers.

2. All reserved bit must be zero.

No. Name Type Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
00H PAR0 R/W DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0
01H PAR1 R/W DA15 DA14 DA13 DA12 DA11 DA10 DA9 DA8
02H PAR2 R/W DA9 DA10 DA11 DA12 DA13 DA14 DA15 DA16
03H PAR3 R/W DA17 DA18 DA19 DA20 DA21 DA22 DA23 DA24
04H PAR4 R/W DA25 DA26 DA27 DA28 DA29 DA30 DA31 DA32
05H PAR5 R/W DA33 DA34 DA35 DA36 DA37 DA38 DA39 DA40
06H RCR R/W RRFT2 RFT1 RFT0 PROM AB AM AR SEP
07H TCR R/W RTSF RTFT1 RTFT0 OFST LB1 LB0
08H CR0 R/W RDMD TDMD TXON RXON STOP STRT INIT
09H CR1 R/W SRST RDMD1 TDMD1 KEYPAGDPOLL FDX ETEN EREN

MT10ENIMT10ENOMT10EOE

MRWAITLATMEM

AIT

78H
79H
7AH

7BH

0AH
0BH
0CH ISR0 R/W CNT BE RU TU TXE RXE PTX PRX
0DH ISR1 R/W KEYI SRCI ABTI NBFI PRAI OVFI ETI ERI
0EH IMR0 R/W CNTM BEM RUM TUM TXEM RXEM PTXM PRXM
0FH IMR1 R/W KEYIM SRCM ABTM NBFM PRAIM OVFM ETM ERM

10H MAR0 R/W FB7 FB6 FB5 FB4 FB3 FB2 FB1 FB0
11H MAR1 R/W FB15 FB14 FB13 FB12 FB11 FB10 FB9 FB8
12H MAR2 R/W FB23 FB22 FB21 FB20 FB19 FB18 FB17 FB16
13H MAR3 R/W FB31 FB30 FB29 FB28 FB27 FB26 FB25 FB24
14H MAR4 R/W FB39 FB38 FB37 FB36 FB35 FB34 FB33 FB32
15H MAR5 R/W FB47 FB46 FB45 FB44 FB43 FB42 FB41 FB40
16H MAR6 R/W FB55 FB54 FB53 FB52 FB51 FB50 FB49 FB48
17H MAR7 R/W FB63 FB62 FB61 FB60 FB59 FB58 FB57 FB56
18H RDA0 R/W AB7 AB6 AB5 AB4 AB3 AB2 AB1 AB0
19H RDA1 R/W AB15 AB14 AB13 AB12 AB11 AB10 AB9 AB8
1AH RDA2 R/W AB23 AB22 AB21 AB20 AB19 AB18 AB17 AB16
1BH RDA3 R/W AB31 AB30 AB29 AB28 AB27 AB26 AB25 AB24
1CH TDA0 R/W AB7 AB6 AB5 AB4 AB3 AB2 AB1 AB0
1DH TDA1 R/W AB15 AB14 AB13 AB12 AB11 AB10 AB9 AB8
1EH TDA2 R/W AB23 AB22 AB21 AB20 AB19 AB18 AB17 AB16
1FH TDA3 R/W AB31 AB30 AB29 AB28 AB27 AB26 AB25 AB24

6CH MPHY R/W MPO1 MPO0 PHYAD4PHYAD3PHYAD2PHYAD1PHYAD0

6DH MIISR R/W GPIO1POLLEDPOLMFDC PHYOPTMIIERR MRERR LNKFL SPEED

6EH BCR0 R/W REQOPTCRFT2 CRFT1 CRFT0 DMAL2 DMAL1 DMAL0

VIA Technologies, Inc. Preliminary VT86C100A

6FH BCR1 R/W CTSF CTF1 CTF0 POT2 POT1 POT0
70H MIICR R/W MAUTORCMD WCMD MDPM MOUT MDO MDI MDC

71H MIIAD R/W MSRCENMDONEMAD4 MAD3 MAD2 MAD1 MAD0

72H
73H
74H EECSR R/W EEPR EMBP LOAD DPM ECS ECK EDI EDO
75H TEST R/W HBDIS FCOL BKOFF TSTOVFTSTUDFTEST2 TEST1 TEST0

76H
77H
78H CFGA R/W EELOADJUMPERMMIOENMIIOPT AUTOOPTMT10ENOMT10ENOMT10EO

79H CFGB R/W QPKTDISTPACENMRDM TXARBITRXARBITMWWAITMRWAITLATMEN

7AH CFGC R/W BROPT DLYEN DTSEL BTSEL BPS2 BPS1 BPS0
7BH CFGD R/W GPIOENDIAG MRDLENMAGIC CRADOMCAP MBA BAKOPT

7CH MPAC0 R/W CD7 CD6 CD5 CD4 CD3 CD2 CD1 CD0
7DH MPAC1 R/W CD15 CD14 CD13 CD12 CD11 CD10 CD9 CD8
7EH CRCC0 R/W CD7 CD6 CD5 CD4 CD3 CD2 CD1 CD0
7FH CRCC1 R/W CD15 CD14 CD13 CD12 CD11 CD10 CD9 CD8

E

VIA Technologies, Inc. Preliminary VT86C100A

1.1 Configure Register Layout

Configuration Register A (0x78)

0 GPIO2OE MD3 GPIO2OE : Output enable of GPIO2 pin

GPIO2O : Output to GPIO2 pin
GPIO2I : GPIO2 input status
AUTOOPT : enable receive event auto transmit descriptor polling

MMIEN : Memory mapped IO enable, accept memory command

GPIO2

Configuration Register B (0x79)

0 LATMEN n/a LATMEN: Latency timer effect enable

4 TXARBIT n/a TXARBIT : the transmitting FIFO DMA will be interleave to receiving

7 QPKTDIS n/a QPKTDIS : disable transmit frame queuing.

JUMPER : Jumper mode to select PHY and operation mode
EELOAD : Enable EEPROM embedded and direct programming

MRWAIT : Master read insert one wait state 2-2-2-2
MWWAIT: Master write insert one wait state 2-2-2-2
RXARBIT : the receiving FIFO DMA will be interleave to transmitting

FIFO DMA after 32 double words transaction.

FIFO DMA after 32 double words transaction.

MRDM : Memory read multiple capable
TPACEN : Tx descriptor pacing algorithm enable

Configuration Register C (0x7A)

Bit Symbol Jumper Function

0-2 BPS0-

BPS3

Configuration Register D (0x7B)

0 BAKOPT n/a BAKOPT : Back-off algorithm optional

n/a Boot PROM Select: Select size at which boot PROM begins and the

size

Bit2 Bit1 Bit0 Size

0 0 0 No Boot PROM
0 0 1 8K
0 1 0 16K
0 1 1 32K
1 X X 64K

BTSEL : Bootrom timing select

DLYEN : Delay transaction while memory read Bootrom
BROPT : set Bootrom address line above Bootrom size selected to logic

1

for small size Bootrom

VIA Technologies, Inc. Preliminary VT86C100A

MBA : Modify back off algorithm
CAP : Capture effect back off
CRADOM : Random back off algorithm

4 MAGIC n/a MAGIC : Turn on Magic key

DIAG :

7 GPIOEN n/a GPIOEN : Turn on GPIO2 input status change monitor

VIA Technologies, Inc. Preliminary VT86C100A

VT86C100A Command Status Registers

MAC command and status register Group

CR0: Command Register 0 (08H; Type=R/W)

This register is used to select register pages, enable or disable remote DMA operation and issue
commands.

Reserved

6 RDMD
5 TDMD
4 TXON
3 RXON
2 STOP

1 STRT
0 INIT

CR1: Command Register 1 (09H; Type=R/W)

This register is used to select register pages, enable or disable remote DMA operation and issue
commands.

This bit indicates that the VT86C100A receive poll demand enable
This bit indicates that the VT86C100A transmit poll demand enable
This bit indicates that the VT86C100A start transmit state while STRT bit on
This bit indicates that the VT86C100A start receive state while STRT bit on
This bit indicates that the VT86C100A into STOP state , this bit set by SFRST bit or

hardware reset
This bit indicates that VT86C100A enter the start command.

Initialize Start : When set on the VT86C100A start to set its bus master register the start

This bit is set when VT86C100A enters reset state and is cleared when a start command is
issued to the CR1. It is also set when receive buffer overflows or system error.

6-4 RES

3 DPOLL
2 FDX
1 ETEN

0 EREN

Reserved
Disable transmit auto polling
This bit set MAC to full duplex in 10BaseT or 100BaseT mode
Early transmit mode enable while CFGD[1] be enable, this bit be clear while hardware

reset only
Early receive mode enable while CFGD[0] be enable, this bit be clear while hardware reset
only

RCR: Receive Configuration Register (06H; Type=R/W)

This register reflects the NIC receive configuration and reset by hardware reset and software reset

Bit Symbol Description

7 RRSF

6-5 RFT[1-0]

4 PRO
3 AB
2 AM

Receive store and forward
Receive FIFO Threshold.

RRFT2 RRFT1 RRFT0 Threshold
0 0 0 64 bytes
0 0 1 32
0 1 0 128
0 1 1 256
1 0 0 512
1 0 1 768
1 1 0 1024
1 1 1 Receive store and forward
If PRO=1, all packets with physical destination address are accepted. If PRO=0, physical
address must match the node address programmed in PAR0-5
If AB=1, packets with broadcast destination address are accepted. If AM=0, packets with
broadcast destination are rejected.
If AM=1, packets with multicast destination address are accepted. If AM=0, packets with
multicast destination are rejected.

VIA Technologies, Inc. Preliminary VT86C100A

1 AR
0 SEP

If AR=1, packets smaller than 64 bytes are accepted. If AR=0, packets smaller than 64 are
rejected.
If SEP=1, packets with receive errors are accepted. If SEP=0, packets with receive errors
are rejected.

TCR: Transmit Configuration Registers (07H, Type=R/W)

Bit Symbol Description

7 RTSF

6-5 RFT[1-0]

4 ­3 OFSET

2-1 LB[1-0]

0 -

Transmit and store and forward : till whole packet enter into FIFO then start transmit
Transmit FIFO Threshold :

RTSF RTF1 RTF0 Threshold
0 0 0 64 bytes
0 0 1 32
0 1 0 128
0 1 1 256
1 0 0 512
1 0 1 768
1 1 0 1024
1 1 1 Transmit store and forward
Reserve

Back-off priority selection : change the back off algorithm as National specification
Loopback mode select for transmit :

0 0 Normal
0 1 Internal loopback
1 0 ENDEC loopback for 10Base-T or MII loopback
1 1 223 loopback or others
Reserved.

VIA Technologies, Inc. Preliminary VT86C100A

ISR: Interrupt Status Register (0CH; Type=R/W)

This register reflects the NIC status. The host reads it to determine the cause of the interrupt
Individual bits are cleared by writing a "1" to the corresponding bit. It must be cleared after
power up.

Magic packet key received interrupt status
Port status change interrupt status
transmit abort interrupt status, this bit will be set while excessive collision
No more receive buffer to use
FIFO overflow condition, next packet race into FIFO with current packet
receiving FIFO overflow interrupt status
Transmit descriptor underflow while in early transmit mode or general I/O pin M10TENI

status change interrupt while GPIOEN=1, this interrupt can be used as PHY report the
link status change.
Indicates the received packet has filled the first data buffer.

CRC error or packet race tally counter overflow interrupt, software can maintain drivers
CRC error counter above 32 bit
PCI Bus error interrupt

Receive buffer unavailable
Transmit buffer underflow
Transmit error bit is set when a packet transmission is aborted due to excessive collisions.
This bit is set when a packet is received with one or more of the following errors:

1) CRC error, 2) Frame alignment error and 3) Missed packet.
This bit indicates that packet is transmitted with no errors.

This bit indicates that packet is received with no errors.

IMR Interrupt Mask Register (0EH; Type=R/W )

All bits correspond to the bits in the ISR register. Power up=all 0s. Setting individual bits will
enable the corresponding interrupts.

EEPROM Configuration and status Register Group

EECSR EEPROM Command Status Register (74H, Type=R/W)

EEPROM programming status

6 EMBP
5 LOAD

4 DPM
3 ECS
2 ECK
1 EDI
0 EDO

EEPROM embedded program enable, the VT86C100A will set this bit to zero after
programming complete.
Dynamic reload EEPROM content, the PAR[5-0] will be update

Direct program EEPROM
EEPROM interface chip select status
EEPROM interface clock status
EEPROM interface data in status
EEPROM interface data out status

VIA Technologies, Inc. Preliminary VT86C100A

MII port control and status Register Group

MIICR MII interface control register (070H, Type=R/W)

MII management port auto polling enable, MIICR has no effect while this set on

6 RCMD
5 WCMD

4 MDPM
3 MOUT
2 MDO
1 MDI
0 MDC

MIIAD MII CSR offset address register (071H, Type=R/W)

6 MSRCE

N
5 MDONE
4 MAD4
3 MAD3
2 MAD2
1 MAD1
0 MAD0

The MII management port address default value be (00001)b,

read enable to read PHY status, reset while complete and PHY status will be store in
register MII data register 0x72
write enable to program PHY, reset while PHY programmed completely

direct program mode enable, while MDPM be set , the WCMD and RCMD have no effect
MDIO output enable indicator while direct program mode
MII interface management port data output status
MII interface management port data input status
MII interface management port clock status

MII management port address bit 4
MII management port address bit 3
MII management port address bit 2
MII management port address bit 1
MII management port address bit 0

MIISR MII status register (06dH, Type=R/W)

GPIO1POL : General purpose I/O 1 pin output polarity, when this bit set as '1', the
GPIO1 pin output active high; set as '0', the GPIO1 pin output active low.

6 res
5 MFDC

4 PHYOPT
3 MIIERR
2 MRERR
1 LNKFL
0 SPEED

Reserve
MFDC : Accelerate the MDC speed when VT86C100A enter MII auto polling; MFDC set

as '0', MDC be normal speed; or MFDC set as '1' , MDC be 4 times speed.

PHYOPT : set 1 use default external PHY device address as 0001
MIIERR : PHY device coding error by insert RX_ERR, write to clear it.
MRERR : MII Management read error, write to clear it
LNKFL : Link fail in 10 or 100MHz
SPEED : Network speed, 0 as 100MHZ, 1 as 10MHz

PHYADR
MII configuration register (06cH, Type=R/W)

VIA Technologies, Inc. Preliminary VT86C100A

MII management port polling timer interval, timer unit be MDC clock cycle
MPO1 MPO0 clock
0 0 1024
0 1 512
1 0 128
1 1 64

5 res

4-0 PHYAD[

4-0]

PHY[4-0] : external PHY device address , these register bytes stored from EEPROM
loading when power up or EEPROM auto-reloading or can be programmed by software,
default as (00001)b

VIA Technologies, Inc. Preliminary VT86C100A

[This page left to blank]

VIA Technologies, Inc. Preliminary VT86C100A

R3

0

PCIVCC

CB8
22UF

1
2
3
4

PCIVCC PCIVCC AD28 MTXD2 AD11 AD10

-PRSNT1 AD24 MTXCK

-PRSNT2 AD22 MRDCK

PCICLK PCIVCC AD17 MRXD3 AD1 AD0

-REQ AD15 MDIO EECS -BPRD
PCIVCC -PME AD14 MD0 MD1
AD31 AD30 AD13 M10TEN MD2 MD3
AD29 AD12 PRTENL MD4

AD27 AD26 AD10 MD6 MD7
AD25 AD9 MA15 PRTENL PRTENH

-CBE3 IDSEL AD7 MA13
AD23 AD6 MA12

AD21 AD20 AD4 MA10
AD19 AD3 MA9

AD17 AD16 AD1 MA7 MA4 MA5

-CBE2 AD0 MA6 MA6 MA7

-IRDY -CBE3 MA4 SVSS

-DEVSEL -CBE1 MA2 MA10 MA11

-PERR IDSEL NC NC2

-CBE1 AD15 -DEVSEL MD4 MTXD2 MTXD1
AD14 -STOP MD3 MTXD0 MTXEN

AD12 AD11 PCICLK MD1 MTXCK MRXER
AD10 -INTA MD0 MRXCK MRXDV

AD8 -CBE0 -PERR
AD7 -PME TST MRXD0 MRXD1

AD5 AD4 NC
AD3 MDC MDIO

AD1 AD0 -INTA -PCIRST
PCIVCC PCIVCC PCICLK

5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49

52
53
54
55
56
57
58
59
60
61
62

PCI_CONB

CB5

CB7

22UF

22UF

P1

P2

B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36
B37
B38
B39
B40
B41
B42
B43
B44
B45
B46
B47
B48
B49

B52
B53
B54
B55
B56
B57
B58
B59
B60
B61
B62

PCI_CONA

1

A1

2

A2

3

A3

4

A4

5

A5

6

A6

7

A7

8

A8

9

A9

10

A10

11

A11

12

A12

13

A13

14

A14

15

A15

16

A16

17

A17

18

A18

19

A19

20

A20

21

A21

22

A22

23

A23

24

A24

25

A25

26

A26

27

A27

28

A28

29

A29

30

A30

31

A31

32

A32

33

A33

34

A34

35

A35

36

A36

37

A37

38

A38

39

A39

40

A40

41

A41

42

A42

43

A43

44

A44

45

A45

46

A46

47

A47

48

A48

49

A49

52

A52

53

A53

54

A54

55

A55

56

A56

57

A57

58

A58

59

A59

60

A60

61

A61

62

A62

22UF

22UF

-INTA AD27 MTXD1

-PCIRST AD18 MRXD2 AD3 AD2

-GNT AD16 MDC

AD28 AD11 PRTENH MD5

AD24 AD8 MA14 MA0 MA1

AD22 AD5 MA11

AD18 AD2 MA8 MA2 MA3

-FRAME MA5 MA8 SVDD

-TRDY -CBE2 MA3 MA9

-STOP -CBE0 MA1 MA12 MA13

PAR -TRDY MD5 MCOL MTXD3

AD13 PAR MD2

AD9 -PCIRST

AD6 NC2 MRXD2 MRXD3

AD2 HDRST HDRST M10TEN

-PCIRST

R1
0

22UF

C1 .1u
C2 .1u
C3 .1u
C4 .1u
C5 .1u
C6 .1u
C7 .1u
C12 .1u
C13 .1u
C11 .1u
C14 .1u
C15 .1u

22UF

-PME

CB1

CB2

CB3

CB4

R4

0

R5

0

U1

VT3043E

AD31 MCRS PAR -CBE1
AD30 MCOL AD15 AD14
AD29 MTXD3 AD13 AD12

AD26 MTXD0 AD9 AD8
AD25 MTXEN -CBE0 AD7

AD23 MRXER
AD21 MRXDV

AD20 MRXD0 AD6 AD5
AD19 MRXD1 AD4

-FRAME MD7

-IRDY MD6 TST MCRS

-GNT EECS

-REQ -BPRD

121

AD31

122

AD30

123

AD29

124

AD28

127

AD27

128

AD26

1

AD25

2

AD24

5

AD23

7

AD22

8

AD21

9

AD20

11

AD19

12

AD18

13

AD17

14

AD16

27

AD15

28

AD14

29

AD13

30

AD12

31

AD11

32

AD10

35

AD9

36

AD8

38

AD7

39

AD6

40

AD5

42

AD4

43

AD3

44

AD2

45

AD1

46

AD0

3

CBE3

16

CBE2

26

CBE1

37

CBE0

4

IDSEL

17

FRAME

18

IRDY

19

TRDY

20

DEVSEL

21

STOP

25

PAR

115

PCICLK

113

INTA

114

PCIRST

118

GNT

119

REQ

23

PERR

120

PME

10

VDD

22

VDD

34

VDD

47

VDD

56

VDD

65

VDD

76

VDD

87

VDD

97

VDD

108

VDD

117

VDD

125

VDD

R6

0

R7

0

R8

0

VSS57VSS66VSS77VSS88VSS

VSS

VSS

VSS

48

98

107

116

126

MCRS

MCOL
MTXD3
MTXD2
MTXD1
MTXD0

MTXE
MTXC
MERR
MRXC

MRXDV
MRXD0
MRXD1
MRXD2
MRXD3

MDIO

M10TEN
PRTENL
PRTENH

MD2/EECK

MD1/EEDI

MD0/EEDO

EECS
BPRD

HDRST

SVDD

SVSS

VSS6VSS15VSS24VSS33VSS41VSS

MDC

MA15
MA14
MA13
MA12
MA11
MA10

MA[15:0]

MD[7:0]

90
91
92
93
94
95
96
99
100
101
102
103
104
105
106
109
110

112
61
62

84
83
82
81
80
79
78

MA9

73

MA8

72

MA7

71

MA6

70

MA5

69

MA4

68

MA3

67

MA2

64

MA1

63

MA0

60

MD7

59

MD6

58

MD5

55

MD4

54

MD3

53
52
51

49
50

89

TST

86

NC2

85

NC

111

74

75

MA[15:0]

MD[7:0]

MCRS
MCOL
MTXD3
MTXD2
MTXD1
MTXD0
MTXEN
MTXCK
MRXER
MRXCK
MRXDV
MRXD0
MRXD1
MRXD2
MRXD3
MDC
MDIO

M10TEN
PRTENL
PRTENH

MA0 MA14 MA15

EECS

-BPRD
TST

NC2
NC

HDRST

SVDD -GNT

C10

C9

.O1u

10uF

SVSS AD27 AD26

1

AD25 AD24

3

-CBE3 IDSEL

5

AD23

7

AD22 AD21

9

AD20

11

AD19 AD18

13

AD17 AD16

15
17

-FRAME -IRDY

19

-TRDY -DEVSEL

21

-STOP

23

-PERR

25
27
29
31
33
35
37

39
41
43
45
47
49
51
53
55
57
59
61
63

65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101

103
105
107
109
111

R2

113

3.6

115

0805

117
119

C8
.1u

-REQ -PME

121

AD31 AD30

123

AD29 AD28

125
127

JP1

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41

43
45
47
49
51
53
55
57
59
61
63
65
67
69
71

73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113

115
117
119
121
123
125
127
129
131
133
135
137
139
141
143

HEADER 72X2

2
4
6

8
10
12
14

-CBE2

16
18
20
22
24
26
28
30
32
34
36
38
40
42

44
46
48
50
52
54
56
58
60
62
64
66
68
70
72

74
76
78
80
82
84
86
88
90
92
94
96
98

100
102
104
106
108
110
112
114

116
118
120
122
124
126
128
130
132
134
136
138
140
142
144

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38

40
42
44
46
48
50
52
54
56
58
60
62
64

66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102

104
106
108
110
112
114
116
118
120
122
124
126
128

VIA TECHNOLOGIES, INC.

|LINK
|2.SCH
|3.SCH

Title

VT3043E Bench Board

Size Document Number Rev

VT5134A A

C

Date: Sheet of

1 3Thursday, September 04, 1997

VIA Technologies, Inc. Preliminary VT86C100A

R42 V
R22
R23
R24

OSC2 50M 25M

1
2

50MHz/*25MHz

-PCIRST

HDRST

MTD972NS 840

V
V

OSC1

VCC

NC

OUT

GND

REFIN CLK25

L2
47uH

V

4

R22
75

3

R24

*75

U4A

1 2

74LS14

R51
33

C40
22u

R78

D9

R48

U3

33

82

MTXCK
MTXD3

MTXD2
MTXD1
MTXD0

MTXEN

TX_ER TXO+/TXU+

MCRS

MCOL

R23

0

.001u

MII_CRS TXU-

R54
33

R55

MRXD3
MRXD2
MRXD1
MRXD0

MRXCK
MRXDV
MRXER

MDC

MDIO

OSCIN

C17
10P

R50
33

RESET PUD01

ANAVCC PUD03

C16

33

R49 33

MII_RXER

R10 4.7K

MDC TXO+/TXU+
MDIO PRD+ TXO-

RESET RXI+
REFIN PSD-

CLK25
OSCIN P1

R21 4.7K

ANAVCC FGND

R56
0

R57
*0

C18

.1u

TX_CLK

75

TXD3

76

TXD2

77

TXD1

78

TXD0

74

TX_EN

73

TX_ER

66

CRS_P2

65

COL

55

RXD3

56

RXD2

57

RXD1

58

RXD0

62

RX_CLK

64

RX_DV

63

RX_ER_P4

43

RX_EN

72

MDC

67

MDIO

44

RESET

86

REFIN

81

CLK25M

2

OSCIN

34

X2

33

X1

96

VCC_A

39

VCC_A

51

VCC_A

70

PCSVCC_A

97

GND_A

40

GND_A

52

GND_A

71

PCSGND_A

59

VCC_B

68

VCC_B

79

VCC_B

84

REFVCC_B

60

GND_B

61

RCLKGND_B

69

GND_B

80

GND_B

85

REFGND_B

18

RXVCC_C

22

TDVCC_C

31

PLLVCC_C

32

OVCC_C

19

RXGND_C

27

TDGND_C

30

PLLGND_C

35

OGND_C

12

CRMVCC_D

15

ECLVCC_D

9

ANAVCC_D

87

CGMVCC_D

3

OSCGND_D

11

CRMGND_D

10

ANAGND_D

88

CGMGND_D

DP83840A

Physical Layer

C19

.1u

C32

.1u

C21

C20

.1u

C33

.1u

C22

.1u

.1u

C26

C27

.1u

.1u

LED_TX
LED_RX
LED_LK

LED_P/F

LED_COL

SPEED_10

TXU+

TXU-

TXS+

TXS­RXI+

REQ

SD+

ENCSEL_P1

LBEN_P0

REPEATER

10BTSER

BPALIGN

BP4B5B
BPSCR

J_TD0

J_TDI

J_TRST

J_TCLK

J_TMS

PHYAD3

RES_0
RES_0
RES_0
RES_0

C23

.1u

C28

.1u

42
41
38
37
36

54

SPEED10

26

R12 10
R13

25

10

R15

24

*0

23

R16 *0

21
20

RXI-

29
28

RTX

17

TD+

16

TD-

5

RD+

6

RD-

8
7

SD-

53
49

95

AN0

46

AN1

47

98
99
100
1

50
91
92
93
94

89

13

NC

14

NC

83

NC

4
45
48
90

C42
.1u

C29

.1u

C37 .1u

PUD01

R81

20

R82
22

AN0 SPEED10
AN1

R63

4.7K

R25
510

PUD02

R9
10K

P3/100

PUD03

C24

C25

.1u

.1u

C30

C31

.1u

.1u

PWR

D1 TX
D2 RX
D3 LK
D4 P/F
D5 COL

D6 100

TXO-

RXI+
RXI-

C38
.1u

PTD+
PTD-

PRD­PSD+ RXI-

P0

R32
*0

R33
0

R37
*0

R42

*10K

C41
*.1u

RP2

130

1 2

*Use RP1,RP2 or Only RP2 -> 510

510

RN2
510

1

2

3

4

5

6

7

8

R52

510

R53
510

R35
0

U2

26

VCC

23

EXTVCC

13

VCC

15

PMRD+

16

PMRD-

25

PMID+

24

PMID-

20

SD+

21

SD-

12

ENCSEL

19

LBEN

17

EQSEL

18

/CDET

14

GND

22

GND

DP83223

Transceiver

TXO+/TXU+
TXU­TXO-

PRD+

3

PRD-

4

PSD- PUD01

5

PSD+ P1

6

PTD- AN1 PUD02

7

PTD+

TXVCC
TXVCC

RXVCC
RXVCC

TXO+

TXO-

TXGND
TXGND

RXGND
RXGND

TXREF

C48
39p

RP1
82

12
3
4
5
6
7

RXI+

RXI-

RXI+

RXI-

L3 FB

L4
FB

C47
39p

5
11

4
27

9
8

2
1

7
10

3
28

6

0/75

P0

MII_CRS

P3/100

MII_RXER

R11

0

R79 0/75

R80

39/49.9

1

2
3

16
14
15

C35
.1u

R31
10

C34
.1u

R19

RD+

CT
TD+

TD-

L1

PT4171

R40

R41

*49.9

*49.9

1%

1%

R17 10/0

R18

10/0
R20
39/49.9

C39
.1u

R14

*2K

7

RX+

CT

5
6

RX­TX+

10

CM

12
11

TX-

R27
75

R58

1

10K

2

PHY0

3

R59

1

10K

2

PHY1

3

R60

1

10K

2

PHY2

3

R61

1

10K

2

PHY3

3

R62

1

10K

2
3

VIA TECHNOLOGIES, INC.

PHY4

Title

Size Document Number Rev

C

Date: Sheet of

C43

*10p

R38

R39

47.5 1%

47.5 1%

3 1

3 1

2N3904

Q3
R36

510

R29

75

R30
75

AN0 PUD03

'*' for Myson PHY and Transceiver

NS or Myson's PHY & Transceiver

VT5134A A

2

2

2N3904
Q2

J1

RJ-45

1
2
3
4
5
6
7
8

910111213

R28
75

CX1
.1u

1
2

AN0

3

1
2

AN1

3

RN1
510

1

2

3

4

5

6

7

8

P3/100

3 1

2

2N3904
Q1

14

R26

R44 *4.7K
R43 *4.7K

2 3Thursday, September 04, 1997

4.7K

R47 *4.7K
R45 *4.7K
R46 *4.7K

TX_ER

VIA Technologies, Inc. Preliminary VT86C100A

M10TEN

PRTENH

PRTENL

MD[7:0]

MA[15:0]

EECS

-BPRD

J4

1

EECS MD7

3 4

-BPRD MD6

5 6
7 8

MD[7:0]

MA[15:0]

R66

4.7K

91110

13 14

MD1 MD0
MD2
EECS

R67

4.7K

R64
0

R65
0

TST

NC2

NC

MA14
MA15

RP4

2

3
4
5
6
7

12

8
9

1615

10K

U5

3

DI

2

SK

1

CS

93C46

10

MA0 MD0
MA1 MD1
MA2 MD2
MA3 MD3
MA4 MD4
MA5 MD5
MA6 MD6
MA7 MD7

25

MA8

24

MA9

21

MA10

23

MA11
MA12

26

MA13

27

20

-BPRD

22

J5

12

4

DO

8

VCC

5

GND

U6

A0

9

A1

8

A2

7

A3

6

A4

5

A5

4

A6

3

A7
A8
A9
A10
A11

2

A12
A13
A14

1

A15
CE

OE

27512

RP6

1
2
3
4
5
6
7
8

O0
O1
O2
O3
O4
O5
O6
O7

12
3
4
5
6
7
8
9

4.7K

11
12
13
15
16
17
18
19

J2

1
3 4
5 6

MD5

7 8

MD4

91110

MD3
MD2

13 14

MD1
MD0

TP1

PCI_PWR PCI_GOOD

1

1N4148

C46

.1u

RP5

2

3
4
5
6

12

7
8

1615

9

4.7K

D8

1N4148

D7

.1u

-PME

C45

R77
0

TP5

AUX_PWR

1

R68

0

12

U8A

1 2

74HC14

R76

4.7K

U8D

74HC14

R69

0

J3

98

1
2
3
4

1
2
3
4
5
6
7
8

U7

REF
RESIN
CT
GND

TL7705A

R70

0

3
4
5
6
7
8
9

3 4

U8C

74HC14

P3

1

AUX5V

2

NC

3

GND

4

WAKUP

5

GND

6

AUX5V

AUX5V_CON

RP3

10K

U8B

74HC14

R75

100K

RESET
RESET

56

SENSE

12

TP2

1

3 1

Q4

2

C44

100p

8

VCC

7
6
5

NPN

ISOLATE

R74
10K

R71

10K

ALTRST

VIA TECHNOLOGIES, INC.

Title

VT3043E Strapping

Size Document Number Rev

VT5134A A

C

Date: Sheet of

TP3

1

R72

7.8K

R73

10K

TP4

1

3 3Thursday, September 04, 1997