or translated into any language, in any form or by any means, electronic, mechanical, magnetic,
optical, chemical, manual or otherwise without the prior written permission of Via Technologies
Incorporated.
The VT86C100A may only be used to identify products of Via Technologies.
All trademarks are the properties of their respective owners.
Disclaimer Notice:
No license is granted, implied or otherwise, under any patent or patent rights of Via Technologies.
Via Technologies makes no warranties, implied or otherwise, in regard to this document and to the
products described in this document. The information provided by this document is believed to be
accurate and reliable to the publication date of this document. However, Via Technologies
assumes no responsibility for any errors in this document. Furthermore, Via Technologies assumes
no responsibility for the use or misuse of the information in this document and for any patent
infringements that may arise from the use of this document. The information and product
specifications within this document are subject to change at any time, without notice and without
obligation to notify any person of such change.
* Single chip Fast Ethernet controller for PCI bus interface
--compliant to PCI v2.1 with optional delay transaction and sub-vendor, sub-system- ID
--Provides a direct connection to PCI bus
--Supports two network ports : 10/100 M MII interface
* High performance PCI mastering structure
-- VIA self-define 128 bytes memory I/O or register I/O based command and status register
-- Software oriented chain structure description to minimize hardware complexity
-- Include on chip bus master DMA with programmable burst length for low CPU utilization
-- Dynamic transmit packet auto queuing for back auto queuing for bac for back to back transmissin
-- Programmable activity polling intervals for description DMA
-- Programmable DMA arbitration priority to minimize overflow under flow condition
-- Support early receive and early transmit interrupt for software parallel processing
-- Interrupt controllable by receive/transmit descriptor list for saving interrupt service time
* Provides standard 100-M bits MII interface
--Support 100Base-TX with CAT5 UTP, STP and fiber cables
-- Support 100Base-T4 with CAT3, CAT4, CAT 5 UTP, STP
* 10/100Mhz full duplex, half duplex operation
* Contains two deeper 2K bytes FIFO for receive and transmit controller both supports bursts of
up to full Ethernet length
-- Programmable receive and transmit FIFO threshold control for optimize PCI throughput
* Flexible dynamically load EEPROM algorithm.
--Load after power-up
--Dynamic auto reload
--Embedded programming for configure modification
--Dynamic direct programming for manufacturing
* Support physical, Broadcast, Multicast address filtering using hashing function
* Support Magic packet and wake on address filtering
* Support external Bootrom up to 64K bytes no external address latch
* Software controllable power down feature
* Single +5V supply, 0.5um standard CMOS technology
* 128 pin PQFP package
AD31-0I/OAddress/Data are multiplexed on the same PCI pins. A bus transaction
consists of an address phase followed by one or more data phases. The
address phase is the clock cycle in which FRAME# is asserted. Write
data is stable and valid when IRDYB is asserted and read data is stable
and valid when TRDYB is asserted.
PCICLKIPCICLK provides timing for all transactions on PCI and is an input pin
to every PCI device.
INTA#ODINTA# is an asynchronous signal which is used to request an interrupt
PCIRST#IWhen PCIRST# is asserted low, the VT86C100A chip performs an
internal system hardware reset. PCIRST# may be asynchronous to CLK
when asserted or deasserted. It is recommended that the deassertion be
synchronous to guarantee clean and bounce free edge.
CBE#[3:0]IBus Command/Byte Enables are multiplexed on the same PCI pins.
During the address phase of a transaction, CBE3-0B define the Bus
Command. Burring the data phase, CBE3-0B are used as Byte Enables.
The Byte Enables define which physical byte lanes carry meaningful
data. CBE0B applies to byte 0 and CBE3B applies to byte 3.
IDSELIUsed as a chip select during PCI configuration cycle.
FRAME#I/OCycle Frame is driven by the current master to indicate the beginning
and duration of an access. FRAME# is asserted to indicate a bus
transaction is beginning. While FRAME# is asserted, data transfers
continue. When FRAME# is deasserted, the transaction is in the final
data phase.
IRDY#I/OInitiator Ready indicates the initiating agent's ability to complete the
current data phase of the transaction. IRDY# is used in conjunction with
TRDY#. A data phase is completed on any clock when both IRDY# and
TRDY# are asserted. During a write, IRDY# indicates that valid data is
present on AD31-0. During a read, it indicates the master is prepared to
accept data. Wait cycles are inserted until both IRDY# and TRDY# are
asserted simultaneously.
TRDY#I/OTarget Ready indicates the target's agent's ability to complete the current
data phase of the transaction. TRDY# is used in conjunction with
IRDY#. A data phase is completed on any clock when both IRDY# and
TRDY# are asserted. During a read, TRDY# indicates that valid data is
present on AD31-0. During a write, it indicates the target is prepared to
accept data. Wait cycles are inserted until both IRDY# and TRDY# are
asserted simultaneously.
DEVSEL#I/ODevice Select, when actively driven, indicates the driving device has
decoded its address as the target of the current access. As an input,
DEVSEL# indicates whether any device on the bus has been selected.
STOP#I/OVT86C100A drives STOP# to disconnect further traction.
Page 7
VIA Technologies, Inc.Preliminary VT86C100A
25
PART/SParity is even parity across AD31-0 and CBE3-0B. PAR is stable and
valid one clock after the address phase. For data phases PAR is stable
and valid one clock after either IRDY# is asserted on a write transaction
or TRDY# is asserted on a read transaction.
118
GNT#IBus grant asserts to indicate to the VT86C100A that access to the bus is
granted.
119
REQ#OBus request is asserted by the bus master indicate to the bus arbiter that
it wants to use the bus.
23
120
111
PERR#I/OParity error asserts when a data parity error is detected
PME#OPower management event interrupt
HDRSTOWhen PCIRST# is asserted low, the VT86C100A chip performs an
internal system hardware reset. Then HDRST is asserted high for
external device reset signal like PHY device.
Network Interface
91MCOLICollision detect when the external PHY device
90MCRSICarrier sense is asserted by the external PHY when the media is active
92-95MTXD[3-0]OMII 4 parallel transmit data lines. This data be synchronized to assertion
by the MTXC signal
96MTXENOTransmit enable signals that the transmit is active in the MII port to an
external PHY device
99MTXCIMII transmit clock supports the 25mhz or 2.5mhz transmit clock
supplied by the external PMD device. This clock should always be
active.
100MERRIMII receive error asserts when a data decoding error is detected by
external PHY device.
101MRXCIMII receive clock supports the 25mhz or 2.5mhz clock. This clock is
recovered by the PHY.
102MRXDVIMII data valid
103-106MRXD[0-3]IFour parallel receive data lines. This data be driven from external PHY
be synchronized with MRXC signal.
109MDCOMII management data clock be soured by VT86C100A MDC bit
(MIIR:0) to the external PHY devices as timing reference for the
MDIO signal.
110MDIOI/OMII management data input/output, read from MDI bit (MIIR:1) or
written from MDO bit (MIIR:2)
112GPIOI/OGPIO
External Memory Support & General purpose I/O support
49EECSOEEPROM Chip Select: Chip select signal for the external EEPROM
when a EEPROM is used to provide the configuration data and
Ethernet Address. A 100K pull-up resistor is connected.
50BPRD#OBoot PROM Read: Read the Boot ROM on the memory support data
bus.
51MD0/
EEDO
52MD1/
EEDI
I/OBootrom data 0
Serial ROM Data output
O/OBootrom data 1
Serial ROM Data input
53MD2/ EECLKO/OBootrom data 2
Serial ROM Clock signal
54-55,58-
MD3-7I/OBootrom Data [3-7] :
60
Page 8
VIA Technologies, Inc.Preliminary VT86C100A
63-64,67-
MA0-MA15OBootrom address line [0-15]
73,78-
84
85GPIO1/AUXP
IOGeneral purpose input and output 1 : usually as Magic key interrupt line
ME
112GPIO2/LKCIOGeneral purpose input and output 2, this pin usually as link change status
from external PHY device.
Power Supply & Ground
10,22,34,47,
56,65,76,
87,97,108
,117,125
6,15,24,33,
41,48,57
,66,75,7
7,88,98,
107,116,
126
VDD, VDDAPPositive 5V Supply: Supply power to Internal digital logic, Digital I/O
pads, and TD, TX pads. Double bonding may be required.
VSS, VSSAGNegative Supply: digital ground. Multiple bonding pads are
required to separate core and I/O pads ground.
Page 9
VIA Technologies, Inc.Preliminary VT86C100A
FUNCTIONAL DESCRIPTIONS
1. GENERAL DESCRIPTION
The VT86C100A Rhine ACPI PCI bus master 100 M FAST Ethernet controller is CMOS VLSI designed for
easy implementation of CSMA/CD IEEE 802.3u 100M local area networks. Significant features include:
twisted-pair interface, PCI Plug&Play compatibility, 32 bit bus mastering, powerful buffer management and
Early Interrupt Receive/Transmit.
The VT86C100A integrates the entire bus interface of PCI systems. Setting hardware jumpers or software
configures the VT86C100A bus interface. The VT86C100A also complies with PCI specification v2.1.. The
VT86C100A supports the Media Independent Interface (MII) network interface.
1.1 FIFO AND CONTROL LOGIC
The VT86C100A incorporates two independent 2K bytes deeper FIFO for transmit or receive data from
system interface or to the network interface, providing temporary storage of data, free host system from the
real-time demands on network.
The VT86C100A enhanced the FIFO management logic to handle received data packets up to four packets
before transfer to system data buffer. This ability reduce the packets losing due to PCI bus mastering abrition
latency.
2. NETWORK INTERFACE
The VT86C100A Rhine ACPI support one MII interface
2.1 MII Interface
The MII interface is an IEEE 802.3 compliant interface that provides a simple and easy interconnection
between the MAC layer and PHY device. This interface has support the following characteristics :
• Support both 10M and 100M data rate.
• Contains data and synchronous clock
• 4-bit independent receive and transmit data.
• Uses TTL signal levels and compatibles with common CMOS processes.
Page 10
VIA Technologies, Inc.Preliminary VT86C100A
3.EEPROM Interface and Programming
VT86C100A uses an 93C46 to store configuration data and Ethernet address.
Note 1. The word on location 03H is optional to user's application requirement.
Note 2. Programming 73H into the upper address is required to protect the Ethernet address from being destroyed accidentally
Note 3. The word on location 04H, 05H is sub-System ID, sub-Vendor ID in PCI specification 2.1.
Reserved for 93C46
.
.
.
.
.
.
.
Reserved for 93C46
.
.
.
.
.
.
.
3.2. DIRECT PROGRAMMING OF EEPROM
The VT86C100A features a easy way to program external EEPROM in-situ. When the RESET is active and if
the upper byte of 0FH on EEPROM is not 73H, the EEPR bit will not be set to indicate that the current
EEPROM has not been programmed yet. This will allow the VT86C100A to enter Direct Programming mode
if EELOAD is also set. In this mode the user can directly control the EEPROM interface signals by writing to
the ECSR Port and the value on the EECS, ESK and EDI bits will be driven onto the EECS, SK(MD2), and
DI(MD1) outputs respectively. These outputs will be latched so the user can generate a clock on SK by
repetitively writing 1 then 0 to the appropriate bit. This can be used to generate the EEPROM signals as per
the 93C46 data sheet.
To read the EEPROM data, users have to generate EEPROM interface signals into EECS, DI and SK as
described above and in the mean time read the data from DO(MD0) input via pin SD0. Reading Data
Transfer Port during programming will not affect the latched data on EECS, SK, and DI outputs. When the
Page 11
VIA Technologies, Inc.Preliminary VT86C100A
EEPROM has been programmed and verified (remember to program the upper byte of 0EH & 0FH with
73H), the user must give VT86C100A a power-on reset to return to normal operation and to read in the new
data.
The Direct Programming mode is mainly used for production to program every bit of the EEPROM. Once the
upper byte of 0EH has been programmed with 073H and a power-on reset has been performed, there is no
way to change the contents of EEPROM except Configuration Registers A, B, and C, which will be discussed
in the following paragraph. For more information, refer to EECSR.
3.3. EMBEDDED PROGRAMMING OF EEPROM
If the upper byte of 0FH of EEPROM has been programmed to 073H when VT86C100A is loading the
EEPROM data during power-on reset, the EEPR bit of Signature Register will be set to prohibit the Direct
Programming mode. However, the user can still program the configuration registers A, B, and C using the
Embedded Programming mode by following the routine specified in the pseudo code below. This operation
will work regardless of the value of EECONFIG. The setting of the EELOAD bit of Configuration Register B
starts the EEPROM write process. Care should be taken not to accidentally modify the POL and GDLNK bits
because these two bits return the value indifferent from the setting. This programming process is ended when
the EELOAD bit goes to zero.
The VT86C100A provides an one level power down mode. The BIOS or Network OS device driver can
configure Register A to diagnostic mode then set the Power-on bit of the diagnostic port to "on." When the
VT86C100A is in Power down mode, all power to the PCI interface is cut off and the chip clock is stopped.
Other registers are read only. Only the diagnostic port is read/writeable.
The VT86C100A can store one “Magic Key” (6 bytes Ethernet address) as external trigger event. When
VT86C100A received one Magic Key address packet, the PME# or GPIO1 will be generated to system.
These signal can be asserted to ATX power PS-ON (refere to ATX specification v2.01) or mother board wake
up interrupt line like ring-in.
Page 13
VIA Technologies, Inc.Preliminary VT86C100A
6. BUFFER MANAGEMENT & HOST COMMUNICATION
The VT86C100A provides an simply and effective buffer management and host communication
method through the PCI Bus mastering : There are two descriptor lists, one for receive and one for transmit.
The base of these two list are pointed into the CRDA (18h) and CTDA (1ch) registers.
The descriptor list reside in the host physical memory address space with double word boundary.
And each descriptor lists just point to one single buffer, but a data buffer consists of either an entire frame or
part of a frame. Data chain can be enabled or disabled by DES1 C bit. Data buffer also reside in host physical
memory double word boundary space.
The device driver can make the last descriptors next link be point to first descriptor address, become
a ring buffer structure.
Providing single buffer, one byte-count buffers, and next descriptor address. And Chain bit control
span multiple data buffers data chain to be compatible various types of memory management schemes..
Page 14
VIA Technologies, Inc.Preliminary VT86C100A
312315
O
RDES0
0000
RDES1ReserveReserveC0000
RDES2Rx Data Buffer Start Address
RDES3Next Descriptor Address
FIGURE 6-2 THE RECEIVE DESCRIPTOR FORMAT :
6.1.2. RECEIVE DESCRIPTOR 0 (RDES0)
RDES0 contain the received frame status, the frame length and the descriptor ownership information.
FLNG[10:0]RSR1RSR0
Owner : This bit control by driver, 1 to identify this descriptor own by
VT86C100A controller, 0 means this descriptor be a free descriptor; Driver must
set this bit be zero when initialed.
Extend Frame Length : Extend byte count for no-normal size Ethernet frame
Frame Length : Received frame length,
RLNG[10:0]
Received OK : The VT86C100A received a good packet from network.
Multicast Address Received : VT86C100A MAC received multicast address
packet
Boardcast Address Received : VT86C100A MAC received boardcast address
packet
Physical Address Received : Physical address received
CHAIN : means of chain buffer,
Start of Packet : In descriptor ring structure, STP=EDP=1 single buffer
descriptor, or chained buffer structure be follows :
STP EDP Description
1 1 Single buffer descriptor
1 0 First buffer descriptor, further buffer chained
0 1 Chained buffer packet end
0 0 X
End of Packet : End of Packet buffer
Receive Status Register 0 :
Buffer Error : Receive Buffer Error
System bus error :
Runt Packet Received :
Long Packet Received :
FIFO Overflow :
Frame Align Error :
CRC Error : received frame CRC checksum error
Receive Error : this bit be set by CRC error or frame alignmnet error or FIFO
overflow or System bus error.
Page 15
VIA Technologies, Inc.Preliminary VT86C100A
6.1.3. RECEIVE DESCRIPTOR 1 (RDES1)
RDES1 contain the interrupt control enable, the chained frame identical and the receive buffer
fragment size information.
Interrupt Control : This bit support for interrupt PACEing , set 1 mean the
VT86C100A received this descriptor will generate the interrupt.
Chain : Chain buffer , this bit be set to 1 means there are chained buffer in next
descriptor
Extend Fragment of Frame Length : must be zero now.
Rx buffer Size : Receive buffer size for this descriptor, the total byte count of
whole frame will be stored in last descriptors
6.2.1. TRANSMIT DESCRIPTORS
312315
RDES0
O
RDES1ReserveTCRC0000
RDES2Tx Data Buffer Start Address
RDES3Next Descriptor Address
FIGURE 6-3 THE TRANSMIT DESCRIPTOR FORMAT
ReserveTSR1TSR0
TLNG[10:0]
6.2.2. TRANSMIT DESCRIPTOR 0 (TDES0)
DES0 contain the received frame status, the frame length and the descriptor ownership information.
Owner : This bit control by driver, 1 to identify this descriptor own by
VT86C100A controller, 0 means this descriptor be a descriptor waiting for
transmit; Driver must set this bit be zero when initialed.
Transmit Status Register 1
Transmit OK : This bit be 1 for transmission error, the transmit include
following
- internal FIFO under-flow
- excessive collision (ABT)
- late collision (OWC)
- carrier sense lost (CRS)
14JABJabber : This bit will set high if Jabber condition happens. Writing to this bit has
no effect
System Error : VT86C100A MAC experience error master abort, target abort,
parity error.
12Reserve
11Reserve
Page 16
VIA Technologies, Inc.Preliminary VT86C100A
10CRS
9OWCLate Collisions : This bit is set when late collision occurred.
8ABTTransmit Abort : transmit module abort after excessive collision.
7-0TSR0
Carrier Sense lost bit is set when the carrier is lost during the transmission of a packet.
Transmit Status Register 0
CD heartbeat : this bit only effective in 10Base-T mode. When set, this bit
indicates a heartbeat collision check failure.
Collision retry count : this 4-bits counter indicates the number of collisions that
occurred
FIFO under-flow : this bit set indicates that the transmitter aborted by transmit
FIFO encountered an empty while transmitting a frame.
Deferred: When set, indicates that the VT86C100A had to defer while ready to
transmit a frame because carrier was asserted.
6.2.3. TRANSMIT DESCRIPTOR 1 (TDES1)
DES1 contain the transmit status, the frame length and the descriptor ownership information.
Transmit Configure Register
Interrupt Control : This bit support for interrupt PACEing , set 1 mean the
VT86C100A received this descriptor will generate the interrupt.
End of Packet : End of Packet buffer
Start of Packet : In descriptor ring structure, STP=EDP=1 single buffer
descriptor, or chained buffer structure be follows :
STP EDP Description
1 1 Single buffer descriptor
1 0 First buffer descriptor, further buffer chained
0 1 Chained buffer packet end
0 0 X
CRC disable : The VT86C100A transmitter will disable generated the CRC
when this set 1.
Chain : Chain buffer
Extend Fragment of Frame Length : must be zero now.
Transmit buffer size : the fragment of frame buffer size
6.3 Buffer Structure and Interrupt Control
data consists of an entire frame or part of a frame, but it cannot exceed a single Ethernet frame size. Buffers
contain only data; All buffer status is maintained in the descriptor . Data chaining can be enable or disable by
Chain bit in DES1[15]. The interrupt control also can be enable or disable by DES1[23]
Page 17
VIA Technologies, Inc.Preliminary VT86C100A
6.3.1 Multiple Chained buffer structure
The VT86C100A can support multiple chain buffer for direct map to OS`s data buffer. The VT86C100A bus
mastering module will direct move the data from network to the OS`s data buffer or direct transmit the data in
OS`s buffer onto network not necessary move to a temperate data buffer. But the data buffer must be double
word aligned. In this multiple chained buffer structure, the first data buffer descriptor Chain
Simple Ring Buffer Structure
0
0
F0
F1
0
F2
Figure 6 : Ring buffer and multiple buffer structure
Multiple Buffer Frame
C
F0
C
F0
F0
0
C=DES1[15]
Page 18
VIA Technologies, Inc.Preliminary VT86C100A
6.3.2 Interrupt Control
The VT86C100A can controllable the receive descriptors and transmit descriptor for what the interrupt
occurred.
The IC bit (DES1[23]) be set 1, the receive or transmit interrupt will be generate the interrupt no matter the
frame been complete received or transmitted. This feature will enable the OS pre-fetch the frame header or
saving the interrupt service overload.
C
I
ER Interrupt
Here
Interrupt
Here
C
0
0
F0
F0
F0
I
C
C
I
0
F1
F2
Interrupt
Here
Save this
interrupt
0
I
F3
Interrupt
Here
Figure 7. The Interrupt Control of VT86C100A
Page 19
VIA Technologies, Inc.Preliminary VT86C100A
VT86C100A REGISTERS
Group 1 : Internal Command Status Register (CSR) Layout
JUMPER : Jumper mode to select PHY and operation mode
EELOAD : Enable EEPROM embedded and direct programming
MRWAIT : Master read insert one wait state 2-2-2-2
MWWAIT: Master write insert one wait state 2-2-2-2
RXARBIT : the receiving FIFO DMA will be interleave to transmitting
n/aBoot PROM Select: Select size at which boot PROM begins and the
size
Bit2Bit1Bit0Size
000No Boot PROM
0018K
01016K
01132K
1X X64K
BTSEL : Bootrom timing select
DLYEN : Delay transaction while memory read Bootrom
BROPT : set Bootrom address line above Bootrom size selected to logic
1
for small size Bootrom
Page 23
VIA Technologies, Inc.Preliminary VT86C100A
MBA : Modify back off algorithm
CAP : Capture effect back off
CRADOM : Random back off algorithm
4MAGICn/aMAGIC : Turn on Magic key
DIAG :
7GPIOENn/aGPIOEN : Turn on GPIO2 input status change monitor
Page 24
VIA Technologies, Inc.Preliminary VT86C100A
VT86C100A Command Status Registers
MAC command and status register Group
CR0:Command Register 0 (08H; Type=R/W)
This register is used to select register pages, enable or disable remote DMA operation and issue
commands.
Reserved
6RDMD
5TDMD
4TXON
3RXON
2STOP
1STRT
0INIT
CR1:Command Register 1 (09H; Type=R/W)
This register is used to select register pages, enable or disable remote DMA operation and issue
commands.
This bit indicates that the VT86C100A receive poll demand enable
This bit indicates that the VT86C100A transmit poll demand enable
This bit indicates that the VT86C100A start transmit state while STRT bit on
This bit indicates that the VT86C100A start receive state while STRT bit on
This bit indicates that the VT86C100A into STOP state , this bit set by SFRST bit or
hardware reset
This bit indicates that VT86C100A enter the start command.
Initialize Start : When set on the VT86C100A start to set its bus master register the start
This bit is set when VT86C100A enters reset state and is cleared when a start command is
issued to the CR1. It is also set when receive buffer overflows or system error.
6-4RES
3DPOLL
2FDX
1ETEN
0EREN
Reserved
Disable transmit auto polling
This bit set MAC to full duplex in 10BaseT or 100BaseT mode
Early transmit mode enable while CFGD[1] be enable, this bit be clear while hardware
reset only
Early receive mode enable while CFGD[0] be enable, this bit be clear while hardware reset
only
This register reflects the NIC receive configuration and reset by hardware reset and software reset
BitSymbolDescription
7RRSF
6-5RFT[1-0]
4PRO
3AB
2AM
Receive store and forward
Receive FIFO Threshold.
RRFT2 RRFT1 RRFT0 Threshold
0 0 0 64 bytes
0 0 1 32
0 1 0 128
0 1 1 256
1 0 0 512
1 0 1 768
1 1 0 1024
1 1 1 Receive store and forward
If PRO=1, all packets with physical destination address are accepted. If PRO=0, physical
address must match the node address programmed in PAR0-5
If AB=1, packets with broadcast destination address are accepted. If AM=0, packets with
broadcast destination are rejected.
If AM=1, packets with multicast destination address are accepted. If AM=0, packets with
multicast destination are rejected.
Page 25
VIA Technologies, Inc.Preliminary VT86C100A
1AR
0SEP
If AR=1, packets smaller than 64 bytes are accepted. If AR=0, packets smaller than 64 are
rejected.
If SEP=1, packets with receive errors are accepted. If SEP=0, packets with receive errors
are rejected.
Back-off priority selection : change the back off algorithm as National specification
Loopback mode select for transmit :
0 0 Normal
0 1 Internal loopback
1 0 ENDEC loopback for 10Base-T or MII loopback
1 1 223 loopback or others
Reserved.
Page 26
VIA Technologies, Inc.Preliminary VT86C100A
ISR: Interrupt Status Register (0CH; Type=R/W)
This register reflects the NIC status. The host reads it to determine the cause of the interrupt
Individual bits are cleared by writing a "1" to the corresponding bit. It must be cleared after
power up.
Magic packet key received interrupt status
Port status change interrupt status
transmit abort interrupt status, this bit will be set while excessive collision
No more receive buffer to use
FIFO overflow condition, next packet race into FIFO with current packet
receiving FIFO overflow interrupt status
Transmit descriptor underflow while in early transmit mode or general I/O pin M10TENI
status change interrupt while GPIOEN=1, this interrupt can be used as PHY report the
link status change.
Indicates the received packet has filled the first data buffer.
CRC error or packet race tally counter overflow interrupt, software can maintain drivers
CRC error counter above 32 bit
PCI Bus error interrupt
Receive buffer unavailable
Transmit buffer underflow
Transmit error bit is set when a packet transmission is aborted due to excessive collisions.
This bit is set when a packet is received with one or more of the following errors:
1) CRC error, 2) Frame alignment error and 3) Missed packet.
This bit indicates that packet is transmitted with no errors.
This bit indicates that packet is received with no errors.
IMR Interrupt Mask Register (0EH; Type=R/W )
All bits correspond to the bits in the ISR register. Power up=all 0s. Setting individual bits will
enable the corresponding interrupts.
EEPROM Configuration and status Register Group
EECSR EEPROM Command Status Register (74H, Type=R/W)
EEPROM programming status
6EMBP
5LOAD
4DPM
3ECS
2ECK
1EDI
0EDO
EEPROM embedded program enable, the VT86C100A will set this bit to zero after
programming complete.
Dynamic reload EEPROM content, the PAR[5-0] will be update
Direct program EEPROM
EEPROM interface chip select status
EEPROM interface clock status
EEPROM interface data in status
EEPROM interface data out status
Page 27
VIA Technologies, Inc.Preliminary VT86C100A
MII port control and status Register Group
MIICR MII interface control register (070H, Type=R/W)
MII management port auto polling enable, MIICR has no effect while this set on
6RCMD
5WCMD
4MDPM
3MOUT
2MDO
1MDI
0MDC
MIIAD MII CSR offset address register (071H, Type=R/W)
6MSRCE
N
5MDONE
4MAD4
3MAD3
2MAD2
1MAD1
0MAD0
The MII management port address default value be (00001)b,
read enable to read PHY status, reset while complete and PHY status will be store in
register MII data register 0x72
write enable to program PHY, reset while PHY programmed completely
direct program mode enable, while MDPM be set , the WCMD and RCMD have no effect
MDIO output enable indicator while direct program mode
MII interface management port data output status
MII interface management port data input status
MII interface management port clock status
MII management port address bit 4
MII management port address bit 3
MII management port address bit 2
MII management port address bit 1
MII management port address bit 0
MIISR MII status register (06dH, Type=R/W)
GPIO1POL : General purpose I/O 1 pin output polarity, when this bit set as '1', the
GPIO1 pin output active high; set as '0', the GPIO1 pin output active low.
6res
5MFDC
4PHYOPT
3MIIERR
2MRERR
1LNKFL
0SPEED
Reserve
MFDC : Accelerate the MDC speed when VT86C100A enter MII auto polling; MFDC set
as '0', MDC be normal speed; or MFDC set as '1' , MDC be 4 times speed.
PHYOPT : set 1 use default external PHY device address as 0001
MIIERR : PHY device coding error by insert RX_ERR, write to clear it.
MRERR : MII Management read error, write to clear it
LNKFL : Link fail in 10 or 100MHz
SPEED : Network speed, 0 as 100MHZ, 1 as 10MHz
PHYADR
MII configuration register (06cH, Type=R/W)
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VIA Technologies, Inc.Preliminary VT86C100A
MII management port polling timer interval, timer unit be MDC clock cycle
MPO1 MPO0 clock
0 0 1024
0 1 512
1 0 128
1 1 64
5res
4-0PHYAD[
4-0]
PHY[4-0] : external PHY device address , these register bytes stored from EEPROM
loading when power up or EEPROM auto-reloading or can be programmed by software,
default as (00001)b