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−Operable in both USB-aware (Windows-95 and NT) and USB legacy BIOS support
−Inter-operable with major USB peripherals
* PCI Interface
−PCI specification v.2.1 compliant
−Supports advanced PCI commands
−Multi-level data FIFOs with full scatter and gather capabilities
* 0.5um high speed low power CMOS process
* Single chip 100-pin PQFP device
VT83C572 CONFIGURATION REGISTERS
The VT83C572 PCI to USB controller is fully compatible with the UHCI specification v.1.1. There
are two sets of software accessible registers -- PCI configuration registers and USB I/O registers. The
USB I/O registers are defined in the UHCI v.1.1 specification.
PCI Configuration Registers
OffsetFunction
1-0 Vendor ID : 1106h(read only)
3-2 Device ID : 3038h(read only)
5-4 Command Register
bit 15-8: reserved
bit 7: Address stepping, default: enabled
bit 6-5: reserved
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bit 4: Memory write and invalidate, default: disabled
bit 3: Fixed at 0 (special cycles)
bit 2: Bus master, default: disabled
bit 1: Memory space, default: disabled
bit 0: I/O space, default: disabled
7-6 Status Register
bit 15: reserved
bit 14: Signaled system error
bit 13: Received master abort
bit 12: Received target abort
bit 11: Signaled target abort
bit 10-9: DEVSEL# timing: fixed at 01 (medium)
bit 8-0: reserved
08 Revision ID.
B-9 Class Code Register:Fixed at 0C0300h to indicate the USB Controller
0C Cache Line Size Default: 00h
0D Latency TimerDefault: 16h
0E Header Type = 00h (read only)
0F BISTFixed at 00
23-20 Base address for UHCI v1.1 compliant USB IO Registers
bit 31-16:reserved
bit 15-5:Port address for the base USB IO Registers, corresponding to AD[15:5]
bit 4-0: 00001b
3C Interrupt Line
3D Interrupt Pin, Default = 01h
3E-3F reserved
40 Misc. Control Register 1
bit 7:PCI Memory Command Option
0 - Support Memory Read Line, Memory Read Multiple, Memory Write and Invalidate
1 - Only support Memory Read, Memory Write Commands
bit 6:Babble Option
0 - Automatically disable babbled port when EOF babble occurs.
1 - Don’t disable babbled port.
bit 5:PCI Parity Check Option
0 - Disable PERR generation
1 - Enable parity check and PERR generation
bit 4:reserved
bit 3:USB Data Length Option
0 - Support TD length up to 1280.
1 - Support TD length up to 1023.
bit 2:USB Power Management
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VIA Technologies, Inc.VT83C572
0 - Disable USB power management
1 - Enable USB power management
bit 1:DMA Option
0 - 16DW burst access
1 - 8DW burst access
bit 0:PCI Wait State
0 - Zero wait
1 - One wait
41 Misc. Control Register 2
bit7-3: reserved
bit 2:Trap Option
0 - Set trap 60/64 status bits without checking enable bits.
1 - Set trap 60/64 status bits only when trap 60/64 enable bits are set.
bit 1:A20gate Pass Through Option
0 - Pass through A20GATE command sequence defined in UHCI.
1 - Don’t pass through Write I/O port 64
bit 0:reserved
42-5Freserved
60 Serial Bus Release Numberfixed at 10h
C0-C1 Legacy Support Register (compliant with UHCI v1.1 specification)
Default=2000h
USB I/O Registers (UHCI v1.1 Compliant)
OffsetFunction
1-0 USB Command
3-2 USB Status
5-4 USB Interrupt Enable
7-6 Frame Number
B-8 Frame List Base Address
0C Start Of Frame Modify
11-10 Port 1 Status/Control
13-12 Port 2 Status/Control
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VT83C572 PIN DESCRIPTION
Signal NamePin No.I/OSignal Description
PCI Bus Interface
AD[31:0]98-100, 1-5, 9-
14, 17-19, 31,
32, 34-36, 38,
39, 41, 42, 44-
47, 49, 50
CBE#[3:0]7, 20, 33, 40BCommand/Byte Enable..
IDSEL8IInitialization Device Select.
FRAME#21BPCI Bus Frame Indicator.
IRDY#22BInitiator Ready Indicator.
TRDY#23BTarget Ready.
DEVSEL#24BDevice Select.
STOP#26BStop Indicator.
PAR30BParity.
PERR#27BPCI Bus Parity Error.
SERR#28ISystem Error.
LOCK#29BPCI Bus Lock.
REQ#97OPCI bus request to the bus arbiter.
GNT#96IPCI bus grant from the bus arbiter.
INTA #95IPCI Interrupt Request.
PCLK93IPCI Bus Clock.
PCIRST#92OPCI Reset: An active low reset signal for the PCI bus.
BPCI Address/Data Bus: The standard PCI address and data lines. The
address is driven with FRAME# assertion and data is driven or
received in following cycles.
Universal Serial Bus Interface
SD0+88BUSB Port 0 Data
SD0-89BUSB Port 0 Data
SD1+84BUSB Port 1 Data
SD1-85BUSB Port 1 Data
X171IUSB Clock input, connected to 48Mhz oscillator or crystal input.
X270OUSB 48Mhz crystal connection. Leave unconnected if oscillator is
used.
CPU Interface
SMI#51OSystem Management Interrupt to the processor for legacy keyboard
and mouse support.
Power and Ground
VDD6, 16, 43, 54,
63, 73, 82, 90,
94
VSS15, 25, 37, 48,
55, 69, 72, 83,
91
VDDA87IUSB Differential Output Power Source
VSSA86IUSB Differential Output Ground