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VND5050AK-E
Datasheet (ST)
37 pgs584.39 Kb0
Specification
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Datasheet VND5050AJ-E, VND5050AK-E Datasheet (ST)

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Page 1
Double channel high side driver with analog current sense
Features
Max transient supply voltage V
Operating voltage range V
Max on-state resistance (per ch.) R
Current limitation (typ) I
Off-state supply current I
1. Typical value with all loads connected
■ Main
– Inrush current active management by
power limitation – Very low standby current – 3.0 V CMOS compatible input – Optimized electromagnetic emission – Very low electromagnetic susceptibility – In compliance with the 2002/95/ec
european directive
■ Diagnostic functions
– Proportional load current sense – High current sense precision for wide range
currents – Current sense disable – Thermal shutdown indication – Very low current sense leakage
■ Protections
– Undervoltage shutdown – Overvoltage clamp – Load current limitation – Self limiting of fast thermal transients – Protection against loss of ground and loss
of V
CC
– Thermal shutdown – Reverse battery protection (see Application
schematic on page 21)
– Electrostatic discharge protection
CC
CC
ON
LIMH
S
41 V
4.5 to 36 V
50 mΩ
18 A
(1)
2µA
VND5050AJ-E
VND5050AK-E
for automotive applications
PowerSSO-24PowerSSO-12
Applications
■ All types of resistive, inductive and capacitive
loads
■ Suitable as LED driver
Description
The VND5050AJ-E, VND5050AK-E is a monolithic device made using STMicroelectronics VIPower M0-5 technology. It is intended for driving resistive or inductive loads with one side connected to ground. Active V clamp protects the device against low energy spikes (see ISO7637 transient compatibility table).
This device integrates an analog current sense which delivers a current proportional to the load current (according to a known ratio) when CS_DIS is driven low or left open. When CS_DIS is driven high, the current sense pin is in a high impedance condition.
Output current limitation protects the device in overload condition. In case of long overload duration, the device limits the dissipated power to safe level up to thermal shutdown intervention. Thermal shutdown with automatic restart allows the device to recover normal operation as soon as fault condition disappears.

Table 1. Device summary

Package
Tube Tape and reel
pin voltage
CC
Order codes
PowerSSO-12
VND5050AJ-E VND5050AJTR-E
PowerSSO-24 VND5050AK-E VND5050AKTR-E
July 2009 Doc ID 12272 Rev 9 1/37
www.st.com
1
Page 2
Contents VND5050AJ-E / VND5050AK-E
Contents
1 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.4 Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.1 GND protection network against reverse battery . . . . . . . . . . . . . . . . . . . 21
3.1.1 Solution 1: resistor in the ground line (RGND only) . . . . . . . . . . . . . . . . 21
3.1.2 Solution 2: diode (DGND) in the ground line . . . . . . . . . . . . . . . . . . . . . 22
3.2 Load dump protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.3 Microcontroller I/Os protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.4 Maximum demagnetization energy (VCC = 13.5V) . . . . . . . . . . . . . . . . . 23
4 Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.1 PowerSSO-12™ thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.2 PowerSSO-24™ thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5 Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.1 ECOPACK® packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.2 PowerSSO-12™ package information . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.3 PowerSSO-24™ package information . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5.4 PowerSSO-12™ packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5.5 PowerSSO-24™ packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
2/37 Doc ID 12272 Rev 9
Page 3
VND5050AJ-E / VND5050AK-E List of tables
List of tables
Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 2. Pin function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 3. Suggested connections for unused and not connected pins . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 4. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 5. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 6. Power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 7. Switching (VCC = 13V; Tj = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 8. Logic input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 9. Protections and diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 10. Current sense (8V<V
Table 11. Truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 12. Electrical transient requirements (part 1/3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 13. Electrical transient requirements (part 2/3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 14. Electrical transient requirements (part 3/3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 15. PowerSSO-12™ thermal parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 16. PowerSSO-24™ thermal parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 17. PowerSSO-12™ mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 18. PowerSSO-24™ mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 19. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
<16V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
CC
Doc ID 12272 Rev 9 3/37
Page 4
List of figures VND5050AJ-E / VND5050AK-E
List of figures
Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 2. Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 3. Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 4. Current sense delay characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 5. Delay response time between rising edge of output current and rising edge of current sense
(CS enabled). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 6. I
OUT/ISENSE
Figure 7. Maximum current sense ratio drift vs load current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 8. Switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 9. Output voltage drop limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 10. Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 11. Off-state output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 12. High level input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 13. Input clamp voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 14. Input high level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 15. Input low level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 16. Input hysteresis voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 17. On-state resistance vs T Figure 18. On-state resistance vs V
Figure 19. Undervoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 20. I
LIMH
vs T
Figure 21. Turn-on voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 22. Turn-off voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 23. STAT_DIS clamp voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 24. Low level STAT_DIS voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 25. High level STAT_DIS voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 26. Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 27. Maximum turn-off current versus inductance (for each channel) . . . . . . . . . . . . . . . . . . . . 23
Figure 28. PowerSSO-12™ PC board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 29. Rthj-amb vs PCB copper area in open box free air condition (one channel on). . . . . . . . . 24
Figure 30. PowerSSO-12™ thermal impedance junction ambient single pulse (one channel on). . . . 25
Figure 31. Thermal fitting model of a double channel HSD in PowerSSO-12™ . . . . . . . . . . . . . . . . . 25
Figure 32. PowerSSO-24™ PC board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 33. Rthj-amb vs PCB copper area in open box free air condition (one channel on). . . . . . . . . 27
Figure 34. PowerSSO-24™ Thermal impedance junction ambient single pulse (one channel on) . . . 28
Figure 35. Thermal fitting model of a double channel HSD in PowerSSO-24™ . . . . . . . . . . . . . . . . . 28
Figure 36. PowerSSO-12™ package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 37. PowerSSO-24™ package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 38. PowerSSO-12™ tube shipment (no suffix). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 39. PowerSSO-12™ tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 40. PowerSS0-24 Figure 41. PowerSSO-24
vs I
case
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
OUT
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
case
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
TM
tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
TM
tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
4/37 Doc ID 12272 Rev 9
Page 5
VND5050AJ-E / VND5050AK-E Block diagram and pin description

1 Block diagram and pin description

Figure 1. Block diagram

V
CC
Pwr
LIM
UNDERVOLTAGE
DRIVER 1
Pwr
1
LIM
OVERTE MP. 1
I
OUT1
2
PwCLAMP 1
K 1
V
DSLIM
I
1
LIM
1
V
CC
CLAMP
GND
INPUT1
INPUT2
CS_DIS

Table 2. Pin function

LOGIC
Name Function
V
CC
OUTPUT
GND
Battery connection.
Power output.
1,2
Ground connection. Must be reverse battery protected by an external diode/resistor network.
DRIVER 2
I
OUT2
PwCLAMP 2
I
LIM
V
DSLIM
OVERTEMP. 2
K 2
OUTPUT1
CURRENT SENSE1
OUTPUT2
2
2
CURRENT SENSE2
INPUT
CURRENT
SENSE
Voltage controlled input pin with hysteresis, CMOS compatible. Controls output
1,2
switch state.
Analog current sense pin, delivers a current proportional to the load current
1,2
CS_DIS Active high CMOS compatible pin, to disable the current sense pin.
Doc ID 12272 Rev 9 5/37
Page 6
Block diagram and pin description VND5050AJ-E / VND5050AK-E

Figure 2. Configuration diagram (top view)

TAB = V
GND
INPUT2
CURRENT SENSE1
INPUT1
CURRENT SENSE2
CS_DIS
cc
12
1 2 3 4 5
6
11 10
V
cc
OUTPUT2 OUTPUT2
9
OUTPUT1
8
OUTPUT1
7
V
cc
CURRENT SENSE1
CURRENT SENSE2
V
GND
N.C.
INPUT2
N.C.
INPUT1
N.C.
N.C.
CS_DIS.
V
CC
CC
OUTPUT2 OUTPUT2 OUTPUT2 OUTPUT2 OUTPUT2 OUTPUT2 OUTPUT1 OUTPUT1 OUTPUT1 OUTPUT1 OUTPUT1 OUTPUT1
TAB = V
CC
PowerSSO-12

Table 3. Suggested connections for unused and not connected pins

PowerSSO-24
Connection/pin Current sense N.C. Output Input CS_DIS
Floating N.R.
To ground
1. Not recommended.
Through 1 KΩ
(1)
resistor
XX X X
XN.R.
(1)
Through 10 KΩ
resistor
Through
10 KΩ resistor
6/37 Doc ID 12272 Rev 9
Page 7
VND5050AJ-E / VND5050AK-E Electrical specifications

2 Electrical specifications

Figure 3. Current and voltage conventions

I
S
V
V
CSD
CC
I
I
CSD
CS_DIS
I
IN1
V
IN1
I
IN2
V
IN2
INPUT1
INPUT2
GND
OUTPUT1
CURRENT SENSE1
OUTPUT2
CURRENT SENSE2
I
GND
OUT1
I
SENSE1
I
OUT2
I
SENSE2
V
SENSE2
V
OUT2
V
SENSE1
V
Fn
V
OUT1
V
CC
Note: V
Fn
= V
- VCC during reverse battery condition.
OUTn

2.1 Absolute maximum ratings

Stressing the device above the rating listed in the “Absolute maximum ratings” table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to the conditions in table below for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality document.

Table 4. Absolute maximum ratings

Symbol Parameter Value Unit
V
-V
-I
I
OUT
-I
I
CSD
-I
CSENSE
V
CSENSE
E
DC supply voltage 41 V
CC
Reverse DC supply voltage 0.3 V
CC
DC reverse ground pin current 200 mA
GND
DC output current Internally limited A
Reverse DC output current 12 A
OUT
DC input current -1 to 10 mA
I
IN
DC current sense disable input current -1 to 10 mA
DC reverse CS pin current 200 mA
Current sense maximum voltage
Maximum switching energy
MAX
(L= 3mH; R
=0Ω; V
L
=13.5V; T
bat
jstart
=150°C; I
OUT
= I
limL
(Typ.))
V
-41
CC
+V
CC
104 mJ
V V
Doc ID 12272 Rev 9 7/37
Page 8
Electrical specifications VND5050AJ-E / VND5050AK-E
Table 4. Absolute maximum ratings (continued)
Symbol Parameter Value Unit
Electrostatic discharge (Human Body Model: R=1.5KΩ;
V
V
ESD
ESD
T
C=100pF) – Input – Current sense –CS_DIS – Output –V
CC
Charge device model (CDM-AEC-Q100-011) 750 V
Junction operating temperature -40 to 150 °C
T
j
Storage temperature -55 to 150 °C
stg
4000 2000 4000 5000 5000
V V V V V

2.2 Thermal data

Table 5. Thermal data

Value
Symbol Parameter
PowerSSO-12 PowerSSO-24
Unit
R
thj-case
R
thj-amb
Thermal resistance junction case (max) (with one channel on)
Thermal resistance junction ambient (max)

2.3 Electrical characteristics

8V<VCC<36 V; -40 °C<Tj<150 °C, unless otherwise specified.

Table 6 . Power section

Symbol Parameter Test conditions Min. Typ. Max. Unit
V
V
V
USDhyst
R
V
clamp
Operating supply voltage 4.5 13 36 V
CC
Undervoltage shutdown 3.5 4.5 V
USD
Undervoltage shutdown hysteresis
On-state resistance
ON
Clamp voltage IS= 20mA 41 46 52 V
I
Supply current
S
(1)
See Figure 29 See Figure 33 °C/W
I
= 2A; Tj= 25°C
OUT
= 2A; Tj= 150°C
I
OUT
= 2A; VCC= 5V; Tj= 25°C
I
OUT
Off-state; V V
IN=VOUT=VSENSE=VCSD
On-state; V I
= 0A
OUT
=13V; Tj=25°C;
CC
=13V; VIN=5V;
CC
2.7 2.7 °C/W
0.5 V
50
mΩ
100
mΩ
65
mΩ
(2)
3
(2)
5
6µAmA
=0V
2
8/37 Doc ID 12272 Rev 9
Page 9
VND5050AJ-E / VND5050AK-E Electrical specifications
Table 6 . Power section (continued)
Symbol Parameter Test conditions Min. Typ. Max. Unit
I
L(off)
V
Off-state output current
Output - VCC diode
F
voltage
(1)
(1)
VIN=V
= 25°C
T
j
V
IN=VOUT
Tj= 125°C
-I
OUT
=0V; VCC=13V;
OUT
000.01 3
=0V; VCC=13V;
5
=4A; Tj=150°C 0.7 V
1. For each channel.
2. PowerMOS leakage included.
Table 7. Switching (VCC=13V; Tj= 25°C)
Symbol Parameter Test conditions Min. Typ. Max. Unit
dV
dV
t
d(on)
t
d(off)
OUT
OUT
W
W
OFF
Turn-on delay time RL= 6.5Ω (see Figure 8)25µs
Turn-off delay time RL= 6.5Ω (see Figure 8)35µs
/dt
Turn-on voltage slope RL= 6.5Ω See Figure 21 V/µs
(on)
/dt
Turn-off voltage slope RL= 6.5Ω See Figure 22 V/µs
(off)
Switching energy losses
ON
during t
won
Switching energy losses during t
woff
RL= 6.5Ω (see Figure 8)0.24mJ
RL= 6.5Ω (see Figure 8)0.2mJ
µA

Table 8. Logic input

Symbol Parameter Test conditions Min. Typ. Max. Unit
V
I
V
I
IH
V
I(hyst)
V
ICL
V
CSDL
I
CSDL
V
CSDH
I
CSDH
Input low level voltage 0.9 V
IL
Low level input current VIN= 0.9V 1 µA
IL
Input high level voltage 2.1 V
IH
High level input current VIN= 2.1V 10 µA
Input hysteresis voltage 0.25 V
Input clamp voltage
I
= 1mA
IN
= -1mA
I
IN
5.5
-0.7
CS_DIS low level voltage 0.9 V
Low level CS_DIS current
CS_DIS high level voltage
High level CS_DIS current
= 0.9V 1 µA
V
CSD
2.1 V
V
= 2.1V 10 µA
CSD
7V
V
Doc ID 12272 Rev 9 9/37
Page 10
Electrical specifications VND5050AJ-E / VND5050AK-E
Table 8. Logic input (continued)
Symbol Parameter Test conditions Min. Typ. Max. Unit
V
CSD(hyst)
V
CSCL

Table 9 . Protections and diagnostics

CS_DIS hysteresis voltage
CS_DIS clamp voltage
I
CSD
I
CSD
= 1mA = -1mA
(1)
0.25 V
5.5
7V
-0.7
Symbol Parameter Test conditions Min. Typ. Max. Unit
I
limH
I
limL
T
TSD
T
T
T
HYST
V
DEMAG
V
RS
ON
DC short circuit current
Short circuit current during thermal cycling
VCC= 13V 5V<V
V
<36V
CC
=13V; TR<Tj<T
CC
TSD
Shutdown temperature 150 175 200 °C
Reset temperature
R
Thermal reset of STATUS
Thermal hysteresis
TSD-TR
)
=2A; VIN=0; L=6mH VCC-41 VCC-46 VCC-52 V
I
OUT
I
=0.1A;
OUT
= -40°C...+150°C
T
j
(see Figure 9)
(T
Turn-off output voltage clamp
Output voltage drop limitation
12 18 24
24
7A
TRS + 1
TRS + 5 °C
135 °C
7°C
25 mV
V
A A
1. To ensure long term reliability under heavy overload or short circuit conditions, protection and related diagnostic signals must be used together with a proper software strategy. If the device is subjected to abnormal conditions, this software must limit the duration and number of activation cycles.

Table 10. Current sense (8V<VCC<16V)

Symbol Parameter Test conditions Min. Typ. Max. Unit
I
=0.05A;
OUT
K
K
dK
1/K1
K
I
0
1
OUT/ISENSE
I
OUT/ISENSE
Current sense ratio
(1)
drift
I
2
OUT/ISENSE
V
SENSE
= -40°C...150°C
T
j
I
=1A; V
OUT
= -40°C
T
j
= 25°C...150°C
T
j
=1A; V
I
OUT
V
CSD
TJ=-40 °C to 150 °C
I
=2A; V
OUT
Tj= -40°C
= 25°C...150°C
T
j
10/37 Doc ID 12272 Rev 9
=0.5V;V
=0V;
SENSE
SENSE
SENSE
=0V;
CSD
=0.5V;V
= 0.5V;
=4V;V
CSD
CSD
=0V;
=0V;
1270 2360 3450
1470
2020
2610
1570
2020
2470
-7 +7 %
1740
2020
2320
1790
2020
2250
Page 11
VND5050AJ-E / VND5050AK-E Electrical specifications
Table 10. Current sense (8V<VCC<16V) (continued)
Symbol Parameter Test conditions Min. Typ. Max. Unit
dK2/K
K
dK
3/K3
I
SENSE0
I
OL
V
SENSE
Current sense ratio
(1)
2
drift
I
3
OUT/ISENSE
Current sense ratio
(1)
drift
Analog sense leakage current
Openload on-state current detection threshold
Max analog sense output voltage
=2 A; V
I
OUT
V
CSD
=-40 °C to 150 °C
T
J
I
=4A; V
OUT
=-40°C
T
j
SENSE
=0V;
SENSE
Tj=25°C...150°C
=4 A; V
I
OUT
V
CSD
=-40 °C to 150 °C
T
J
=0A; V
I
OUT
V
CSD
=-40°C...150°C
T
j
V
CSD
=-40°C...150°C
T
j
=2A; V
I
OUT
V
CSD
=-40°C...150°C
T
j
VIN = 5V, I
I
=4A; V
OUT
SENSE
=0V;
SENSE
=5V; VIN=0V;
=0V; VIN=5V;
SENSE
=5V; VIN=5V;
SENSE
CSD
= 4 V;
-4 +4 %
=4V;V
CSD
=0V;
1880 1900
2010 2010
2160 2120
= 4 V;
-2 +2 %
=0V;
0
0
1
2
=0V;
0
1
= 5 µA 4 20 mA
=0V 5 V
µA
µA
µA
Analog sense
V
SENSEH
output voltage in over temperature
V
CC
=13V; R
=10KΩ 9V
SENSE
condition
Analog sense
I
SENSEH
output current in over temperature
V
CC
=13V; V
=5V 8 mA
SENSE
condition
Delay response
t
DSENSE1H
time from falling edge of CS_DIS pin
Delay response
t
DSENSE1L
time from rising edge of CS_DIS pin
t
DSENSE2H
Delay response time from rising edge of INPUT pin
V I (see Figure 4)
V I (see Figure 4)
V I (see Figure 4)
<4V, 0.5A<Iout<4A
SENSE
=90% of I
SENSE
<4V, 0.5A<Iout<4A
SENSE
=10% of I
SENSE
<4V, 0.5A<Iout<4A
SENSE
=90% of I
SENSE
SENSE max
SENSE max
SENSE max
50 100 µs
520µs
80 250 µs
Doc ID 12272 Rev 9 11/37
Page 12
Electrical specifications VND5050AJ-E / VND5050AK-E
Table 10. Current sense (8V<VCC<16V) (continued)
Symbol Parameter Test conditions Min. Typ. Max. Unit
Delay response
V I
SENSE
I
OUT
I
OUTMAX
V I
SENSE
(see Figure 4)
Δt
DSENSE2H
t
DSENSE2L
time between rising edge of output current and rising edge of current sense
Delay response time from falling edge of INPUT pin
1. Parameter guaranteed by design; it is not tested.
<4V,
SENSE
= 90% of I
= 90% of I
=2A (see Figure 5)
<4V, 0.5A<Iout<4A
SENSE
=10% of I
SENSEMAX,
OUTMAX
SENSE max

Figure 4. Current sense delay characteristics

INPUT
CS_DIS
LOAD CURRENT
SENSE CURRENT
t
DSENSE2H
t
DSENSE1L
t
DSENSE1H
65 µs
100 250 µs
t
DSENSE2L
12/37 Doc ID 12272 Rev 9
Page 13
VND5050AJ-E / VND5050AK-E Electrical specifications
Figure 5. Delay response time between rising edge of output current and rising
edge of current sense (CS enabled)
V
IN
Δ
t
DSENSE2H
t
I
OUT
I
SENSE
90% I
OUTMAX
I
OUTMAX
I
SENSEMAX
t
90% I
SENSEMAX
t
Doc ID 12272 Rev 9 13/37
Page 14
Electrical specifications VND5050AJ-E / VND5050AK-E
Figure 6. I
OUT/ISENSE
vs I
I
OUT/ISENS E
OUT
3000
2500
M ax -40°C t o 150°C
Max 25°C to 150°C
2000
M in 25°C t o 150°C
1500
M in -40°C to 150°C
1000
500
12345
(A)
I
OUT

Figure 7. Maximum current sense ratio drift vs load current

Typ 25°C
dk/k(%)
10
5
0
-5
-10
1234
Note: Parameter guaranteed by design; it is not tested.
I
OUT
(A)
14/37 Doc ID 12272 Rev 9
Page 15
VND5050AJ-E / VND5050AK-E Electrical specifications

Table 11. Truth table

Conditions Input Output Sense (V
Normal operation
L
H
L
H
CSD
0
Nominal
=0V)
(1)
Over temperature
Undervoltage
Short circuit to GND (R
≤ 10 mΩ)
sc
Short circuit to V
CC
Negative output voltage clamp
1. If the V and external circuit.
is high, the SENSE output is at a high impedance, its potential depends on leakage currents
CSD
L
H
L
H
L H H
L H
LL 0

Figure 8. Switching characteristics

V
OUT
dV
OUT
INPUT
t
Won
80%
/dt
(on)
t
r
t
d(on)
10%
t
d(off)
t
Woff
90%
t
L L
L L
L L L
V
SENSEH
H H
dV
/dt
OUT
(off)
f
0
V
SENSEH
0 0
0
0 if T
< T
j
if Tj > T
0
< Nominal
t
TSD
TSD
t

Figure 9. Output voltage drop limitation

Vcc-V
out
Tj=150oC
V
on
Von/R
on(T)
Doc ID 12272 Rev 9 15/37
T
=25oC
j
=-40oC
T
j
I
out
Page 16
Electrical specifications VND5050AJ-E / VND5050AK-E

Table 12. Electrical transient requirements (part 1/3)

ISO 7637-2:
2004(E)
test pulse
Test levels
III IV
(1)
Number of
pulses or
test times
Burst cycle/pulse
repetition time
Delays and impedance
1 -75V -100V
2a +37V +50V
5000
pulses
5000
pulses
0.5 s 5 s 2 ms, 10 Ω
0.2 s 5 s 50 µs, 2 Ω
3a -100V -150V 1h 90 ms 100 ms 0.1 µs, 50 Ω
3b +75V +100V 1h 90 ms 100 ms 0.1 µs, 50 Ω
4-6V-7V1 pulse
(2)
5b
1. The above test levels must be considered referred to VCC = 13.5V except for pulse 5b.
+65V +87V 1 pulse 400 ms, 2 Ω
100 ms, 0.01

Table 13. Electrical transient requirements (part 2/3)

ISO 7637-2:
Test level results
2004(E)
test pulse
III IV
1C C
2a C C
3a C C
(1)
Ω
3b C C
4C C
(2)
5b
1. The above test levels must be considered referred to VCC = 13.5V except for pulse 5b.
2. Valid in case of external load dump clamp: 40V maximum referred to ground.
CC

Table 14. Electrical transient requirements (part 3/3)

Class Contents
C All functions of the device are performed as designed after exposure to disturbance.
E
One or more functions of the device are not performed as designed after exposure to disturbance and cannot be returned to proper operation without replacing the device.
16/37 Doc ID 12272 Rev 9
Page 17
VND5050AJ-E / VND5050AK-E Electrical specifications

Figure 10. Waveforms

NORMAL OPERATION
INPUT
CS_DIS
LOAD CURRENT
SENSE CURRENT
UNDERVOLTAGE
V
V
CC
INPUT CS_DIS
LOAD CURRENT
SENSE CURRENT
V
USD
USDhyst
INPUT CS_DIS
LOAD VOLTAGE LOAD CURRENT SENSE CURRENT
T
j
T
R
INPUT
CS_DIS
LOAD CURRENT
SENSE CURRENT
T
TSD
T
RS
current
limitation
SHORT TO V
<Nominal
OVERLOAD OPERATION
power limitation
SHORTED LOAD NORMAL LOAD
CC
thermal cycling
<Nominal
I
LIMH
I
LIML
V
SENSEH
Doc ID 12272 Rev 9 17/37
Page 18
Electrical specifications VND5050AJ-E / VND5050AK-E

2.4 Electrical characteristics curves

Figure 11. Off-state output current Figure 12. High level input current

Iloff (uA)
1
0.875
0.75
0.625
0.5
0.375
0.25
0.125
0
-50 -25 0 25 50 75 100 125 150 175
Off State Vcc=13V
Vin=Vout=0V
Tc ( °C )

Figure 13. Input clamp voltage Figure 14. Input high level

Vicl (V)
7
6.8
6.6
6.4
6.2
6
5.8
5.6
5.4
5.2
5
Iin=1mA
-50 -25 0 25 50 75 100 125 150 175
Tc ( °C )

Figure 15. Input low level Figure 16. Input hysteresis voltage

Vil (V)
2
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
-50 -25 0 25 50 75 100 125 150 175
Tc ( °C )
Iih (uA)
5
4.5
4
3.5
3
2.5
2
1.5
0.5
0
Vin=2.1V
1
-50 -25 0 25 50 75 100 125 150 175
Tc ( °C )
Vih (V)
4
3.5
3
2.5
2
1.5
1
0.5
0
-50 -25 0 25 50 75 100 125 150 175
Tc ( °C )
Vhyst (V)
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
-50 -25 0 25 50 75 100 125 150 175
Tc ( °C )
18/37 Doc ID 12272 Rev 9
Page 19
VND5050AJ-E / VND5050AK-E Electrical specifications
Figure 17. On-state resistance vs T
case
Ron (mOhm)
100
90
80
70
60
50
40
30
20
10
0
-50 -25 0 25 50 75 100 125 150 175
Iout=2A
Vcc=13V
Figure 18. On-state resistance vs V
Ron (mOhm)
100
90
80
70
60
50
40
30
20
10
0
0 5 10 15 20 25 30 35 40
Tc ( °C )

Figure 19. Undervoltage shutdown Figure 20. I

Vusd (V)
16
14
12
10
8
6
4
2
0
-50 -25 0 25 50 75 100 125 150 175
Tc ( °C )
Ilimh (A)
25
22.5
20
17.5
15
12.5
10
7.5
5
-50 -25 0 25 50 75 100 125 150 175
LIMH
vs T
Vcc=13V
CC
Tc= 150°C
Tc= 125°C
Tc= 25°C
Tc= - 40 °C
Vcc (V)
case
Tc ( °C )

Figure 21. Turn-on voltage slope Figure 22. Turn-off voltage slope

(dVout/dt)on (V/ms)
1000
900
800
700
600
500
400
300
200
100
0
-50 -25 0 25 50 75 100 125 150 175
Vcc=13V
RI=6.5Ohm
Tc (° C)
Doc ID 12272 Rev 9 19/37
(dVout/dt)off (V/ms)
1000
900
800
700
600
500
400
300
200
100
0
-50 -25 0 25 50 75 100 125 150 175
Vcc=13V
RI=6.5Ohm
Tc ( °C )
Page 20
Electrical specifications VND5050AJ-E / VND5050AK-E

Figure 23. STAT_DIS clamp voltage Figure 24. Low level STAT_DIS voltage

Vsdcl(V)
14
12
Isd=1mA
10
8
6
4
2
Vsdl(V)
8
7
6
5
4
3
2
1
0
-50 -25 0 25 50 75 100 125 150 175
Tc ( °C )

Figure 25. High level STAT_DIS voltage

Vsdh(V)
8
7
6
5
4
3
2
1
0
-50 -25 0 25 50 75 100 125 150 175
Tc (° C)
0
-50 -25 0 25 50 75 100 125 150 175
Tc (° C)
20/37 Doc ID 12272 Rev 9
Page 21
VND5050AJ-E / VND5050AK-E Application information

3 Application information

Figure 26. Application schematic

+5V
V
CC
R
prot
CS_DIS
D
ld
μ
C
R
prot
R
prot
R
SENSE
C
EXT
INPUT
CURRENT SENSE
OUTPUT
GND
R
GND
GND
D
GND
V
Note: Channel 2 has the same internal circuit as channel 1.

3.1 GND protection network against reverse battery

3.1.1 Solution 1: resistor in the ground line (R
This can be used with any type of load.
The following is an indication on how to dimension the R
1. R
2. R
where -I maximum rating section of the device datasheet.
≤ 600mV / (I
GND
≥ (−VCC) / (-I
GND
is the DC reverse ground pin current and can be found in the absolute
GND
S(on)max
GND
).
)
GND
only)
resistor.
GND
Power Dissipation in R
P
= (-VCC)2/R
D
GND
(when VCC<0: during reverse battery situations) is:
GND
This resistor can be shared amongst several different HSDs. Please note that the value of this resistor should be calculated with formula (1) where I
S(on)max
becomes the sum of the
maximum on-state currents of the different devices.
Please note that if the microprocessor ground is not shared by the device ground then the R
will produce a shift (I
GND
S(on)max
* R
) in the input thresholds and the status output
GND
values. This shift will vary depending on how many devices are ON in the case of several high side drivers sharing the same R
Doc ID 12272 Rev 9 21/37
GND
.
Page 22
Application information VND5050AJ-E / VND5050AK-E
If the calculated power dissipation leads to a large resistor or several devices have to share the same resistor then ST suggests to utilize Solution 2 (see below).
3.1.2 Solution 2: diode (D
A resistor (R
=1kΩ) should be inserted in parallel to D
GND
) in the ground line
GND
inductive load.
This small signal diode can be safely shared amongst several different HSDs. Also in this case, the presence of the ground network will produce a shift (≈600mV) in the input threshold and in the status output values if the microprocessor ground is not common to the device ground. This shift will not vary if more than one HSD shares the same diode/resistor network.

3.2 Load dump protection

Dld is necessary (Voltage Transient Suppressor) if the load dump peak voltage exceeds the V
max DC rating. The same applies if the device is subject to transients on the VCC line
CC
that are greater than the ones shown in the ISO 7637-2: 2004(E) table.

3.3 Microcontroller I/Os protection

If a ground protection network is used and negative transient are present on the VCC line, the control pins will be pulled negative. ST suggests to insert a resistor (R prevent the µC I/Os pins to latch-up.
The value of these resistors is a compromise between the leakage current of µC and the current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of µC I/Os.
if the device drives an
GND
prot
) in line to
-V
CCpeak/Ilatchup
≤ R
prot
≤ (V
OHμC-VIH-VGND
Calculation example:
For V
5kΩ ≤ R
Recommended values: R
22/37 Doc ID 12272 Rev 9
CCpeak
prot
≤ 180kΩ.
= - 100V and I
latchup
=10kΩ, C
prot
≥ 20mA; V
EXT
) / I
IHmax
OHµC
=10nF.
≥ 4.5V
Page 23
VND5050AJ-E / VND5050AK-E Application information

3.4 Maximum demagnetization energy (VCC = 13.5V)

Figure 27. Maximum turn-off current versus inductance (for each channel)

100
A
B
10
I (A)
1
0,1 1 10 100
C
L (mH )
A:
T
= 150°C single pulse
jstart
VIN, I
B: T
C:
L
= 100°C repetitive pulse
jstart
T
= 125°C repetitive pulse
jstart
Note: Values are generated with R
demagnetization) of every pulse must not exceed the temperature specified above for curves A and B.
Demagnetization Demagnetization Demagnetization
=0 Ω.In case of repetitive pulses, T
L
(at beginning of each
jstart
t
Doc ID 12272 Rev 9 23/37
Page 24
Package and PCB thermal data VND5050AJ-E / VND5050AK-E

4 Package and PCB thermal data

4.1 PowerSSO-12™ thermal data

Figure 28. PowerSSO-12™ PC board

Note: Layout condition of R
area= 77 mm x 86 mm,PCB thickness=1.6 mm, Cu thickness=70 μm (front and back side), Copper areas: from minimum pad lay-out to 8 cm
Figure 29. R
thj-amb
on)
RTHj_amb(°C/ W)
70
65
60
55
50
45
40
35
30
0246810
and Zth measurements (PCB: Double layer, Thermal Vias, FR4
th
2
).
vs PCB copper area in open box free air condition (one channel
PCB Cu heatsink area (cm^ 2)
24/37 Doc ID 12272 Rev 9
Page 25
VND5050AJ-E / VND5050AK-E Package and PCB thermal data
Figure 30. PowerSSO-12™ thermal impedance junction ambient single pulse (one
channel on)
ZTH (°C/ W)
100
Footprint
2 cm
8 cm
2
2
10
1
0,1
0,0001 0,001 0,01 0,1 1 10 100 1000
Time ( s)
Equation 1: pulse calculation formula
Z
THδ
where δ = t

Figure 31. Thermal fitting model of a double channel HSD in PowerSSO-12™

R
TH
/T
P
δ Z
THtp
1 δ–()+⋅=
(a)
a. The fitting model is a simplified thermal tool and is valid for transient evolutions where the embedded
protections (power limitation or thermal cycling during thermal shutdown) are not triggered.
Doc ID 12272 Rev 9 25/37
Page 26
Package and PCB thermal data VND5050AJ-E / VND5050AK-E

Table 15. PowerSSO-12™ thermal parameter

Area/island (cm2)Footprint28
R1= R7 (°C/W) 0.7
R2= R8 (°C/W) 2.8
R3 (°C/W) 4
R4 (°C/W) 8 8 7
R5 (°C/W) 22 15 10
R6 (°C/W) 26 20 15
C1= C7 (W.s/°C) 0.001
C2= C8 (W.s/°C) 0.0025
C3 (W.s/°C) 0.05
C4 (W.s/°C) 0.2 0.1 0.1
C5 (W.s/°C) 0.27 0.8 1
C6 (W.s/°C) 3 6 9
26/37 Doc ID 12272 Rev 9
Page 27
VND5050AJ-E / VND5050AK-E Package and PCB thermal data

4.2 PowerSSO-24™ thermal data

Figure 32. PowerSSO-24™ PC board

Note: Layout condition of R
area= 77 mm x 86 mm, PCB thickness=1.6mm, Cu thickness=70 µm (front and back side), Copper areas: from minimum pad lay-out to 8 cm
Figure 33. R
thj-amb
on)
RTHj_amb(°C/W)
55
50
45
40
35
30
0246810
and Zth measurements (PCB: Double layer, Thermal Vias, FR4
th
2
).
vs PCB copper area in open box free air condition (one channel
PCB Cu heatsink area (cm^2)
Doc ID 12272 Rev 9 27/37
Page 28
Package and PCB thermal data VND5050AJ-E / VND5050AK-E
Figure 34. PowerSSO-24™ Thermal impedance junction ambient single pulse (one
channel on)
Equation 2: pulse calculation formula
Z
THδ
where δ = t

Figure 35. Thermal fitting model of a double channel HSD in PowerSSO-24™

b. The fitting model is a simplified thermal tool and is valid for transient evolutions where the embedded
R
TH
/T
P
δ Z
THtp
1 δ–()+⋅=
protections (power limitation or thermal cycling during thermal shutdown) are not triggered.
(b)
28/37 Doc ID 12272 Rev 9
Page 29
VND5050AJ-E / VND5050AK-E Package and PCB thermal data

Table 16. PowerSSO-24™ thermal parameter

Area/island (cm2)Footprint28
R1=R7 (°C/W) 0.4
R2=R8 (°C/W) 2
R3 (°C/W) 6
R4 (°C/W) 7.7
R5 (°C/W) 9 9 8
R6 (°C/W) 28 17 10
C1=C7 (W.s/°C) 0.001
C2=C8 (W.s/°C) 0.0022
C3 (W.s/°C) 0.025
C4 (W.s/°C) 0.75
C5 (W.s/°C) 1 4 9
C6 (W.s/°C) 2.2 5 17
Doc ID 12272 Rev 9 29/37
Page 30
Package and packing information VND5050AJ-E / VND5050AK-E

5 Package and packing information

5.1 ECOPACK® packages

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK
®
packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com
ECOPACK
®
is an ST trademark.

5.2 PowerSSO-12™ package information

Figure 36. PowerSSO-12™ package dimensions

.
30/37 Doc ID 12272 Rev 9
Page 31
VND5050AJ-E / VND5050AK-E Package and packing information

Table 17. PowerSSO-12™ mechanical data

Symbol
Min. Typ. Max.
A 1.25 1.62
A1 0 0.1
A2 1.10 1.65
B 0.23 0.41
C 0.19 0.25
D4.8 5.0
E3.8 4.0
e0.8
H5.8 6.2
h 0.25 0.5
L 0.4 1.27
Millimeters
k0° 8°
X1.9 2.5
Y3.6 4.2
ddd 0.1
Doc ID 12272 Rev 9 31/37
Page 32
Package and packing information VND5050AJ-E / VND5050AK-E

5.3 PowerSSO-24™ package information

Figure 37. PowerSSO-24™ package dimensions

Table 18. PowerSSO-24™ mechanical data

Millimeters
Symbol
Min. Typ. Max.
A - 2.45
A2 2.15 2.35
a1 0 0.1
b 0.33 0.51
c 0.23 0.32
D 10.10 10.50
E7.4 7.6
e0.8
e3 8.8
F2.3
G 0.1
H 10.1 10.5
32/37 Doc ID 12272 Rev 9
Page 33
VND5050AJ-E / VND5050AK-E Package and packing information
Table 18. PowerSSO-24™ mechanical data (continued)
Symbol
Min. Typ. Max.
h 0.4
k0° 8°
L 0.55 0.85
O1.2
Q0.8
S2.9
T3.65
U1.0
N 10°
X4.1 4.7
Y6.5 7.1
Millimeters
Doc ID 12272 Rev 9 33/37
Page 34
Package and packing information VND5050AJ-E / VND5050AK-E

5.4 PowerSSO-12™ packing information

Figure 38. PowerSSO-12™ tube shipment (no suffix)

B
C
Base Q.ty 100 Bulk Q.ty 2000 Tube length (± 0.5) 532
A
A1.85 B6.75 C (± 0.1) 0.6
All dimensions are in mm.

Figure 39. PowerSSO-12™ tape and reel shipment (suffix “TR”)

REEL DIMENSIONS
Base Q.ty 2500 Bulk Q.ty 2500 A (max) 330 B (min) 1.5 C (± 0.2) 13 F 20.2 G (+ 2 / -0) 12.4 N (min) 60 T (max) 18.4
TAPE DIMENSIONS
According to Electronic Industries Association (EIA) Standard 481 rev. A, Feb. 1986
Tape width W 12 Tape Hole Spacing P0 (± 0.1) 4 Component Spacing P 8 Hole Diameter D (± 0.05) 1.5 Hole Diameter D1 (min) 1.5 Hole Position F (± 0.1) 5.5 Compartment Depth K (max) 4.5 Hole Spacing P1 (± 0.1) 2
All dimensions are in mm.
End
Start
Top
cover
tape
500mm min
Empty components pockets saled with cover tape.
User direction of feed
No componentsNo components Components
500mm min
34/37 Doc ID 12272 Rev 9
Page 35
VND5050AJ-E / VND5050AK-E Package and packing information

5.5 PowerSSO-24™ packing information

Figure 40. PowerSS0-24
C
B
A
Figure 41. PowerSSO-24
TM
tube shipment (no suffix)
Base Qty 49 Bulk Qty 1225 Tube length (±0.5) 532 A 3.5 B 13.8 C (±0.1) 0.6
All dimensions are in mm.
TM
tape and reel shipment (suffix “TR”)
REEL DIMENSIONS
Base Qty 1000 Bulk Qty 1000 A (max) 330 B (min) 1.5 C (± 0.2) 13 F 20.2 G (+2 / -0) 24.4 N (min) 100 T (max) 30.4
TAPE DIMENSIONS
According to Electronic Industries Association (EIA) Standard 481 rev. A, Feb. 1986
Tape width W 24 Tape Hole Spacing P0 (± 0.1) 4 Component Spacing P 12 Hole Diameter D (± 0.05) 1.55 Hole Diameter D1 (min) 1.5 Hole Position F (± 0.1) 11.5 Compartment Depth K (max) 2.85 Hole Spacing P1 (± 0.1) 2
End
All dimensions are in mm.
Start
Top
cover
tape
500mm min
Empty components pockets sealed with cover tape.
User direction of feed
No componentsNo components Components
500mm min
Doc ID 12272 Rev 9 35/37
Page 36
Revision history VND5050AJ-E / VND5050AK-E

6 Revision history

Table 19. Document revision history

Date Revision Changes
30-Mar-2006 1 Initial release.
14-Apr-2006 2 PowerSSO-24 dimensions table update.
26-Apr-2007 3
14-May-2007 4
01-Jun-2007 5
04-Dec-2007 6
Reformatted
Figure 31 title corrected
Ta bl e 4 : corrected E Ta bl e 1 0: added dk1/k1, dk2/k2, dk3/k3, Δt
MAX
value.
DSENSE2H
. Added Figure 5. Updated Figure 6. Added Figure 7.
Ta bl e 1 2: Updated test level values III and IV for test pulse 5b and
notes. Added Section 3.4: Maximum demagnetization energy (VCC = 13.5V).
Figure 31: Thermal fitting model of a double channel HSD in PowerSSO-12™, Figure 35: Thermal fitting model of a double channel HSD in PowerSSO-24™: added notes.
Updated Table 10: Current sense (8V<V – changed t – added I
OL
DSENSE2H
parameter.
max value from 300 µs to 250µs.
CC
<16V):
Updated Section 4.1: PowerSSO-12™ thermal data: – Changed Figure 29: Rthj-amb vs PCB copper area in open box free
air condition (one channel on).
– Changed Figure 30: PowerSSO-12™ thermal impedance junction
ambient single pulse (one channel on).
– Updated Ta b le : :
R3 value changed from 7 to 4 °C/W. R4 values changed from 10 /10 /10 to 8 /8 /7 °C/W.
12-Feb-2008 7
Corrected typing error in Table 10: Current sense (8V<V changed I
Table 18: PowerSSO-24™ mechanical data:
– Deleted A (min) value
16-Jun-2009 8
– Changed A (max) value from 2.47 to 2.45 – Changed A2 (max) value from 2.40 to 2.35 – Changed a1 (max) value from 0.075 to 0.1 – Added F and k rows
Updated Figure 37: PowerSSO-24™ package dimensions.
21-Jul-2009 9
Updated Table 18: PowerSSO-24™ mechanical data: – Deleted G1 row – Added O, Q, S, T, and U rows
36/37 Doc ID 12272 Rev 9
test condition from VIN = 0V to VIN = 5V.
OL
<16V):
CC
Page 37
VND5050AJ-E / VND5050AK-E
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