Page 1
4 BIT PROGRAMMABLE SYNCHRONOUS BUCK
FEATURESFEATURES
Provides Single Chip Solution for Vcore,
GTL+ ,AGP Bus, 1.8V , 2.5V
Automatic Voltage Selection for AGP slot's
Vddq supply
4 Linear regulator controller on board to
achieve lowest system cost solution
Standby Vref provides reference for the ACPI
regulators
Designed to meet Intel Latest VRM specification for next generation micrprocessors
On board DAC programs the output voltage
from 1.3V to 2.05V
On board resistor dividers provides lowest
component count
Loss less Short Circuit Protection for all
outputs
Synchronous operation allows maximum
efficiency
Patented architecture allows fixed frequency
operation as well as 100% duty cycle during
dynamic load
Soft Start
High current totem pole driver for direct
driving of the external Power MOSFET
Power Good function Monitors all Outputs
OVP Circuitry Protects the Switcher Output
and generates a Fault output
APPLICATIONSAPPLICATIONS
Total Power Soloution for Next Generation Intel
Processor application
US3022
PLUS FOUR LDO CONTROLLER
PRELIMINARY DATASHEET
DESCRIPTIONDESCRIPTION
The US3022 is the first controller IC with five controller in
one package specifically designed to meet Intel specification for next generation microprocessor applications
requiring multiple on board regulators . The US3022 pro-
vides a single chip controller IC for the Vcore , 4
LDO controllers, one with the automatic select pin
that connects to the TYPE DETECT pin of the AGP
slot for the AGP Vddq supply, one for GTL+ , the
other for the 1.8V chip set regulator as well as 2.5V
for the clock as required for the next generation
PC applications. The US3022 typically uses Bipolar
transistors for Vout3(1.5V) and Vout4(1.8V) and Vout5
however if Vaux pin is connected to 12V, then
MOSFETs can also be used as external pass elements. No external resistor divider is necessary for
any of the regulators. The switching regulator feature
a patented topology that in combination with a few external components as shown in the typical application
circuit ,will provide well in excess of 20A of output current for an on- board DC/DC converter while automatically providing the right output voltage via the 5 bit internal DAC .The US3022 also features, loss less current
sensing for both switcher by using the Rds-on of
the high side Power MOSFET as the sensing resistor, an output under voltage shutdown that detects
short circuit condition for the linear outputs and
latches the system off, and a Power Good window
comparator that switches its open collector output low
when any one of the outputs is outside of a pre programmed window.
TYPICAL APPLICATIONTYPICAL APPLICATION
5V
3.3V
Vout2
Vout3
LINEAR
CONTROL
LINEAR
CONTROL
US3022
PACKAGE ORDER INFORMATIONPACKAGE ORDER INFORMATION
Ta (°C) Device Package
0 TO 70 US3022CW 28 pin Plastic SOIC WB
Rev. 1.0
11/2/99
LINEAR
CONTROL
SWITCHER
CONTROL
LINEAR
CONTROL
Vout5
3022app3-1.0
Vout1
Vout4
4-1
Page 2
US3022
ABSOLUTE MAXIMUM RATINGSABSOLUTE MAXIMUM RATINGS
V5 supply Voltage ........................................... 7V
V12 Supply Voltage ............................................ 20V
Storage Temperature Range ................................. -65 TO 150°C
Operating Junction Temperature Range .......... 0 TO 125°C
PACKAGE INFORMATIONPACKAGE INFORMATION
28 PIN WIDE BODY PLASTIC SOIC (W)
TOP VIEW
1
Drive2
2
Vsen5
3
Vref
4
VID3
5
VID2
6
VID1
7
VID0
8 21
PGood
9 20
Vsen2
10 19
Drive5
11 18
Select
12 17
SS
13 16
Fault / Rt
14
Vsen4 Drive4
28
27
26
25
24
23
22
15
V12
UGate
Phase
LGate
PGnd
OCSet
Vsen1
Fb
V5
Vsen3
Drive3
Gnd
Vaux
θJA =80°C/W
ELECTRICAL SPECIFICATIONSELECTRICAL SPECIFICATIONS
Unless otherwise specified ,these specifications apply over ,V12 = 12V, V5 = 5V and Ta=0 to 70°C. Typical values
refer to Ta =25°C. Low duty cycle pulse testing are used which keeps junction and case temperatures equal to the
ambient temperature.
PARAMETER SYM TEST CONDITION MIN TYP MAX UNITS
Supply UVLO Section
UVLO Threshold-12V Supply ramping up 10 V
UVLO Hysterises-12V 0.6 V
UVLO Threshold-5V Supply ramping up 4.4 V
UVLO Hysterises-5V 0.3 V
Supply Current
Operating Supply Current
V12 6 mA
V5 30
Switching Controllers; Vcore (Vsen 1) and AGP (Vsen 2)
VID Section (Vcore only)
DAC output voltage (note 1) 0.99Vs Vs 1.01Vs V
DAC Output Line Regulation 0.1 %
DAC Output Temp Variation 0.5 %
VID Input LO 0.8 V
VID Input HI 2 V
VID input internal pull-up
resistor to V5 27 kΩ
Vsen2 Voltage Select<0.8V 1.5 V
Select>2V 3.3 V
4-2
Rev. 1.0
11/2/99
Page 3
US3022
Error Comparator Section
Input bias current 2 uA
Input Offset Voltage -2 +2 mV
Delay to Output Vdiff=10mV 100 nS
Current Limit Section
C.S Threshold Set Current 200 uA
C.S Comp Offset Voltage -5 +5 mV
Hiccup Duty Cycle Css=0.1 uF 10 %
Output Drivers Section
Rise Time CL=3000pF 70 nS
Fall Time CL=3000pF 70 nS
Dead band Time Between
High side and Synch Drive
(Vcore Switcher Only) CL=3000pF 200 nS
Oscillator Section (internal)
Osc Frequency Rt=Open 217 Khz
1.8V Regulator (Vsen 4)
Vsense Voltage Vo4 Ta=25, Drive4 = Vsen4 1.800 V
Vsense Voltage 1.800 V
Input bias current 2 uA
Output Drive Current Vaux-Vdrive>0.6V 50 mA
1.5V Regulator (Vsen 3)
Vsense Voltage Vo3 Ta=25, Drive3 = Vsen3 1.500 V
Vsense Voltage 1.500 V
Input bias current 2 uA
Output Drive Current Vaux-Vdrive>0.6V 50 mA
2.5V Regulator (Vsen 5)
Vsense Voltage Vo5 Ta=25, Drive5 = Vsen5 2.500 V
Vsense Voltage 2.500 V
Input bias current 2 uA
Output Drive Current Vaux-Vdrive>0.6V 50 mA
Power Good Section
Vsen1 UV lower trip point Vsen1 ramping down 0.90Vs V
Vsen1 UV upper trip point Vsen1 ramping up 0.92Vs V
Vsen1 UV Hysterises .02Vs V
Vsen1 HV upper trip point Vsen1 ramping up 1.10Vs V
Vsen1 HV lower trip point Vsen1 ramping down 1.08Vs V
Vsen1 HV Hysterises .02Vs V
Vsen2 trip point Select<0.8V 1.100 V
Select>2V 2.560 V
Vsen4 trip point 1.320 V
Vsen3 trip point 1.140 V
Vsen5 trip point 1.875 V
Power Good Output LO RL=3mA 0.4 V
Power Good Output HI RL=5K pull up to 5V 4.8 V
Fault (Overvoltage) Section
Core O.V. upper trip point Vsen1 ramping up 1.17Vs V
Core O.V. lower trip point Vsen1 ramping down 1.15Vs V
FAULT Output HI Io=3mA 10 V
Soft Start Section
Soft Start Current OCset=0V , Phase=5V 20 uA
Note 1: Vs refers to the set point voltage given in Table 1.
Rev. 1.0
11/2/99
4-3
Page 4
US3022
Vref Section
Vref Initial Accuracy No Load,Ta=25 1.980 2.000 2.020 V
Vref Initial Accuracy No Load, Over Temp 1.960 2.000 2.040 V
Vref Change with Load No Load to 30K load -2 %
Vref Output Impedance 150 300 600 Ohm
VID3 VID2 VID1 VID0 Vs
1 1 1 1 1.30
1 1 1 0 1.35
1 1 0 1 1.40
1 1 0 0 1.45
1 0 1 1 1.50
1 0 1 0 1.55
1 0 0 1 1.60
1 0 0 0 1.65
0 1 1 1 1.70
0 1 1 0 1.75
0 1 0 1 1.80
0 1 0 0 1.85
0 0 1 1 1.90
0 0 1 0 1.95
0 0 0 1 2.00
0 0 0 0 2.05
Table 1 - Set point voltage vs. VID codes
PIN DESCRIPTIONSPIN DESCRIPTIONS
PIN# PIN SYMBOL
7 VID0
6 VID1
5 VID2
4 VID3
3 Vref
8 PGOOD
21 FB
1 Drive2
10 Drive5
Pin Description
LSB input to the DAC that programs the output voltage. This pin is TTL compatible that
realizes a logic “1” as either HI or Open. When left open,his pin is pulled up internally by
a 27kΩ resistor to 5V supply.
Input to the DAC that programs the output voltage. This pin is TTL compatible that realizes a logic “1” as either HI or Open. When left open,his pin is pulled up internally by a
27kΩ resistor to 5V supply.
Input to the DAC that programs the output voltage. This pin is TTL compatible that realizes a logic “1” as either HI or Open. When left open,his pin is pulled up internally by a
27kΩ resistor to 5V supply.
MSB input to the DAC that programs the output voltage. This pin is TTL compatible that
realizes a logic “1” as either HI or Open. When left open,his pin is pulled up internally by
a 27kΩ resistor to 5V supply.
This pin provides a 2V reference that remains on when the 5V pin is connected to the 5V
standby of the ATX supply. In this application, the Vref pin is used to provide reference for
the ACPI regulators.
This pin is an open collector output that switches LO when any of the outputs are outside
of the specified under voltage trip point. It also switches low when Vsen1 pin is more than
10% above the DAC voltage setting.
This pin provides the feedback for the synchronous switching regulator. Typically this pin
can be connected directly to the output of the switching regulator. However, a resistor
divider is recommended to be connected from this pin to vout1 and GND to adjust the
output voltage for any drop in the output voltage that is caused by the trace resistance.
The value of the resistor connected from Vout1 to FB1 must be less than 1000Ω.
This pin controls the gate of an external MOSFET for the AGP linear regulator.
This pin controls the gate of an external transistor for the 2.5V Clock linear regulator.
4-4
Rev. 1.0
11/2/99
Page 5
US3022
PIN# PIN SYMBOL
22 Vsen1
9 Vsen2
15 Drive4
23 OCSET
26 PHASE
12 SS
13 FAULT/Rt
18 Drive3
19 Vsen3
16 Vaux
14 Vsen4
17 GND
24 PGND
25 LGATE
27 UGATE
28 V12
20 V5
11 Select
2 Vsen5
Pin Description
This pin is internally connected to the undervoltage and overvoltage comparators sensing
the Vcore status. It must be connected directly to the Vcore supply.
This pin provides the feedback for the AGP linear regulator. The Select pin when connected to the "Type Detect" pin of the AGP slot automatically selects the right voltage for
the AGP Vddq.
This pin controls the gate of an external MOSFET for the 1.8V chip set linear regulator.
This pin is connected to the Drain of the power MOSFET of the Core supply and it
provides the positive sensing for the internal current sensing circuitry. An external resistor programs the C.S threshold depending on the Rds of the power MOSFET. An external
capacitor is placed in parallel with the programming resistor to provide high frequency
noise filtering.
This pin is connected to the Source of the power MOSFET for the Core supply and it
provides the negative sensing for the internal current sensing circuitry.
This pin provides the soft start for all the regulators. An internal current source charges
an external capacitor that is connected from this pin to GND which ramps up the outputs
of the regulators, preventing the outputs from overshooting as well as limiting the input
current. The second function of the Soft Start cap is to provide long off time (HICCUP) for
the synchronous MOSFET during current limiting.
This pin has dual function. It acts as an output of the OVP circuitry or it can be used to
program the frequency using an external resistor . When used as a fault detector, if any
of the switcher outputs exceed the OVP trip point, the FAULT pin switches to 12V and
the soft start cap is discharged. If the FAULT pin is to be connected to any external
circuitry, it needs to be buffered.
This pin controls the gate of an external transistor for the 1.5V GTL+ linear regulator.
This pin provides the feedback for the linear regulator that its output drive is Drive3.
This pin is normally connected to 3.3V or 5V input. When connected to the 12V supply,
it provides gate drive voltage for the # 3, #4 and #5 (Drive 3,4,5) linear regulator's pass
transistors in case MOSFET transistors are being used instead of Bipolars.
This pin provides the feedback for the linear regulator that its output drive is Drive4.
This pin serves as the ground pin and must be connected directly to the ground plane.
This pin serves as the Power ground pin and must be connected directly to the GND
plane close to the source of the synchronous MOSFET. A high frequency capacitor
(typically 1 uF) must be connected from V12 pin to this pin for noise free operation.
Output driver for the synchronous power MOSFET for the Core supply.
Output driver for the high side power MOSFET for the Core supply.
This pin is connected to the 12 V supply and serves as the power Vcc pin for the output
drivers. A high frequency capacitor (typically 1 uF) must be placed close to this pin and
PGND pin and be connected directly from this pin to the GND plane for the noise free
operation.
5V supply voltage. A high frequency capacitor (0.1 to 1 uF) must be placed close to this
pin and connected from this pin to the GND plane for noise free operation.
This pin provides automatic voltage selection for the AGP switching regulator. When it is
pulled LO, the voltage is 1.5V and when left open or pulled to HI, the voltage is 3.3V.
This pin provides the feedback for the linear regulator that its output drive is Drive5.
Rev. 1.0
11/2/99
4-5
Page 6
US3022
BLOCK DIAGRAMBLOCK DIAGRAM
V12
V5
Vsen1
PGood
Vsen3
Vsen4
Vaux
Drive4
Drive3
Select
Drive2
Vsen2
Drive5
UVLO
1.26V
Enable
Fb
1.17Vset
Over
Voltage
Vset
Enable
V12
UGate
PWM
1.1Vset
+
Slope
Comp
Osc
Control
V12
LGate
Phase
Soft
0.9Vset
Enable
Start &
Fault
Logic
R
3R
Over
Current
200uA
Vset
OCSet
PGnd
Gnd
Fault / Rt
SS
VID0
1.5V
R
3R
R
3R
3.3V
2.5V
4Bit
DAC
+
2V
VID1
VID2
VID3
Vref
4-6
Vsen5
3022blk1-1.0
Figure 1 - Simplified block diagram of the US3022.
Rev. 1.0
11/2/99
Page 7
TYPICAL APPLICATIONTYPICAL APPLICATION
12V
3.3Vin
Vout2(1.5V or 3.3V)
TYPE DETECT#
Vout3 (1.5V)
Vout4(1.8V)
Vout5(2.5V)
C6
+
220UF
C13
+
680uf
C15
+
680uf
Q6
C16
+
680uf
PMBT2222A
C17
+
220uf
Q5
MJD200
Q4
MJD200
Q2
IRL3103S
C5
1UF
16
1
9
11
18
19
15
14
10
2
2328
US3022
17 12
C18
0.1uF
R1
2.21K
US3022
+5Vin
L1
+
2.5UH
1UH
C3
1500uf
6MV1500DX
C2
C4
220PF
R2
27
5.1
26
R3
25
5.1
24
22
21
20
C14
1UF
5VSB
8
VID0
7
VID1
6
VID2
5
VID3
4
Vref(2V)
3
Fault/Rt
13
C19
0.1uF
+
1500uf
Q1
IRL3103S
L2
Q3
IRL3103S
The Vref(2V) can be used to provide reference for
the ACPI regulatos. In this application the ACPI
regulators are designed using op-amp and discrete
transistors.
C1
+
680uf
VCORE
C7
C8
C9
C10
C11
+
+
+
1500uf
1500uf
PGood
1500uf
+
1500uf
C12
+
+
1500uf
1500uf
6MV1500DX
Figure 2 - Typical application of US3022 for an on board DC-DC converter providing power for the Vcore , GTL+,
1.8V chip set supply, 2.5V clock supply as well as auto select AGP supply for the next generation PC applications.
Rev. 1.0
11/2/99
4-7
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