Datasheet US3018CW Datasheet (UNISEM)

Page 1
5 BIT PROGRAMMABLE SYNCHRONOUS BUCK PLUS
LDO CONTROLLER AND 200mA LDO ON BOARD
FEATURESFEATURES
Provides Single Chip Solution for Vcore, GTL+ & Clock Supply 200 mA On board LDO regulator Designed to meet the latest Intel specification for Pentium II On board DAC programs the output voltage from 1.3V to 3.5V Linear regulator controller on board for 1.5V GTL+ supply Loss less Short Circuit Protection with HICCUP Synchronous operation allows maximum effi­ciency Patented architecture allows fixed frequency operation as well as 100% duty cycle during dynamic load Soft Start High current totem pole driver for direct driv­ing of the external Power MOSFET Power Good function Monitors all Outputs OVP Circuitry Protects the Switcher Output and generates a Fault signal Thermal Shutdown Logic Level Enable Input
APPLICATIONSAPPLICATIONS
Total Power Soloution for Pentium II processor application
US3018
PRELIMINARY DATASHEET
DESCRIPTIONDESCRIPTION
The US3018 controller IC is specifically designed to meet Intel specification for Pentium II microprocessor ap­plications as well as the next generation of P6 family processors. The US3018 provides a single chip con-
troller IC for the Vcore , LDO controller for GTL+ and an internal 200mA regulator for clock supply which are required for the Pentium II applications.
These devices feature a patented topology that in com­bination with a few external components as shown in the typical application circuit ,will provide in excess of 18A of output current for an on- board DC/DC converter while automatically providing the right output voltage via the 5 bit internal DAC. The US3018 also features, loss
less current sensing for both switchers by using the Rds-on of the high side Power MOSFET as the sens­ing resistor, internal current limiting for the clock supply, a Power Good window comparator that switches
its open collector output low when any one of the out­puts is outside of a pre programmed window. Other fea­tures of the device are ; Undervoltage lockout for both 5V and 12V supplies, an external programmable soft start function , programming the oscillator frequency via an external resistor, OVP circuitry for both switcher out­puts and an internal thermal shutdown.
TYPICAL APPLICATIONTYPICAL APPLICATION
5V
US3018
3.3V
LINEAR
Vout3
Notes: Pentium II is trade mark of Intel Corp.
CONTROL
PACKAGE ORDER INFORMATIONPACKAGE ORDER INFORMATION
Ta (°C) Device Package
0 TO 70 US3018CW 24 pin Plastic SOIC WB
Rev. 1.4 12/8/00
SWITCHER1
CONTROL
LINEAR
REGULATOR
Vout1
Vout2
3018app3-1.1
4-1
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US3018
ABSOLUTE MAXIMUM RATINGSABSOLUTE MAXIMUM RATINGS
V5 supply Voltage ........................................... 7V
V12 Supply Voltage ............................................ 20V
Storage Temperature Range ................................. -65 TO 150°C
Operating Junction Temperature Range .......... 0 TO 125°C
PACKAGE INFORMATIONPACKAGE INFORMATION
24 PIN WIDE BODY PLASTIC SOIC (W)
TOP VIEW
1
V12
2
VID4
3
VID3
4
VID2
5
VID1
6
VID0
7
PGood
8 17
V5
9 16
SS
10 15
Fault / Rt
11 14
Fb2
12 13
Vin2 Vout2
24 23 22 21 20 19 18
UGate1 Phase1 LGate1 PGnd OCSet1 Vsen1 Fb1 En Fb3 Gate3 Gnd
θJA =80°C/W
ELECTRICAL SPECIFICATIONSELECTRICAL SPECIFICATIONS
Unless otherwise specified ,these specifications apply over ,V12 = 12V, V5 = 5V and Ta=0 to 70°C. Typical values refer to Ta =25°C. Low duty cycle pulse testing are used which keeps junction and case temperatures equal to the
ambient temperature.
PARAMETER SYM TEST CONDITION MIN TYP MAX UNITS Supply UVLO Section
UVLO Threshold-12V Supply ramping up 10 V UVLO Hysterises-12V 0.4 V UVLO Threshold-5V Supply ramping up 4.3 V UVLO Hysterises-5V 0.3 V
Supply Current
Operating Supply Current
I12 V12 6 mA
I5 V5 20
Switching Controller, Vcore (Vout 1) VID Section
DAC output voltage (note 1) Vdac 0.99Vs Vs 1.01Vs V DAC Output Line Regulation 0.1 % DAC Output Temp Variation 0.5 % VID Input LO 0.8 V VID Input HI 2 V VID input internal pull-up 27 k resistor to V5
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Rev. 1.4
12/8/00
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US3018
Error Comparator Section
Input bias current 2 uA Input Offset Voltage -2 +2 mV Delay to Output Vdiff=10mV 100 nS
Current Limit Section
C.S Threshold Set Current 200 uA C.S Comp Offset Voltage -5 +5 mV Hiccup Duty Cycle Css=0.1 uF 10 %
Output Drivers Section
Rise Time CL=3000pF 70 nS Fall Time CL=3000pF 70 nS Dead band Time Between High side and Synch Drive Vcore Switcher Only CL=3000pF 200 nS
Oscillator Section (internal)
Osc Frequency 200 Khz
2.5V Regulator (Vout 2)
Reference Voltage Vo2 Ta=25, Vout2 = FB2 1.260 V Reference Voltage 1.260 V Dropout Voltage Io = 200 mA 0.6 V Load Regulation 1mA< Io <200 mA 0.5 % Line Regulation 3.1V<Vin2<4V, Vo=2.5V 0.2 % Input bias current 2 uA Output Current 200 mA Current limit 300 mA Thermal Shutdown 145 °C
1.5V Regulator (Vout 3)
Reference Voltage Vo3 Ta=25, GATE3 = FB3 1.260 V Reference Voltage 1.260 V Input bias current 2 uA Output Drive Current 50 mA
Power Good Section
Core U.V lower trip point Vsen1 ramping down 0.90Vs V Core U.V upper trip point Vsen1 ramping up 0.92Vs V Core U.V Hysterises .02Vs V Core O.V upper trip point Vsen1 ramping up 1.10Vs V Core O.V lower trip point Vsen1 ramping down 1.08Vs V Core O.V Hysterises .02Vs V FB2 lower trip point FB2 ramping down 0.95 V FB2 upper trip point FB2 ramping up 1.05 V FB3 lower trip point FB3 ramping down 0.95 V FB3 upper trip point FB3 ramping up 1.05 V Power Good Output LO RL=3mA 0.4 V Power Good Output HI RL=5K pull up to 5V 4.8 V
Fault (Overvoltage) Section
Core O.V upper trip point Vsen1 ramping up 1.17Vs V Core O.V lower trip point Vsen1 ramping down 1.15Vs V Vin2 upper trip point Vin2 ramping up 4.3 V Vin2 lower trip point Vin2 ramping down 4.2 V FAULT Output HI Io=3mA 10 V
Soft Start Section
Pull up resistor to 5V OCset=0V , Phase=5V 23 K Note 1: Vs refers to the set point voltage given in Table 1.
Rev. 1.4 12/8/00
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US3018
Enable Section
En pin input LO voltage Venl Regulator OFF 0.8 V En pin input HI voltage Venh Regulator ON 2 V En pin input LO current Ven=0V to 0.8V 0.01 uA En pin input HI current Ven=2V to 5V 20 uA
D4 D3 D2 D1 D0 Vs D4 D3 D2 D1 D0 Vs
0 1 1 1 1 1.30 1 1 1 1 1 2.0 0 1 1 1 0 1.35 1 1 1 1 0 2.1 0 1 1 0 1 1.40 1 1 1 0 1 2.2 0 1 1 0 0 1.45 1 1 1 0 0 2.3 0 1 0 1 1 1.50 1 1 0 1 1 2.4 0 1 0 1 0 1.55 1 1 0 1 0 2.5 0 1 0 0 1 1.60 1 1 0 0 1 2.6 0 1 0 0 0 1.65 1 1 0 0 0 2.7 0 0 1 1 1 1.70 1 0 1 1 1 2.8 0 0 1 1 0 1.75 1 0 1 1 0 2.9 0 0 1 0 1 1.80 1 0 1 0 1 3.0 0 0 1 0 0 1.85 1 0 1 0 0 3.1 0 0 0 1 1 1.90 1 0 0 1 1 3.2 0 0 0 1 0 1.95 1 0 0 1 0 3.3 0 0 0 0 1 2.00 1 0 0 0 1 3.4 0 0 0 0 0 2.05 1 0 0 0 0 3.5
PIN DESCRIPTIONSPIN DESCRIPTIONS
PIN# PIN SYMBOL
6 VID0
5 VID1
4 VID2
3 VID3
2 VID4
7 PGOOD
18 FB1
Pin Description
LSB input to the DAC that programs the output voltage. This pin is TTL compatible that realizes a logic “1” as either HI or Open. When left open,his pin is pulled up internally by a 27k resistor to 5V supply. Input to the DAC that programs the output voltage. This pin is TTL compatible that realizes a logic “1” as either HI or Open. When left open,his pin is pulled up internally by a 27k resistor to 5V supply. Input to the DAC that programs the output voltage. This pin is TTL compatible that realizes a logic “1” as either HI or Open. When left open,his pin is pulled up internally by a 27k resistor to 5V supply. MSB input to the DAC that programs the output voltage. This pin is TTL compatible that realizes a logic “1” as either HI or Open. When left open,his pin is pulled up internally by a 27k resistor to 5V supply. This pin selects a range of output voltages for the DAC.When in the LOW state the range is 1.3V to 2.05V and when it switches to HI state the range is 2.0V to 3.5V. This pin is TTL compatible that realizes a logic “1” as either HI or Open. When left open,his pin is pulled up internally by a 27k resistor to 5V supply. This pin is an open collector output that switches LO when any of the outputs are outside of the specified under voltage trip point. It also switches low when Vsen1 pin is more than 10% above the DAC voltage setting. This pin provides the feedback for the synchronous switching regulator. Typically this pin can be connected directly to the output of the switching regulator. However, a resistor divider is recommended to be connected from this pin to vout1 and GND to adjust the output voltage for any drop in the output voltage that is caused by the trace resistance. The value of the resistor connected from Vou1 to FB1 must be less than 100.
Table 1 - Set point voltage vs. VID codes
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Rev. 1.4
12/8/00
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US3018
PIN# PIN SYMBOL
19 VSEN1 12 VIN2 20 OCSET1
23 PHASE1 9 SS
10 FAULT/Rt
15 GATE3 16 FB3 13 VOUT2 11 FB2 14 GND 21 PGND
22 LGATE1 24 UGATE1 1 V12
8 V5 17 En
Pin Description
This pin is internally connected to the undervoltage and overvoltage comparators sensing the Vcore status. It must be connected directly to the Vcore supply. This pin is the input that provides power for the internal LDO regulator. It is also monitored for the under voltage and over voltage conditions. This pin is connected to the Drain of the power MOSFET of the Core supply and it provides the positive sensing for the internal current sensing circuitry. An external resis­tor programs the C.S threshold depending on the Rds of the power MOSFET. An external capacitor is placed in parallel with the programming resistor to provide high frequency noise filtering. This pin is connected to the Source of the power MOSFET for the Core supply and it provides the negative sensing for the internal current sensing circuitry. This pin provides the soft start for the switching regulator. An internal resistor charges an external capacitor that is conected from 5V supply to this pin which ramps up the outputs of the switching regulators, preventing the outputs from overshooting as wellas limiting the input current. The second function of the Soft Start cap is to provide long off time (HICCUP) for the synchronous MOSFET during current limiting. This pin has dual function. It acts as an output of the OVP circuitry or it can be used to program the frequency using an external resistor . When used as a fault detector, if the switcher output exceed the OVP trip point, the FAULT pin switches to 12V and the soft start cap is discharged. If the FAULT pin is to be connected to any external circuitry, it needs to be buffered as shown in the application circuit. This pin controls the gate of an external transistor for the 1.5V GTL+ linear regulator. This pin provides the feedback for the linear regulator that its output drive is GATE3. This pin is the output of the internal LDO regulator. This pin provides the feedback for the internal LDO regulator that its output is Vout4. This pin serves as the ground pin and must be conected directly to the ground plane. This pin serves as the Power ground pin and must be conected directly to the GND plane close to the source of the synchronous MOSFET. A high frequency capacitor (typically 1 uF) must be connected from V12 pin to this pin for noise free operation. Output driver for the synchronous power MOSFET for the Core supply. Output driver for the high side power MOSFET for the Core supply. This pin is connected to the 12 V supply and serves as the power Vcc pin for the output drivers. A high frequency capacitor (typically 1 uF) must be placed close to this pin and PGND pin and be connected directly from this pin to the GND plane for the noise free operation. 5V supply voltage. A high frequency capacitor (0.1 to 1 uF) must be placed close to this pin and connected from this pin to the GND plane for noise free operation. This pin is a TTL compatible Enable pin. When this pin is left open or pulled high, the device is enabled and when is pulled low, it will disable the switcher and the LDO controller (Vout 3) leaving the internal 200mA regulator operational. When signal is given to enable the device, both switcher and Vout 3 will go through soft start, the same as during start up.
Rev. 1.4 12/8/00
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US3018
BLOCK DIAGRAMBLOCK DIAGRAM
V12
VID0 VID1 VID2 VID3 VID4
Vsen1
Fb3
Gate3
Vin2
Vout2
Fb2
PGood
En
V5
Enable
UVLO
Vset
5Bit
DAC
V12
1.26V 0.9V
V5
4.3V
1.17Vset
2.5V
1.1Vset
0.9Vset
Over
Voltage
Enable
+
Slope Comp
Soft
Start &
Fault Logic
Vset
Enable
Osc
PWM
Control
Over
Current
200uA
V12
V12
3018blk1-1.2
Fb1 UGate1
LGate1
Phase1 OCSet1
Fault / Rt
SS
PGnd Gnd
4-6
Figure 1 - Simplified block diagram of the US3018
Rev. 1.4
12/8/00
Page 7
TYPICAL APPLICATIONTYPICAL APPLICATION
US3018
12V
5V
3.3V
Vout3
1.5V
Vout4
2.5V
R22
L1
C17
C18
C3
C19
R5
R6
R7
3018app1-1.6
R8
1
V12
V5
8 23
Fault/Rt
Vin2
12
Gate3
15
Fb3
Vout2
13
Fb2 Gnd
U1
1411
20
OCSet1
UGate1 24
Phase1
LGate1
PGnd
Vsen1
Fb1
En 17
PGood 7
VID0 VID1 VID2 VID3 VID4
SS
9
C9
C9
R13
R14
22
2110 19 18
616 5 4 3 2
5V
5V
Q3
Q4 C13
R19
C2
C1
Q2
R15
R17
C14C10R12C8
L3
Vout1
C16
R16 R21
C15
1.8V - 3.5V
PGood
Figure 2 - Typical application of US3018 for an on board DC-DC converter providing power for the Vcore
, GTL+ & Clock supply for the Deschutes and the next generation processor applications.
Rev. 1.4 12/8/00
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US3018
US3018 Application Parts List
Ref Desig Description Qty Part # Manuf Q2 MOSFET 1 IRLR024, TO252 package IR Q3 MOSFET 1 IRL3103S, TO263 package IR Q4 MOSFET with Schottky 1 IRL3103D1S, TO263 package IR L1 Inductor 1 L=1uH, 5052 core with 4 turns of Micro Metal
1.0mm wire
L3 Inductor 1 L=2.7uH, 5052B core with 7 turns of Micro Metal
1.2mm wire C1,17 Capacitor, Electrolytic 2 6MV1000GX, 1000uF,6.3V Sanyo C2 Capacitor, Electrolytic 1 10MV470GX, 470uF,10V Sanyo C3 Capacitor, Electrolytic 1 10MV1200GX, 1200uF,10V Sanyo C8 Capacitor, Ceramic 1 1uF, 0805 C9,15,19 Capacitor, Ceramic 3 1uF, 0603 C10 Capacitor, Ceramic 1 220pF, 0603 C13 Capacitor, Ceramic 1 1000pF, 0603 C14 Capacitor, Electrolytic 2 10MV1200GX, 1200uF,10V Sanyo C16 Capacitor, Electrolytic 6 6MV1500GX, 1500uF,6.3V, Sanyo C18 Capacitor, Electrolytic 1 6MV150GX, 150uF,6.3V Sanyo R5 Resistor 1 19.1, 1%, 0603 R6,7,8 Resistor 3 100, 1%, 0603 R12 Resistor 1 3.3k, 5%, 0603 R13,14,15 Resistor 3 4.7, 5%, 1206 R16,17,21 Resistor 3 2.2k, 1%, 0603 R22 Resistor 1 10, 5%, 0603
4-8
Rev. 1.4
12/8/00
Page 9
TYPICAL APPLICATIONTYPICAL APPLICATION
(Dual Layout with HIP6018)
12V
3.3V
L1
5V
C2
C1
C3
R22
R11
1
V12
V5
8 23
(Fault)
C19
Fault/Rt (Rt)
Vin2
12
U1
20
OCSet1
UGate1 24
Phase1
LGate1
PGnd
Vsen1
Fb1
En
(Comp1)
US3018
C14C10R12C8
R13
R14
22
2110 19 18
17
C11
Q3
Q4 C13
C12
R18
R15
R17
R16 R21
C15
R19
L3
Vout1
C16
1.8V - 3.5V
PGood
Vout3
1.5V
Vout4
2.5V 1411
C20 C9
PGood 7
VID0 VID1 VID2 VID3 VID4
SS
9
616 5 4 3 2
5V
Q2
R5
C17
C18
R6
R7
R8
15
13
3018app2-1.6
Gate3
Fb3
Vout2
Fb2 Gnd
Figure 3 - Typical application of US3018 in a dual layout with HIP6018 for an on board DC-DC converter providing
power for the Vcore , GTL+ & Clock supply for the Deschutes and the next generation processor applications.
Components that need to be modified to make the dual layout work for US3018 and HIP6018.
Part # R11 R18 C9 C11 C12 C19 C20 HIP6018 O V O V V O V US3018 S O V O O V O
S - Short O - Open V - See Unisem or Harris parts list for the value.
Rev. 1.4 12/8/00
Table 2 - Dual layout component table
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US3018
US3018 Application Parts List Dual Layout with HIP6018
Ref Desig Description Qty Part # Manuf Q2 MOSFET 1 IRLR024, TO252 package IR Q3 MOSFET 1 IRL3103S, TO263 package IR Q4 MOSFET with Schottky 1 IRL3103D1S, TO263 package IR L1 Inductor 1 L=1uH, 5052 core with 4 turns of Micro Metal
1.0mm wire
L3 Inductor 1 L=2.7uH, 5052B core with 7 turns of Micro Metal
1.2mm wire C1,17 Capacitor, Electrolytic 2 6MV1000GX, 1000uF,6.3V Sanyo C2 Capacitor, Electrolytic 1 10MV470GX, 470uF,10V Sanyo C3 Capacitor, Electrolytic 1 10MV1200GX, 1200uF,10V Sanyo C8 Capacitor, Ceramic 1 1uF, 0805 C9,15,19 Capacitor, Ceramic 3 1uF, 0603 C10 Capacitor, Ceramic 1 220pF, 0603 C11,12,20 Capacitor, Ceramic 3 See Table 2, dual layout component
0603 * 3 C13 Capacitor, Ceramic 1 1000pF, 0603 C14 Capacitor, Electrolytic 2 10MV1200GX, 1200uF,10V Sanyo C16 Capacitor, Electrolytic 6 6MV1500GX, 1500uF,6.3V, Sanyo C18 Capacitor, Electrolytic 1 6MV150GX, 150uF,6.3V Sanyo R5 Resistor 1 19.1, 1%, 0603 R6,7,8 Resistor 3 100, 1%, 0603 R11 Resistor 1 0Ω, 0603 R12 Resistor 1 3.3k, 5%, 0603 R13,14,15 Resistor 3 4.7, 5%, 1206 R16,17,21 Resistor 3 2.2k, 1%, 0603 R18 Resistor 1 See Table 2, dual layout component
0603 * 1 R19 Resistor 1 220k, 1%, 0603 R22 Resistor 1 10, 5%, 0603
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Rev. 1.4
12/8/00
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US3018
Application InformationApplication Information
An example of how to calculate the components for the application circuit is given below. Assuming, two set of output conditions that this regula­tor must meet for Vcore : a) Vo=2.8V , Io=14.2A, Vo=185mV, ∆Io=14.2A b) Vo=2V , Io=14.2A, Vo=140mV, ∆Io=14.2A The regulator design will be done such that it meets the worst case requirement of each condition.
Output Capacitor Selection
The first step is to select the output capacitor. This is done primarily by selecting the maximum ESR value that meets the transient voltage budget of the total ∆Vo specification. Assuming that the regulators DC initial accuracy plus the output ripple is 2% of the output volt­age, then the maximum ESR of the output capacitor is calculated as :
ESR =
The Sanyo MVGX series is a good choice to achieve both the price and performance goals. The 6MV1500GX , 1500uF, 6.3V has an ESR of less than 36 m typ . Selecting 6 of these capacitors in parallel has an ESR of 6 m which achieves our low ESR goal. Other type of Electrolytic capacitors from other manu­facturers to consider are the Panasonic “FA” series or the Nichicon “PL” series.
Reducing the Output Capacitors Using Voltage Level Shifting Technique
The trace resistance or an external resistor from the output of the switching regulator to the Slot 1 can be used to the circuit advantage and possibly reduce the number
of output capacitors, by level shifting the DC regu­lation point when transitioninig from light load to full load and vice versa. To accomplish this, the out-
put of the regulator is typically set about half the DC drop that results from light load to full load. For example, if the total resistance from the output capacitors to the Slot 1 and back to the GND pin of the 3018 is 5m and if the total I, the change from light load to full load is 14A, then the output voltage measured at the top of the resistor divider which is also connected to the output capacitors in this case, must be set at half of the 70 mV or 35mV higher than the DAC voltage setting. This in­tentional voltage level shifting during the load transient
100
1427.
m
eases the requirement for the output capacitor ESR at the cost of load regulation. One can show that the new ESR requirement eases up by half the total trace re- sistance. For example, if the ESR requirement of the output capacitors without voltage level shifting must be 7m then after level shifting the new ESR will only need to be 8.5m if the trace resistance is 5m (7+5/2=9.5). However, one must be careful that the combined “volt­age level shifting” and the transient response is still within the maximum tolerance of the Intel specification. To in­sure this, the maximum trace resistance must be less than: Rs 2(Vspec - 0.02*Vo - Vo)/I Where : Rs=Total maximum trace resistance allowed Vspec=Intel total voltage spec Vo=Output voltage
Vo=Output ripple voltageI=load current step
For example, assuming: Vspec=±140 mV=±0.1V for 2V output Vo=2V
Vo=assume 10mV=0.01VI=14.2A
Then the Rs is calculated to be: Rs 2(0.140 - 0.02*2 - 0.01)/14.2=12.6m However, if a resistor of this value is used, the maximum power dissipated in the trace (or if an external resistor is being used) must also be considered. For example if Rs=12.6 m , the power dissipated is (Io^2)*Rs=(14.2^2)*12.6=2.54W. This is a lot of power to be dissipated in a system. So, if the Rs=5m, then the power dissipated is about 1W which is much more ac­ceptable. If level shifting is not implemented, then the maximum output capacitor ESR was shown previously to be 7m which translated to 6 of the 1500uF, 6MV1500GX type Sanyo capacitors. With Rs=5m, the maximum ESR becomes 9.5m which is equivalent to
4 caps. Another important consideration is that if a trace is being used to implement the resistor, the power dissipated by the trace increases the case temperature of the output capacitors which could seriously effect the life time of the output capaci­tors.
Output Inductor Selection
The output inductance must be selected such that un­der low line and the maximum output voltage condition, the inductor current slope times the output capacitor ESR is ramping up faster than the capacitor voltage is drooping during a load current step.
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US3018
However if the inductor is too small , the output ripple current and ripple voltage become too large. One solu­tion to bring the ripple current down is to increase the switching frequency , however that will be at the cost of reduced efficiency and higher system cost. The follow­ing set of formulas are derived to achieve the optimum performance without many design iterations. The maximum output inductance is calculated using the following equation :
L = ESR * C * ( Vinmin - Vomax ) / ( 2* ∆I )
Where : Vinmin = Minimum input voltage For Vo = 2.8 V , I = 14.2 A L =0.006 * 9000 * ( 4.75 - 2.8) / (2 * 14.2) = 3.7 uH Assuming that the programmed switching frequency is set at 200 KHZ , an inductor is designed using the Micrometals’ powder iron core material. The summary of the design is outlined below :
The selected core material is Powder Iron , the selected core is T50-52D from Micro Metal wounded with 8 Turns of # 16 AWG wire, resulting in 3 uH inductance with 3 m of DC resistance.
Assuming L = 3 uH and the switching frequency ; Fsw = 200 KHZ , the inductor ripple current and the output ripple voltage is calculated using the following set of equations : T = 1/Fsw T Switching Period D ( Vo + Vsync ) / ( Vin - Vsw + Vsync ) D Duty Cycle Ton = D * T Vsw High side Mosfet ON Voltage = Io * Rds Rds Mosfet On Resistance Toff = T - Ton Vsync Synchronous MOSFET ON Voltage=Io * Rds
Ir = ( Vo + Vsync ) * Toff /LIr Inductor Ripple CurrentVo = Ir * ESRVo Output Ripple Voltage
In our example for Vo = 2.8V and 14.2 A load , Assum­ing IRL3103 MOSFET for both switches with maximum on resistance of 19 m, we have : T = 1 / 200000 = 5 uSec Vsw =Vsync= 14.2*0.019=0.27 V D ( 2.8 + 0.27 ) / ( 5 - 0.27 + 0.27 ) = 0.61 Ton = 0.61 * 5 = 3.1 uSec Toff = 5 - 3.1 = 1.9 uSec
Ir = ( 2.8 + 0.27 ) * 1.9 / 3 = 1.94 AVo = 1.94 * .006 = .011 V = 11 mV
Power Component Selection
Assuming IRL3103 MOSFETs as power components, we will calculate the maximum power dissipation as fol­lows: For high side switch the maximum power dissipation happens at maximum Vo and maximum duty cycle. Dmax ( 2.8 + 0.27 ) / ( 4.75 - 0.27 + 0.27 ) = 0.65 Pdh = Dmax * Io^2*Rds(max) = 0.65*14.2^2*0.029=3.8 W Rds(max)=Maximum Rds-on of the MOSFET at 125°C For synch MOSFET, maximum power dissipation hap­pens at minimum Vo and minimum duty cycle. Dmin ( 2 + 0.27 ) / ( 5.25 - 0.27 + 0.27 ) = 0.43 Pds = (1-Dmin)*Io^2*Rds(max) =(1 - 0.43) * 14.2^2 * 0.029 = 3.33 W
Heatsink Selection
Selection of the heat sink is based on the maximum allowable junction temperature of the MOSFETS. Since we previously selected the maximum Rds-on at 125°C, then we must keep the junction below this temperature. Selecting TO220 package gives θjc=1.8°C/W ( From the venders’ datasheet ) and assuming that the selected heatsink is Black Anodized , the Heat sink to Case ther­mal resistance is ; θcs=0.05°C/W , the maximum heat sink temperature is then calculated as : Ts = Tj - Pd * (θjc + θcs) Ts = 125 - 3.82 * (1.8 + 0.05) = 118 °C With the maximum heat sink temperature calculated in the previous step, the Heat Sink to Air thermal resis­tance (θsa) is calculated as follows : Assuming Ta=35 °C T = Ts - Ta = 118 - 35 = 83 °C Temperature Rise Above Ambient
θsa = T/Pd θsa = 83 / 3.82 = 22 °C/W
Next , a heat sink with lower θsa than the one calcu­lated in the previous step must be selected. One way to do this is to simply look at the graphs of the “Heat Sink Temp Rise Above the Ambient” vs. the “Power Dissipa­tion” given in the heatsink manufacturers’ catalog and select a heat sink that results in lower temperature rise than the one calculated in previous step. The following heat sinks from AAVID and Thermaloy meet this crite­ria.
Co. Part # Thermalloy 6078B AAVID 577002
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US3018
Following the same procedure for the Schottcky diode results in a heatsink with θsa = 25 °C/W. Although it is possible to select a slightly smaller heatsink, for sim­plicity the same heatsink as the one for the high side MOSFET is also selected for the synchronous MOSFET.
Switcher Current Limit Protection
The US3018 uses the MOSFET Rds-on as the sensing resistor to sense the MOSFET current and compares to a programmed voltage which is set externally via a re­sistor (Rcs) placed between the drain of the MOSFET and the “CS+” terminal of the IC as shown in the appli­cation circuit. For example, if the desired current limit point is set to be 22A for the synchronous and 16A for the non synchronous , and from our previous selection, the maximum MOSFET Rds-on=19m, then the cur­rent sense resistor Rcs is calculated as : Vcs=IcL*Rds=22*0.019=0.418V Rcs=Vcs/Ib=(0.418V)/(200uA)=2.1k Where: Ib=200uA is the internal current setting of the US3018
Switcher Frequency Selection
For the 1.5V and 2A load: Pd = (3.3 - 1.5)*2=3.6 W Assuming Tj-max=125°C Ts = Tj - Pd * (θjc + θcs) Ts = 125 - 3.6 * (1.8 + 0.05) = 118 °C With the maximum heat sink temperature calculated in the previous step, the Heat Sink to Air thermal resis­tance (θsa) is calculated as follows : Assuming Ta=35 °C T = Ts - Ta = 118 - 35 = 83 °C Temperature Rise Above Ambient
θsa = T/Pd θsa = 83 / 3.6 = 23 °C/W
The same heat sink as the one selected for the switcher MOSFETs is also suitable for the 1.5V regulator.
2.5V, Clock Supply The US3018 provides an internal ultra low dropout
regulator with a minimum of 200mA current capabil-
ity that converts 3.3V supply to a programmable regu­lated 2.5V supply to power the clock chip. The internal regulator has short circuit protection with internal ther­mal shutdown.
The US3018 frequency is internally set at 200kHz with no external timing resistor. However, it can be adjusted up by using an external resistor from Rt pin to GND or can be adjusted down if the resistor is connected to the 12V supply.
1.5V, GTL+ Supply LDO Power MOSFET Selection
The first step in selectiong the power MOSFET for the
1.5V linear regulator is to select its maximum Rds-on of the pass transistor based on the input to output Dropout voltage and the maximum load current. Rds(max)=(Vin - Vo)/IL For Vo=1.5V, and Vin=3.3V , IL=2A Rds-max=(3.3 - 1.5)/2= 0.9 Note that since the MOSFETs Rds-on increases with temperature, this number must be divided by 1.5, inorder to find the Rds-on max at room temperature. The Motorola MTP3055VL has a maximum of 0.18 Rds-on at room temperature, which meets our requirement. To select the heatsink for the LDO Mosfet the first step is to calculate the maximum power dissipation of the device and then follow the same procedure as for the switcher. Pd = ( Vin - Vo ) * IL Where : Pd = Power Dissipation of the Linear Regulator IL = Linear Regulator Load Current
1.5V and 2.5V Supply Resistor Divider Selection
Since the internal voltage reference for the linear regula­tors is set at 1.26V for US3018, there is a need to use external resistor dividers to step up the voltage. The re­sistor dividers are selected using the following equations: Vo=(1+Rt/Rb)*Vref Where: Rt=Top resistor divider Rb=Bottom resistor divider Vref=1.26V typical For 1.5V supply : Assuming Rb=100 Rt=Rb*[(Vo/Vref) - 1] Rt=100*[(1.5/1.26) - 1]=19.1 For 2.5V supply : Assuming Rb=200 Rt=Rb*[(Vo/Vref) - 1] Rt=200*[(2.5/1.26) - 1]=197 Select Rt=200
Switcher Output Voltage Adjust
As it was discussed earlier,the trace resistance from the output of the switching regulator to the Slot 1 can be used to the circuit advantage and possibly reduce the number of output capacitors, by level shifting the DC
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US3018
regulation point when transitioninig from light load to full load and vice versa. To account for the DC drop, the output of the regulator is typically set about half the DC drop that results from light load to full load. For example, if the total resistance from the output capacitors to the Slot 1 and back to the GND pin of the 3018 is 5m and if the total I, the change from light load to full load is 14A, then the output voltage measured at the top of the resistor divider which is also connected to the output capacitors in this case, must be set at half of the 70 mV or 35mV higher than the DAC voltage setting. To do this, the top resistor of the resistor divider(R17 in the applica­tion circuit) is set at 100, and the R19 is calculated. For example, if DAC voltage setting is for 2.8V and the desired output under light load is 2.835V, then R19 is calculated using the following formula : R19= 100*{Vdac /(Vo - 1.004*Vdac)} [Ω] R19= 100*{2.8 /(2.835 - 1.004*2.800)} = 11.76 k Select 11.8 k , 1%
Note: The value of the top resistor must not exceed 100. The bottom resistor can then be adjusted to raise
the output voltage.
Soft Start Capacitor Selection
The soft start capacitor must be selected such that dur­ing the start up when the output capacitors are charging
limit treshold. A minimum of 1uF capacitor insures this for most applications. An internal resistor charges the soft start capacitor which slowly ramps up the inverting
cap thereby limiting the input current. For example, with 1uF of soft start capacitor, the ramp up rate is approxi­mated to be 1V/20mS. For example if the output ca­pacitance is 9000uF, the maximum start up current will be: I=9000uF*(1V/20mS)=0.45A The other function of the soft start cap is to provide an off time between the current limit cycles(HICCUP) in order for the synchronous MOSFET to cool off and survive the short circuit condition. The off time between the current limit cycles is appoximated as: T(hicup)=60*Css (mS)
Input Filter
It is highly recommended to place an inductor between the system 5V supply and the input capacitors of the switching regulator to isolate the 5V supply from the switching noise that occurs during the turn on and off of the switching components. Typically an inductor in the range of 1 to 3 uH will be sufficient in this type of appli­cation.
External Shutdown
The best way to shutdown the US3018 is to pull down on the soft start pin using an external small signal tran­sistor such as 2N3904 or 2N7002 small signal MOSFET. This allows slow ramp up of the output, the same as the power up.
Layout Considerations
Switching regulators require careful attention to the lay­out of the components, specifically power components since they switch large currents. These switching com­ponents can create large amount of voltage spikes and high frequency harmonics if some of the critical compo­nents are far away from each other and are connected with inductive traces. The following is a guideline of how to place the critical components and the connections between them in order to minimize the above issues. Start the layout by first placing the power components:
1) Place the input capacitor C14 and the high side mosfet, Q3 as close to each other as possible.
2) Place the synchronous mosfet,Q4 and the Q3 as close to each other as possible with the intention that the source of Q3 and drain of the Q4 has the shortest length.
3) Place the snubber R15 & C13 between Q4 & Q3.
4) Place the output inductor ,L3 and the output capaci­tors ,C16 between the mosfet and the load with output capacitors distributed along the slot 1 and close to it.
5) Place the bypass capacitors, C8 and C19 right next to 12V and 5V pins. C8 next to the 12V, pin 1 and C19 next to the 5V, pin 8.
6) Place the US3018 such that the pwm output drives, pins 24 and 22 are relatively short distance from gates of Q3 and Q4.
7) Place all resistor dividers close to their respective feedback pins.
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8) Place the 2.5V output capacitor, C18 close to the pin13 of the IC and the 1.5V output capacitor, C17 close to the Q2 MOSFET. Note: It is better to place the
1.5V linear regulator components close to the 3018 and then run a trace from the output of the regulator to the load. However, if this is not possible then the trace from the linear drive output pin, pin 16 must be run away
from any high frequency data signals. It is critical, to place high frequency ceramic ca­pacitors close to the clock chip and termination resistors to provide local bypassing.
9) Place R12 and C10 close to pin 20.
10) Place C9 close to pin 9. Component connections:
Note : It is extremely important that no data bus should be passing through the switching regulator section specifically close to the fast transition nodes such as PWM drives or the inductor voltage.
Using the 4 layer board, dedicate on layer to GND, an­other layer as the power layer for the 5V, 3.3V, Vcore,
1.5V and if it is possible for the 2.5V.
Connect all grounds to the ground plane using di­rect vias to the ground plane.
Use large low inductance/low impedance plane to con­nect the following connections either using component side or the solder side. a) C14 to Q3 Drain b) Q3 Source to Q4 Drain c) Q4 drain to L3 d) L3 to the output capacitors, C16 e) C16 to the load, slot 1 f) Input filter L1 to the C16 and C3 g) C1 to Q2 drain h) C17 to the Q2 source I) A minimum of 0.2 inch width trace from the C18 ca­pacitor to pin 13 Connect the rest of the components using the shortest connection possible
US3018
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US3018
TYPICAL APPLICATIONTYPICAL APPLICATION
(Dual Layout with HIP6016)
12V
L1
5V
C2 C3
*
Q5
To ATX S.D.
*
* The components with
Asterisks can be eliminated If Fault pin is not used.
3.3V C1
R20
C14C10R12C8
1
R11
*
R22
*
R21
V12
V5
8 23
(Fault)
C19
Fault/Rt (Rt)
Vin2
12
U1
20
OCSet1
UGate1 24
Phase1
LGate1
PGnd
Vsen1
Fb1
En
(Comp1)
R13
R14
22
2110 19 18
17
C11
C12
Q3
Q4
R18
C13
R15 R16
R17
C15
R19
L3
Vout1
C16
1.8V - 3.5V
PGood
Vout3
1.5V
Vout2
2.5V
PGood 7
Q2
R5
C17
C18
R6
R7
R8
15
13
3018app2-1.3
Gate3
Fb3
Vout2
Fb2 Gnd
1411
C20 C9
SS
VID0 VID1 VID2 VID3 VID4
9
616 5 4 3 2
5V
Figure 3 - Typical application of US3018 in a dual layout with HIP6016 for an on board DC-DC converter providing
power for the Vcore , GTL+ & Clock supply for the Deschutes and the next generation processor applications.
Components that need to be modified to make the dual layout work for US3018 and HIP6016.
Part # R5,R7,R11,R21 R6,R8,R16,R18,C11,C12,C20 R22 C9,C19 C15 HIP6016 O V S O V US3018 S O O V S
S - Short O - Open V - See Unisem or Harris parts list for the value.
Table 2 - Dual layout component table
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US3018
US3018 Application Parts List Dual Layout with HIP6016
Ref Desig Description Qty Part # Manuf Q3,4 MOSFET 2 IRL3103
IRL3103S (Note 1) IR Q5 MOSFET, GP 1 2N7002 MOT Q2 MOSFET 1 MTP3055VL, TO263 package MOT L1 Inductor 1 L=1 uH L3 Inductor 1 Core :L=2 uH R=2 mohm Micro Metal C16 Capacitor ,Electrolytic 6 6MV1500GX ,1500uF,6.3V, Sanyo C14 Capacitor ,Electrolytic 2 6MV1500GX ,1500uF,6.3V, Sanyo C3 Capacitor ,Electrolytic 1 6MV1500GX ,1500uF,6.3V, Sanyo C18 Capacitor ,Electrolytic 1 220uF , 6.3V, ECAOJFQ221 Panasonic C17,C1 Capacitor ,Electrolytic 2 680uF,10V, EEUFA1A681L Panasonic C2 Capacitor ,Electrolytic 1 680uF,10V, EEUFA1A681L Panasonic C8,19 Capacitor , Ceramic 2 0805Z105P250NT Novacap
1uF,25V,Z5U,0805 smt C9 Capacitor , Ceramic 1 0805Z105P250NT Novacap
1uF,25V,Z5U,0805 smt
See Table 2, dual layout component C10 Capacitor , Ceramic 1 220pF, SMT 0805 size C13 Capacitor , Ceramic 1 470pF, SMT 0805 size C9,11, See Table 2, dual layout component 12,15,20 R12 Resistor 1 2.21k ,1%, SMT 0805 size R13,14 Resistor 2 10, 5%, SMT 1206 size R15 Resistor 1 10, 5%, SMT 1206 size R20 Resistor 1 10k, 5%, SMT 0805 size R6 Resistor 1 100, 1%, SMT 0805 size R8 Resistor 1 200, 1%, SMT 0805 size R5 Resistor 1 19.1, 1%, SMT 0805 size R7 Resistor 1 200, 1%, SMT 0805 size R17 Resistor 1 100, 1%, SMT 0805 size R19 Resistor 1 10k, 1%, SMT 0805 size R11 See Table 2, dual layout component 16,18, 21,22 HS3,4 Q1,3,4 Heatsink 2 6270 Thermalloy
Note 1 : For the applications where it is desirable not to use the Heatsink, the IRL3103S MOSFET in the TO263 SMT package with 1 square of pad area using top and bottom layers of the board as a minimum is required.
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