Datasheet UPD16680P, UPD16680W Datasheet (NEC)

DATA SHEET

MOS INTEGRATED CIRCUIT

µµµµ

PD16680

1/53, 1/40 DUTY, LCD CONTROLLER/DRIVER WITH BUILT-IN RAM

DESCRIPTION

The µPD16680 is a driver which contains a RAM capable of full - dot LCD display. The single µPD16680 IC chip can
operate a full - dot (up to 100 by 51 dots) LCD and pictographs (100 pictographs).

PD16680 can operate on single 3 V-power supply, is suitable for graphic pagers and cellular.

The

µ

FEATURES

LCD driver with a built-in display RAM

•

Can operate on single 3 V-power supply

•

Booster circuit incorporated : Switchable 3 or 4 folds

•

Dot display RAM : 100 x 51 bits

•

Pictographic display RAM : 100 bits

•

Pictographic display's duty changeable : 1/53 or 1/40 duty

•

Output for full-dot : 100 segments and 52 commons

•

Data input based on serial & 4-bit / 8-bit parallel switch over

•

String resister to output bias level incorporated

•

Selectable LCD driving bias level (select from 1/8 bias, 1/7 bias, 1/6 bias)

•

Oscillation circuit incorporated

•

D/A converter incorporated (for LCD driving voltage adjustment)

•

ORDERING INFORMATION

Part number Package
PD16680W/P Wafer/Chip(Matched COG mounting)

µ

Remark

Document No. S12694EJ2V0DS00(2nd edition)
Date Published July 1999 NS CP(K)
Printed in Japan

Purchasing the above products in term of chips per requires an exchange of other documents as well,
including a memorandum on the product quality. Therefore those who are interested in this regard are
advised to contact an NEC salesperson for further details.

The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.

Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.

The mark

••••

shows major revised points.

©

1997, 1999

1. BLOCK DIAGRAM

100

µµµµ

PD16680

SEG

1

SEG

PCOM

51

COM

0

COM

LC5

V

LC4

100

Segment Driver

100

100-bit latch

100 bits

100 x 51 bits

Pictograph Data RAM

Display Data RAM

100 bits

Blink Data RAM

LCD Voltage Generator

Common Driver

53-bit Register

V

LCBS3

V

LCBS2

V

LCBS1

V

LC3

V

LC2

V

LC1

V

CHA

AMP

Blink Controller

OUT

AMP

Remark

2

DD

SS

V

V

/xxx indicates act ive low signals.

Address Decoder

Data

Register

I/O

Buffer

6

D
to

(NS)

(DATA)

1

7

WS

0

STB

E(SCK)

D

D

D

Data Sheet S12694EJ2V0DS00

Command Decoder

OUT

/RESET

TEST

Timing Generator

Oscillator

circuit

OUT

BRI

OSC

OSCINOSC

D/A Converter

CHA

DA

IN(-)

OP Amp

AMP

IN(+)

AMP

LCD

V

DC/DC

Converter

−

−

−

3

1

2

, C

, C

, C

+

+

+

1

3

2

EXT

V

C

C

C

2. PIN CONFIGURATION (Top view)

Chip Size : 12.5 mm x 1.89 mm

µµµµ

PD16680

250

264

249

115

Y

X

1

114

100

99

Data Sheet S12694EJ2V0DS00

3

Table 2-1. Pad Layout (1/2)

µµµµ

PD16680

Pin No. Pin Name

X(

m) Y(µm)

µ

1 Dummy –5883.2 –811.0 67 C
2 Dummy –5763.2 –811.0 68 C
3 Dummy –5643.2 –811.0 69 C
4V
5V

LCBS1
LCBS1

–5523.2 –811.0 70 C

–5403.2 –811.0 71 C
6 Dummy –5283.2 –811.0 72 C
7V
8V

LCBS2
LCBS2

–5163.2 –811.0 73 V

–5043.2 –811.0 74 V
9 Dummy –4923.2 –811.0 75 V

10 V
11 V

LCBS3
LCBS3

–4803.2 –811.0 76 Dummy 3116.8 –811.0

–4683.2 –811.0 77 V

12 Dummy –4563.2 –811.0 78 DA
13 AMP
14 AMP

OUT
OUT

–4443.2 –811.0 79 AMP

–4323.2 –811.0 80 OSC

15 Dummy –4203.2 –811.0 81 OSC
16 AMP
17 AMP

IN(-)
IN(-)

–4083.2 –811.0 82 V

–3963.2 –811.0 83 OSC

Pin No. Pin Name

3
3
3
3
3
3
DD
DD
DD

EXT

DD

+
+
+
–
–
–

CHA

CHA
IN
OUT

BRI

X(µm) Y(µm)

2036.8 –811.0

2156.8 –811.0

2276.8 –811.0

2396.8 –811.0

2516.8 –811.0

2636.8 –811.0

2756.8 –811.0

2876.8 –811.0

2996.8 –811.0

3236.8 –811.0

3356.8 –811.0

3476.8 –811.0

3596.8 –811.0

3716.8 –811.0

3836.8 –811.0

3956.8 –811.0
18 Dummy –3843.2 –811.0 84 D0(DATA) 4076.8 –811.0
19 AMP
20 AMP

IN(+)
IN(+)

–3723.2 –811.0 85 D

–3603.2 –811.0 86 D
21 Dummy –3483.2 –811.0 87 D
22 V
23 V

DD
DD

–3363.2 –811.0 88 D

–3243.2 –811.0 89 D
24 Dummy –3123.2 –811.0 90 D
25 V
26 V
27 V

LC5
LC5
LC5

–3003.2 –811.0 91 D7(NS) 4916.8 –811.0

–2883.2 –811.0 92 WS 5036.8 –811.0

–2763.2 –811.0 93 STB 5156.8 –811.0

1
2
3
4
5
6

4196.8 –811.0

4316.8 –811.0

4436.8 –811.0

4556.8 –811.0

4676.8 –811.0

4796.8 –811.0

28 Dummy –2643.2 –811.0 94 E(SCK) 5276.8 –811.0
29 V
30 V
31 V

LC4
LC4
LC4

–2523.2 –811.0 95 /RESET 5396.8 –811.0

–2403.2 –811.0 96 V

–2283.2 –811.0 97 TEST

DD

5516.8 –811.0

OUT

5636.8 –811.0
32 Dummy –2163.2 –811.0 98 Dummy 5756.8 –811.0
33 V
34 V
35 V
36 Dummy –1683.2 –811.0 102 COM
37 V
38 V
39 V
40 Dummy –1203.2 –811.0 106 COM
41 V
42 V
43 V
44 Dummy –723.2 –811.0 110 COM
45 V
46 V
47 V
48 V
49 V
50 V
51 V
52 V
53 V
54 Dummy 476.8 –811.0 120 COM
55 C
56 C
57 C
58 C
59 C
60 C
61 C
62 C
63 C
64 C
65 C
66 C

LC3
LC3
LC3

LC2
LC2
LC2

LC1
LC1
LC1

LCD
LCD
LCD
DD
DD
DD
SS
SS
SS

1
1
1
1
1
1
2
2
2
2
2
2

–2043.2 –811.0 99 Dummy 5876.8 –811.0
–1923.2 –811.0 100 Dummy 6112.0 –682.2
–1803.2 –811.0 101 Dummy 6112.0 –592.2

–1563.2 –811.0 103 COM
–1443.2 –811.0 104 COM
–1323.2 –811.0 105 COM

–1083.2 –811.0 107 COM
–963.2 –811.0 108 COM
–843.2 –811.0 109 COM

–603.2 –811.0 111 COM
–483.2 –811.0 112 COM

27
28
29
30
31
32
33
34
35
36
37

6112.0 –502.2

6112.0 –412.2

6112.0 –322.2

6112.0 –232.2

6112.0 –142.2

6112.0 –52.2

6112.0 37.8

6112.0 127.8

6112.0 217.8

6112.0 307.8

6112.0 397.8

–363.2 –811.0 113 Dummy 6112.0 487.8
–243.2 –811.0 114 Dummy 6112.0 577.8
–123.2 –811.0 115 Dummy 6030.0 817.8
–3.2 –811.0 116 Dummy 5940.0 817.8

100

38
39
40
41
42
43
44
45
46
47
48
49
50
51

5850.0 817.8

5760.0 817.8

5670.0 817.8

5580.0 817.8

5490.0 817.8

5400.0 817.8

5310.0 817.8

5220.0 817.8

5130.0 817.8

5040.0 817.8

4950.0 817.8

4860.0 817.8

4770.0 817.8

4680.0 817.8

4500.0 817.8

116.8 –811.0 117 COM

236.8 –811.0 118 COM

356.8 –811.0 119 COM

+
+
+
–
–
–
+
+
+
–
–
–

596.8 –811.0 121 COM

716.8 –811.0 122 COM

836.8 –811.0 123 COM

956.8 –811.0 124 COM

1076.8 –811.0 125 COM

1196.8 –811.0 126 COM

1316.8 –811.0 127 COM

1436.8 –811.0 128 COM

1556.8 –811.0 129 COM

1676.8 –811.0 130 COM

1796.8 –811.0 131 PCOM 4590.0 817.8

1916.8 –811.0 132 SEG

4

Data Sheet S12694EJ2V0DS00

Table 2-1. Pad Layout (2/2)

µµµµ

PD16680

Pin No. Pin Name

133 SEG
134 SEG
135 SEG
136 SEG
137 SEG
138 SEG
139 SEG
140 SEG
141 SEG
142 SEG
143 SEG
144 SEG
145 SEG
146 SEG
147 SEG
148 SEG
149 SEG
150 SEG
151 SEG
152 SEG
153 SEG
154 SEG
155 SEG
156 SEG
157 SEG
158 SEG
159 SEG
160 SEG
161 SEG
162 SEG
163 SEG
164 SEG
165 SEG
166 SEG
167 SEG
168 SEG
169 SEG
170 SEG
171 SEG
172 SEG
173 SEG
174 SEG
175 SEG
176 SEG
177 SEG
178 SEG
179 SEG
180 SEG
181 SEG
182 SEG
183 SEG
184 SEG
185 SEG
186 SEG
187 SEG
188 SEG
189 SEG
190 SEG
191 SEG
192 SEG
193 SEG
194 SEG
195 SEG
196 SEG
197 SEG
198 SEG

99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34

X(

m) Y(µm)

µ

4410.0 817.8 199 SEG

4320.0 817.8 200 SEG

4230.0 817.8 201 SEG

4140.0 817.8 202 SEG

4050.0 817.8 203 SEG

3960.0 817.8 204 SEG

3870.0 817.8 205 SEG

3780.0 817.8 206 SEG

3690.0 817.8 207 SEG

3600.0 817.8 208 SEG

3510.0 817.8 209 SEG

3420.0 817.8 210 SEG

3330.0 817.8 211 SEG

3240.0 817.8 212 SEG

3150.0 817.8 213 SEG

3060.0 817.8 214 SEG

2970.0 817.8 215 SEG

2880.0 817.8 216 SEG

2790.0 817.8 217 SEG

2700.0 817.8 218 SEG

2610.0 817.8 219 SEG

2520.0 817.8 220 SEG

2430.0 817.8 221 SEG

2340.0 817.8 222 SEG

2250.0 817.8 223 SEG

2160.0 817.8 224 SEG

2070.0 817.8 225 SEG

1980.0 817.8 226 SEG

1890.0 817.8 227 SEG

1800.0 817.8 228 SEG

1710.0 817.8 229 SEG

1620.0 817.8 230 SEG

1530.0 817.8 231 SEG

1440.0 817.8 232 COM

1350.0 817.8 233 COM

1260.0 817.8 234 COM

1170.0 817.8 235 COM

1080.0 817.8 236 COM

990.0 817.8 237 COM

900.0 817.8 238 COM

810.0 817.8 239 COM

720.0 817.8 240 COM

630.0 817.8 241 COM

540.0 817.8 242 COM

450.0 817.8 243 COM

360.0 817.8 244 COM

270.0 817.8 245 COM

180.0 817.8 246 COM

90.0 817.8 247 COM

Pin No. Pin Name

33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11

X(µm) Y(µm)
–1530.0 817.8
–1620.0 817.8
–1710.0 817.8
–1800.0 817.8
–1890.0 817.8
–1980.0 817.8
–2070.0 817.8
–2160.0 817.8
–2250.0 817.8
–2340.0 817.8
–2430.0 817.8
–2520.0 817.8
–2610.0 817.8
–2700.0 817.8
–2790.0 817.8
–2880.0 817.8
–2970.0 817.8
–3060.0 817.8
–3150.0 817.8
–3240.0 817.8
–3330.0 817.8
–3420.0 817.8
–3510.0 817.8
–3600.0 817.8
–3690.0 817.8
–3780.0 817.8
–3870.0 817.8
–3960.0 817.8
–4050.0 817.8
–4140.0 817.8
–4230.0 817.8
–4320.0 817.8
–4410.0 817.8
–4500.0 817.8
–4590.0 817.8
–4680.0 817.8
–4770.0 817.8
–4860.0 817.8
–4950.0 817.8
–5040.0 817.8
–5130.0 817.8
–5220.0 817.8
–5310.0 817.8
–5400.0 817.8
–5490.0 817.8
–5580.0 817.8
–5670.0 817.8
–5760.0 817.8
–5850.0 817.8

0.0 817.8 248 Dummy –5940.0 817.8
–90.0 817.8 249 Dummy –6030.0 817.8
–180.0 817.8 250 Dummy –6112.0 577.8
–270.0 817.8 251 Dummy –6112.0 487.8
–360.0 817.8 252 COM
–450.0 817.8 253 COM
–540.0 817.8 254 COM
–630.0 817.8 255 COM
–720.0 817.8 256 COM
–810.0 817.8 257 COM
–900.0 817.8 258 COM
–990.0 817.8 259 COM
–1080.0 817.8 260 COM
–1170.0 817.8 261 COM

10
9
8
7
6
5
4
3
2
1

–6112.0 397.8
–6112.0 307.8
–6112.0 217.8
–6112.0 127.8
–6112.0 37.8
–6112.0 -52.2
–6112.0 -142.2
–6112.0 -232.2
–6112.0 -322.2
–6112.0 -412.2

–1260.0 817.8 262 PCOM –6112.0 -502.2
–1350.0 817.8 263 Dummy –6112.0 -592.2
–1440.0 817.8 264 Dummy –6112.0 -682.2

Data Sheet S12694EJ2V0DS00

5

3. PIN DESCRIPTIONS

3.1 Power System Pins

Pin Symbol Pin Name Pin No. I/O Function Description

DD

V

SS

V

LCD

V

★

V

V
V
C
C
C

LC1

to V

LCBS1

LCBS3

+

, C

1

+

, C

2

+

, C

3

LC5

to

–

1

–

2

–

3

µµµµ

PD16680

Logic and booster power
supply pin

22, 23,

48 to 50,

- Power supply pin for logic and booster ci rcuit.

73 to 75,

82, 96

Logic and driver ground

51 to 53 - Ground pin for logic and driver circuit .
pin
Driver power supply pin 45 to 47 - Driver power supply pin. Output pin of i nternal booster circuit.

Please connect with a 1

F booster capacitor to ground.

µ

When not using the i nternal booster circuit, the driver power

can be turned on directly.
Driver reference power
supply

25 to 27,
29 to 31,
33 to 35,
37 to 39,

- Reference power supply pin for LCD drive.
When the internal bi as i s selected, be sure to leave it open.
When display contrast is bad, connect a capacitor between
these pins and ground.

41 to 43

Bias level select pin 4, 5, 7,

8, 10, 11

- When the internal bias is selected, Connecting these pins
outside the IC, the bias l evel can be changed.

Capacitor connection pins 55 to 72 - Capacitor connection pins for booster circuit. When using

internal booster circuit, connect a 1

F capacitor between

µ

these pins.

6

Data Sheet S12694EJ2V0DS00

µµµµ

PD16680

3.2 Logic System Pins (1/2)

Pin Symbol Pin Name Pin No. I/O Function Description

WS Word length select pin

(Word Select )

CHA

DA

D/A converter select pi n 78 I This pin sel ec ts whether to use the internal D/A c onverter for

STB Strobe 93 I This pin is select signal of device, strobe signal for data

E(SCK) Enable(shift clock) 94 I When using paral l el i nt erface mode, this pin becomes the

D0(DATA) Data-bus(data) 84 I/ O When using parallel interface m ode, this pin becomes t he D

3

D1 to D

D4 to D

6

Data-bus 85 to 87 I/O W hen using parallel interface mode, these pin becom es the

Data-bus 88 to 90 I /O When using parallel interfac e mode, thes e pin become t he D

D7(NS) Data-bus(nibble select) 91 I/ O When word select (WS) is High level, this pin becomes the D

OUT

TEST

TEST signal output 97 O When to do test , this pin is output for test signal.

/RESET Reset 95 I

92 I This pin selects the word length.

At High level, it become an 8-bit parallel interface.
At Low level, when D

7

(NS) is High level, it become a serial
interface.
When the word length is 4 bits, data is transferred in the
upper-to-low sequence by mean of data buss es D
The word length cannot be changed after power-on.

LCD driving voltage adjustment or not .
At High level, D/A c onverter is used. At Low level, unused.

transfer. Data transfer is initialized at falling/rising edge of
STB.
Data can be input/output at Low level either in parallel
interface or serial interf ace mode.
When STB is Hi gh l evel , Enable/shift clock is bypassed.

data enable input. In reading-in, dat a i s fetched into the
interface buffer at ris i ng edge. In reading-out, data is fetched
from interface buff er at falling edge.
When using serial i nterface mode, this pin becom es the data
shit clock.
In reading-in, data is fetc hed into the interfac e buffer at rising
edge.
In reading-out, data is fetched from interface buffer at falling
edge.

bit of data-bus.
When using serial interface mode, this pin becomes the
input/output pin of the c ommand and display data (3 states).

1

D

to D3 bits of data-bus. W hen using serial interface m ode,

keep them H or L.

to D6 bits of data-bus. When using serial interf ace mode, keep
them H or L.

bit of data-bus.
When word select (WS) is Low level, This pin becomes nibble
select pin. At High l evel , selected 4-bit parallel interface.
At Low level, selected serial i nterface.

When using in normal operation, this pin leave open.
At Low level, the

PD16680 is initialized.

µ

0

to D3.

0

4

7

Data Sheet S12694EJ2V0DS00

7

3.2 Logic System Pins (2/2)

Pin Symbol Pin Name Pin No. I/O Function Description

CHA

AMP

EXT

V

OSC

OSC

OSC

IN

OUT

BRI

Amp mode select pin 79 I Select operational amplifier mode.

At High level, “Level capac i tor mode”.
At Low level, “LCD driving mode”.

LCD reference supply
switching

77 I Select the m ethod for supplying LCD power circuit. At High

level, LCD driving voltage is suppli ed external circuit. At Low
level, it is supplied internal circuit.

Oscillation pin

80 I

These pins are connected with the 1 MΩ resistor. W hen us ing
external oscillation, input into the OSC

OUT

OSC

81 O

open.

Blinking Clock 83 I This pin is oscillation input for Blink ing. To input 2 Hz external

clock, when to use Blink i ng by external c l ock mode.
When not to use t hi s pin, keep it H or L.

µµµµ

PD16680

IN

, and leaving the

8

Data Sheet S12694EJ2V0DS00

3.3 Driver System Pins

Pin Symbol Pin Name Pin No. I/O Function Description

SEG1 to

100

SEG
COM1 to

51

COM

PCOM Pictographic common 131, 262 O Common output pins for pictograph.

AMPIN(+) 19, 20

AMPIN(-)

OUT

AMP

Dummy Dummy pad 1, 2, 3, 9, 12,

Segment 132 to 231 O Segment output pins.

Common 102 to 112,

O Common output pins
117 to 130,
232 to 247,
252 to 261

(Same waveform output from these pins.)

Operational amplifier input

I These pins are the input pins of operat ional amplif ier for LCD

driving voltage adjustment .
When using the int ernal D/A converter, leave AMP
When not using the i nternal D/A converter, it is necessary to

16,17

input the reference voltage.

IN(–)

AMP

is connected to the resist er for LCD driving voltage
adjustment.
See

4. LCD DRIVING VOLTAGE CONTROL CIRCUIT

Operational amplifier
output

13,14 O This is the input pin of operati onal amplifier for LCD driving

voltage adjustment. Normally it is connected to the res i ster for
LCD driving voltage adjustment . See

VOLTAGE CONTROL CIRCUIT

this pin a 0.1 to 1

µ

internal operational amplif i er be stable.

- Dumm y pins are not connected to the internal circuit. Leave

15, 18, 21,

open if they are not used.

24, 28, 32,
33, 40, 44,
54, 76,
98 to 101,
113 to 116,
248 to 251,
263, 264

. It recomm ends to connect to

F capacitor to make the output of the

µµµµ

IN(+)

4. LCD DRIVING

PD16680

open.

.

4. LCD DRIVING VOLTAGE CONTROL CIRCUIT

CHA

AMP

DA

IN(+)

AMP

IN(−)

R

1

D/A
Converter

+

−

AMP

R

2

outVLC1

C

1

V

LC2VLC3

Data Sheet S12694EJ2V0DS00

Reference power circuit

V

LCBS1

V

LCBS3

V

LCBS2

V

LC4VLC5

V

EXT

V

SS

9

µµµµ

PD16680

5. POWER CIRCUIT

The

PD16680 incorporate the booster circuit is switchable between 3 and 4 folds. The boosting magnitude of

µ

internal booster circuit is selected by the capacitor connection.

The reference power circuit is switchable between internal driving circuit and external driving circuit. The method

EXT

for supplying the reference circuit selected by V

5.1 Booster circuit

pin (H : External, L : Internal ).

Using Internal driving circuit, to connect condenser for boosting between C

LCD

connect condenser between V
booster circuit boost voltage between V

and VDD to be stable boosting voltage. And to set V

DD

and VSS to 3 or 4 folds.

+

and C

1

–

+

, C

1

2

EXT

pin to low level, internal

and C

–

+

, C

2

3

and C

The booster circuit is using clock made by internal oscillation circuit. It is necessary that oscillation to be operated.

+

–

+

–

+

–

, C

,C

,C

C

1

1

,C

2

2

3

,C

DD

, V

are pins for booster circuit. To use the wire that have low register value to connect

3

these pins.

Figure 5-1 3x and 4x Booster Circuits

V

LCD = 4VDD = 12 V

(4-fold boost)

V

LCD = 3VDD = 9 V

(3-fold boost)

VDD = 3 V

SS = 0 V

V

Remarks 1.

When to use 3-fold booster circuit, not to connect condenser between C
open C

2.

When to use external power supply circuit, booster circuit is not operating.

+

2

and C

–

.

3

+

3

and C

–

+

, C

2

1

and C

–

, leave

1

3

–

, to

10

Data Sheet S12694EJ2V0DS00

5.2 LCD driving circuit

µµµµ

PD16680

5.2.1 To use internal driving circuit, not to use D/A converter ( V

EXT

= L , DA

CHA

= L )

When to internal driving circuit is chosen, boosted voltage be used for power of internal operational amplifier

adjusting LCD driving voltage. To connect external resister R

LC1

possible to adjust LCD driving voltage of V

. If using thermistor to adjust LCD driving voltage according to the

1

, R2, and input reference voltage to AMP

temperature characteristic of LCD panel, we recommend connecting it with R

LC1

The value of V

can be computed by the following formula.

2

in parallel.

(+)

IN

Equation 5-1

R

2

V

= AMPIN(+) = (1+ ) V

LC1

Remark

2

R

R2 x R

=

′

R2 + R

′

R

th

th

REF

1

Figure 5-2 When not using Internal power supply select or D/A converter

DA

CHA

D/A
Converter

V

REF

to Internal driving circuit

pin. It is

AMP

AMP

IN(+)

R

IN(-)

1

+

−

R

R

AMP

th

2

out

V

LC1

1

C

Data Sheet S12694EJ2V0DS00

11

µµµµ

PD16680

5.2.2 To use internal driving circuit and D/A converter ( V

To use D/A converter, it is possible to adjust reference voltage V
command.
To set 6-bit data to D/A converter register, reference voltage V
The formula of V

LC1

is as same written in

Equation 5-1

.

Figure 5-3 Using internal power supply select and D/A converter

V

DD

D/A
Converter

V

REF

+

−

AMP

out

AMP

Open

DA

IN(+)

AMP

CHA

IN(-)

= L , DA

EXT

REF

inputted to AMP

REF

is choose one level from 64 level in 1/2 VDD to VDD.

V

DD

CHA

= H )

(+)

pin for LCD driving by

IN

to Internal driving circuit

V

LC1

R

th

R

2

R

1

C

1

.

5.2.3 To use external driving circuit ( V

EXT

= H )

When external voltage supply circuit for LCD driving is chosen, operational amplifier incorporated IC is off.
Therefore, it is impossible to use operational amplifier for LCD driving and D/A converter function. LCD driving
voltage is adjust by the voltage inputted to V

LCD

Remarks 1.

Set V

2.

DA

3.

Set AMP

CHA ,

LC1.

V

≥

IN

AMP

pin "open".

OUT

(+)

, AMP

(-)

IN

are CMOS input. Set H level or L level.

LCD

and V

LC1

pins directly.

12

Data Sheet S12694EJ2V0DS00

5.3 REFERENCE VOLTAGE CIRCUIT

µµµµ

PD16680

5.3.1 To use internal reference voltage circuit ( V

When internal driving circuit is chosen, 6 levels for LCD reference voltage (V

EXT

= L )

LC1

, V

LC2

, V

LC3

, V

LC4

, V

, VSS) is

LC5

generate by internal breeder resister.

5.3.2 To use external driving circuit ( V

EXT

= H )

When external driving circuit is chosen, operational amplifier incorporated IC is Off. It is necessary to input voltage
to V

, V

, V

, V

LC1

LC2

LC3

LC4

and V

directly.

LC5

Generally, These levels are made by external breeder resister. The display dignity of LCD declines when these
resistance values are big, it is necessary to choose the resistance value which corresponds with the LCD panel.

There is an effect that improves display dignity when connecting a capacitor with each level pins and the ground. It is
necessary to choose the condenser value which corresponds with the LCD panel.

★

Figure 5-3. Reference voltage circuit

AMP

OUT

V

LC1

V

LC2

+

−

R

+

−

R

to SEG, COM Outputs

to COM Output

V

V

V

V

LC3

LCBS1

LCBS2

LCBS3

V

LC4

V

LC5

V

SS

+

−

R

R

R

+

−

R

+

−

R

to SEG Output

Voltage follower for level voltage

to SEG Output

to COM Output

to SEG, COM Output

Data Sheet S12694EJ2V0DS00

13

5.4 Setting BIAS value

When internal driving circuit chosen, by connecting the interval of the pin V
bias value can be set from the 1/6 bias, the 1/7 bias, the 1/8 bias.

Bias value Pin connection

LCBS1

LCBS2

1/8 bias V

, V
1/7 bias To connect V
1/6 bias To connect V

, V

LCBS3

LCBS1

LCBS1

All open
and V
and V

LCBS2

LCBS3

, or V

LCBS2

, V

LCBS2

and V

is open.

LCBS3

5.5 Voltage followers for level power supply

LCBS1

, V

LCBS2

LCBS3

, V

outside the IC, the

µµµµ

PD16680

By the input of AMP

• LCD driving mode ( AMP
When this mode is chosen, The voltage follower maximizes electric current supply ability for LCD drive. It
doesn't need to connect the external capacitor for the level stability.

CHA

pin, it controls voltage follower for the LCD drive level power supply.

CHA

= L )

• Level capacitor mode ( AMP
When this mode is chosen, The voltage follower maximizes electric current supply ability for the external
condenser charging. In this mode, it needs to connect the external capacitor ( 0.1 to 1.0 µF ) for the level stability.

CHA

= H )

Caution When using this mode without connecting capacitor, the display dignity will be bad.

14

Data Sheet S12694EJ2V0DS00

5.6 Application circuit example

5.6.1 To use internal driving circuit, LCD driving mode

µµµµ

PD16680

A) Boost 4folds (not to use D/A converter)

V

DD

V

LCD

+

C

2

+

C

1

+

C

1

−

C

1

+

C

2

+

C

1

−

C

2

+

C

3

+

C

1

AMP

IN(+)

AMP

AMP

Note1

IN(−)

OUT

V

LC1

V

LC2

V

LC3

V

LC4

V

DD

Rth(Thermistor)

R2

+

Open

R1

B) Boost 3 folds

+

C

2

+

C

1

Open

C

1

+

V

DD

V

LCD

+

C

1

−

C

1

Note2

+

C

2

−

C

2

+

C

3

Notes 1.

Remark

−

C

3

V

EXT

V

SS

When to use D/A converter, AMP

+

–

2

2.

3

C

, C

are open.

C1 = C2 = 1.0

µ

m

AMP

IN(+)

V

LC5

CHA

is open.

Open

−

Note2

C

3

V

EXT

V

SS

Data Sheet S12694EJ2V0DS00

15

5.6.2 To use internal driving circuit, LCD driving mode

µµµµ

PD16680

A) Boost 4folds(not to use D/A converter)

V

DD

V

LCD

+

C

2

+

C

1

+

C

1

−

C

1

+

C

2

+

C

1

−

C

2

+

C

3

+

C

1

−

C

3

AMP

IN(+)

AMP

AMP

Note1

IN(−)

OUT

V

V

V

V

V

LC1

LC2

LC3

LC4

LC5

R2

+

V

DD

V

DD

Rth(Thermistor)

+

+

+

+

B) Boost 3 folds

V

DD

V

LCD

R1

+

C

C

C

+

2

+

1

Open

+

1

Open

+

C

1

−

C

1

Note2

+

2

C

−

C

2

+

C

3

−

Note2

C

3

Notes 1.

Remark

V

EXT

V

SS

When to use D/A converter, AMP

+

–

2

2.

3

, C

C

are open.

C1 = C2 = 1.0

µ

m

AMP

IN(+)

CHA

is open.

V

EXT

V

SS

16

Data Sheet S12694EJ2V0DS00

5.6.3 To use external driving circuit

V

DD

To use 1/6 bias

AMP

AMP

IN(+)

IN(−)

µµµµ

PD16680

Open

AMP

OUT

V

LCD

+

C

1

V

LC1

Open

External power supply

R

−

C

1

+

C

2

V

LC2

R

V

−

C

2

+

C

3

−

C

3

V

DD

V

EXT

LC3

2R

V

LC4

R

V

LC5

R

V

SS

Data Sheet S12694EJ2V0DS00

17

6. LCD DRIVING

The µPD16680 is able to choose duty 1/53 duty or 140 duty.

6.1 1/53 duty driving

µµµµ

PD16680

When 1/53 duty is chosen, the

1

outputs (COM

VLC1
VLC2
VLC3

SEG1

VLC4
VLC5

VSS

VLC1
VLC2
VLC3

COM1

VLC4
VLC5

VSS

to COM51), the pictograph part common outputs (PCOM).

12345678 51525312345678 515253

PD16680 outputs a choice signal once at 1 frame from the dot part common

µ

1 Frame

COM2

PCOM

18

VLC1
VLC2
VLC3

VLC4
VLC5

VSS

VLC1
VLC2
VLC3

VLC4
VLC5

VSS

Data Sheet S12694EJ2V0DS00

6.2 1/40 duty driving

µµµµ

PD16680

When 1/40 duty is chosen, the

1

to COM19, COM27 to COM45), the pictograph part common outputs (PCOM ).

(COM

12345678 38394012345678 383940

VLC1
VLC2
VLC3

SEG1

VLC4
VLC5

VSS

VLC1
VLC2
VLC3

COM1

VLC4
VLC5

VSS

PD16680 outputs a choice signal once at 1 frame from the dot part common outputs

µ

1 Frame

COM2

PCOM

VLC1
VLC2
VLC3

VLC4
VLC5

VSS

VLC1
VLC2
VLC3

VLC4
VLC5

VSS

Data Sheet S12694EJ2V0DS00

19

7. LCD DISPLAY

The µPD16680 can display 100 by 51 dots (called full-dot display) LCD display and 100 pictographs.

Figure 7-1 LCD matrix

4

6

89101112131415161718

PCOM

COM
COM2
COM3
COM4
COM5
COM6
COM7
COM8

COM9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
COM17
COM18
COM19

123

1

5

7

8990919293949596979899

µµµµ

PD16680

100

COM47
COM48
COM49
COM50
COM51

20

Data Sheet S12694EJ2V0DS00

µµµµ

PD16680

8. GROUP ADDRESSES

8.1 Dot display

The group addresses of dot display are assigned as follows.
To be chosen the address is increment, when X address goes to 0CH, next address is 00H. At this time, Y address
goes to next address. When Y address goes to 33H, next address is 00H, too.

X address

02H

0BH 0CH

00H

01H

02H

Y address

03H

00H

01H

32H
33H

b7 b6 b5 b4 b7 b6 b5 b4b3 b2 b1 b0

Remark

★

When 1/53 duty and using 1/40 duty are used, the RAM addresses and the common pins used are as follows.

Note

Data of X address = 0CH : b7 to b4 are data, b3 to b0 are don't care.

Duty

1/53 duty 00H to 33H - COM1 to COM51 ­1/40 duty 00H to 12H

Use RAM

Y addresses

1AH to 2CH

Note

Don’t use RAM

Y addresses

13H to 19H

2DH to 33H

Use common pins Don’t use c ommon

COM1 to COM19

COM27 to COM45

If address incrementation is set when 1/40 duty is used, the X address value following 0CH is 00H. At the

X

COM20 to COM26
COM46 to COM51

same time the Y address is incremented by 1. The Y address value following 12H is 1AH, and the value
following 2CH is 00H.

X

pins

X

X

Data Sheet S12694EJ2V0DS00

21

8.2 Pictograph

The group addresses of pictograph are assigned as follows.
To be chosen the address is increment, X address goes to 0CH, next address is 00H.

X address

µµµµ

PD16680

00H

(PCOM)

Y address

00H 01H 02H 03H

b6

b5

b4

8 bits

b7

b3

b2 b1

b0

0BH 0CH

Table 8-1 PCOM (Y address = 00H)

X address

b7 b6 b5 b4 b3 b2 b1 b0
00H 12345678
01H 910111213141516
02H 17 18 19 20 21 22 23 24
03H 25 26 27 28 29 30 31 32
04H 33 34 35 36 37 38 39 40
05H 41 42 43 44 45 46 47 48

Segment output No.

Remark

06H 49 50 51 52 53 54 55 56
07H 57 58 59 60 61 62 63 64
08H 65 66 67 68 69 70 71 72
09H 73 74 75 76 77 78 79 80
0AH 8182838485868788
0BH 8990919293949596
0CH 979899100XXXX

Data of X address = 0CH :b7 to b4 are data, b3 to b0 are don’t care.

22

Data Sheet S12694EJ2V0DS00

8.3 Blink data

The group addresses of brink data are assigned as follows.
To be chosen the address is increment, when X address goes to 0CH, next address is 00H.

X address

µµµµ

PD16680

00H

(PCOM)

Y address

00H 01H 02H 03H

b5

b7

b6

b4

8 bits

b3

b2 b1

b0

0BH 0CH

Table 8-2 PCOM (Y address = 00H)

X address

b7 b6 b5 b4 b3 b2 b1 b0
00H 12345678
01H 910111213141516
02H 17 18 19 20 21 22 23 24
03H 25 26 27 28 29 30 31 32
04H 33 34 35 36 37 38 39 40
05H 41 42 43 44 45 46 47 48

Segment output No.

Remark

06H 49 50 51 52 53 54 55 56
07H 57 58 59 60 61 62 63 64
08H 65 66 67 68 69 70 71 72
09H 73 74 75 76 77 78 79 80
0AH 8182838485868788
0BH 8990919293949596
0CH 979899100XXXX

Data of X address = 0CH :b7 to b4 are data, b3 to b0 are don’t care.

Data Sheet S12694EJ2V0DS00

23

9. COMMAND

9.1 Basic form

Command Register (CR)

µµµµ

PD16680

Command Register (CR)

Address Register (CR)

Command Register (CR)

+

++

++

9.2 Command register

The command register’s basic configuration is as follows.

MSB

b7 b6 b5 b4 b3 b2 b1 b0

LSB

Table 7-1 Command Table

Extend Select Register (ESR)

X address (XAD) Y address (YAD)

Data 1 (DT1)

Choices

Command Type (0 x H to B x H)

.....

24

Command

Reset 00100111

Display ON/OFF
Standby
D/A converter setting
Duty setting
Blink setting
Data R/W mo de
Test mode

D7 D6 D5 D4 D3 D2 D1 D0

00001b2b1b0
00010b2b1b0
00101000
00011b3b2b0
01000b2b1b0
10110b2b1b0
10111b2b1b0

Data Sheet S12694EJ2V0DS00

Register

9.2.1 Reset

The all IC's commands are initialized.

µµµµ

PD16680

MSB

001

0

0

LSB

111

9.2.2 Display ON/OFF

ON/OFF of the display is controlled.

MSB

00001 b1b0b2

LSB

Choices
000 : LCD OFF (SEG
001 : LCD OFF (SEG
111 : LCD ON

n

, COMn, PCOMn = Vss)

n

, COMn, PCOMn = non-serective output)

9.2.3 Standby

The DC/DC converter is stopped, thus reducing the supply current. This display is placed in the OFF state (SEGn,
COMn = V

).

SS

Even at Standby, it is possible to write command and data.

MSB

000

Note

SEG

b2 b1 b0

0

1

n

, COMn, PCOM = V

LSB

Cohices
000 : Nomal operation

001 : Standby (DC/DC converter halt, all display OFF , OSC halt)

SS

Note

Data Sheet S12694EJ2V0DS00

25

9.2.4 D/A converter setting

The internal D/A converter is set. D/A converter output voltage is controlled from 1/2V

DD

to VDD.

µµµµ

PD16680

LSB

+

MSB

00

MSB

001

000

1

0

Caution After resetting, it is set to 20H.

9.2.5 Duty setting

The duty is set.

MSB

000

1

1

LSB

b2 b1 b0

Choices
000 : 1/53 duty
001 : 1/40 duty

LSB

b2 b1 b0

b3

b4b5

Extend Choices
D/A Converter output voltage
00H(MIN.) to 3FH(MAX.)

Note

Note

If the duty cycle is 1/40, leave open from COM

to COM51.

39

9.2.6 Blink setting

The blinks of the pictograph of the address whose blink data is “1” are controlled.

MSB

010

Note

0

0

This refers to the frequency of the external clock which is input from the OSC

LSB

b2 b1 b0

Choices
000 : Blink halt
001 : Blink start (Blink frequency = f
010 : Blink start (Blink frequency = f

OSC

/32768)

Note

BRI

/2)

BR1

pin.

26

Data Sheet S12694EJ2V0DS00

9.2.7 Data R/W mode

Data Read/Write (R/W), increment, address counter resetting, etc. are set in this mode.

DATA

MSB

LSB

MSB

LSB

µµµµ

PD16680

101

Notes 1.

2.

Remark

1

b2 b1 b0

0

++

Choices 1
00 : The address is incremented starting from the current one
01 : Current address retained

Choices 2
0 : Data writing
1 : Data reading

Note2

b2b3b4b5b6b7 b1 b0

When X address and Y address goes to last address, next address is 00H.
The data read mode is canceled at STB's rising edge (Switched to data write mode).

When using serial data transfer, it is necessary to write 8-bit data. No assurance is IC's operation when

. . .

Note1

STB is rising during data transfer.

9.2.8 Test mode

The test mode is set. The test mode is for checking IC’s operation, and no assurance is made for its regular use or
continued operation.

MSB

101

1

b2 b1 b0

1

LSB

Choices
000 : Nomal Operation
001 to 111 : Test mode

Data Sheet S12694EJ2V0DS00

27

★

9.3 Address register

Selects the address type and specifies the address.

µµµµ

PD16680

MSB

11b5

b4

000

0

LSB

MSB

000

++

Choice1
00 : Dot address
01 : Pictograph group address
10 : Blink data group address

b3

0

LSB

b2 b1 b0

MSB

00b5

X address
Dot display group address : 00H to 0CH
Pictograph group address : 00H to 0CH
Blink group address : 00H to 0CH

b3

b4

LSB

b2 b1 b0

Y address
Dot display group address : 00H to 33H
Pictograph group address : 00H
Blink group address : 00H

Caution If unspecified addresses have been set, operation is not assured.

10. RESETTING

When reset (command reset, hardware (terminal) reset), the contents of each register are as follows.

Register name

b7 b6 b5 b4 b3 b2 b1 b0

Register contents

Status

Display ON / OFF 00001000LCD OFF (SEGn, COMn, PCOM = VSS)
Standby 0 0 0 1 0 0 0 0 Normal operat i on
Duty setting 0 0 0 1 1 0 0 0 1/53 duty
D/A converter setting 1 0 0 0 0 0 0 0 To set 20H
Blink setting 01000000Blink halt
Data R/W mode 1 0 1 1 0 0 0 0 Data write, the addres s is incremented(+1) starting

from current address.

Test mode 1 0 1 1 1 0 0 0 Normal operat i on

28

Data Sheet S12694EJ2V0DS00

11. COMMUNICATION FORMAT

11.1 serial

11.1.1 Reception 1 (Command/Data write : 1 byte)

STB

µµµµ

PD16680

DATA

SCK

b7 b6 b5 b2 b1 b0

12

3

11.1.2 Reception 2 (Command/Data write : 2 bytes or more)

STB

DATA

SCK

b7 b6 b5 b2 b1 b0

123

6781 2

Command 1 Command 2/Data

67

b6 b5 b4 b3

b7

45

3

8

11.1.3 Transmission (Command/Data read)

STB

DATA

SCK

b7 b6 b5 b2 b1 b0 b7 b6 b5 b4 b3

123

Data Read Command

678 123456

Wait time : t

Data Sheet S12694EJ2V0DS00

WAIT

Data read

29

11.2 Parallel

11.2.1 8-bit parallel interface

STB

D

0

to D

7

E

11.2.2 4-bit parallel interface

STB

µµµµ

PD16680

D

0

to D

7

E

Upper Upper UpperLower Lower Lower

30

Data Sheet S12694EJ2V0DS00

12 CPU ACCESS EXAMPLE

12.1 Initialize and write data

µµµµ

PD16680

Item STB

Start H xxxxxxxx
Reset L 00100111

Duty setting L 0 0 0 1 1 0 0 0 1/53 duty

Address Register 1 L 1 1 0 0 0 0 0 0 Dot address
Address Register 2 L 0 0 0 0 0 0 0 0 X address = 00H
Address Register 3 L 0 0 0 0 0 0 0 0 Y address = 00H

Data R/W mode L 10110000

Dot display Data 1

Dot display Data 663

Address Register 1 L 1 1 0 1 0 0 0 0 Pict ograph group address
Address Register 2 L 0 0 0 0 0 0 0 0 X address = 00H
Address Register 3 L 0 0 0 0 0 0 0 0 Y address = 00H

b7 b6 b5 b4 b3 b2 b1 b0

H xxxxxxxx

H xxxxxxxx

H xxxxxxxx

L

L
H xxxxxxxx

H xxxxxxxx

Command / Data

Data write,
The address is increment ed starting from the current one.

DDDDDDDDDDDDDDDDDot data

(63 bytes)

Explanation

Data R/W mode L 10110000

Pictograph Data 1

Pictograph Data 13

Display ON / OFF L 00001111LCD ON
End H xxxxxxxx

Remark

x = Don't Care, D = data

L

DDDDDDDDDDDDDDDDPictograph data

L
H xxxxxxxx

Data write,
The address is increment ed starting from the current one.

(13 bytes)

Data Sheet S12694EJ2V0DS00

31

12.2 Change display data and pictograph data (All data are changed)

µµµµ

PD16680

Item STB

Start H xxxxxxxx
Address Register 1 L 1 1 0 0 0 0 0 0 Dot address
Address Register 2 L 0 0 0 0 0 0 0 0 X address = 00H
Address Register 3 L 0 0 0 0 0 0 0 0 Y address = 00H

Data R/W mode L 10110000

Dot display Data 1

Dot display Data 663

Address Register 1 L 1 1 0 1 0 0 0 0 Pict ograph group address
Address Register 2 L 0 0 0 0 0 0 0 0 X address = 00H
Address Register 3 L 0 0 0 0 0 0 0 0 Y address = 00H

Data R/W mode L 10110000

Pictograph Data 1

Pictograph Data 13
End H xxxxxxxx

b7 b6 b5 b4 b3 b2 b1 b0

H xxxxxxxx

L

L
H xxxxxxxx

H xxxxxxxx

L

L

Command / Data

Data write,
The address is increment ed starting from the current one.

DDDDDDDDDDDDDDDDDot data

(663 bytes)

Data write,
The address is increment ed starting from the current one.

DDDDDDDDDDDDDDDDPictograph data

(13 bytes)

Explanation

Remark

x = Don't Care, D = data

32

Data Sheet S12694EJ2V0DS00

12.3 Read display data and pictograph data (All data are read)

µµµµ

PD16680

Item STB

Start H xxxxxxxx
Address Register 1 L 1 1 0 0 0 0 0 0 Dot address
Address Register 2 L 0 0 0 0 0 0 0 0 X address = 00H
Address Register 3 L 0 0 0 0 0 0 0 0 Y address = 00H

Data R/W mode L 10110100

Dot display Data 1

Dot display Data 663

Address Register 1 L 1 1 0 1 0 0 0 0 Pict ograph group address
Address Register 2 L 0 0 0 0 0 0 0 0 X address = 00H
Address Register 3 L 0 0 0 0 0 0 0 0 Y address = 00H

Data R/W mode L 10110100

Pictograph Data 1

Pictograph Data 13
End H xxxxxxxx

b7 b6 b5 b4 b3 b2 b1 b0

H xxxxxxxx

L

L
H xxxxxxxx

H xxxxxxxx

L

L

Command / Data

Data read,
The address is increment ed starting from the current one.

DDDDDDDDDDDDDDDDDot data

(663 bytes)

Data read,
The address is increment ed starting from the current one.

DDDDDDDDDDDDDDDDPictograph data

(13 bytes)

Explanation

Remark

x = Don't Care, D = data

Data Sheet S12694EJ2V0DS00

33

12.4 Blink data setting

µµµµ

PD16680

Item STB

Start H xxxxxxxX
Address Register 1 L 1 1 1 0 0 0 0 0 Blink group address
Address Register 2 L 0 0 0 0 0 0 0 0 X address = 00H
Address Register 3 L 0 0 0 0 0 0 0 0 Y address = 00H

Data R/W mode L 10110000

★

Blink Data 1

Blink Data 13

★
★

Blink setting L 0 1 0 0 0 0 1 0 Blink start, blink frequency = f
End H xxxxxxxx

Remark

x= Don't Care, D = data

b7 b6 b5 b4 b3 b2 b1 b0

H xxxxxxxx

L

L
H xxxxxxxx

Command / Data

Data write,
The address is increment ed starting from the current one.

DDDDDDDDDDDDDDDDBlink data

(13 bytes)

Explanation

BRI

/2

34

Data Sheet S12694EJ2V0DS00

13. ELECTRICAL SPECIFICATIONS

µµµµ

PD16680

Absolute maximum ratings (TA =+25

C, VSS =0 V)

°°°°

Parameter Symbol Ratings Unit

LC1

DD

DD

LCD

to V

IN1

OUT1

I/01

IN2

OUT2

A

stg

LC5

–0.3 to +3.75 V

–0.3 to +5.0 V

–0.3 to +15.0, VDD ≤ V

–0.3 to V

LCD

LCD

+0.3 V
–0.3 to VDD+0.3 V
–0.3 to VDD+0.3 V
–0.3 to VDD+0.3 V

–0.3 to V
–0.3 to V

LCD

+0.3 V

LCD

+0.3 V

–40 to +85

–55 to +150

Supply voltage (4-fold voltage mode) V
Supply voltage (3-fold voltage mode) V
Driver supply voltage V
Driver reference supply input volt age V
Logic system input vol t age V
Logic system output vol tage V
Logic system input / output voltage V
Driver system input volt age V
Driver system output voltage V
Operating temperature T
Storage temperature T

Caution If the absolute maximum rating of even one of the above parameters is exceeded even

momentarily, the quality of the product may be degraded. Absolute maximum ratings, therefore,
specify the values exceeding which the product may be physically damaged. Be sure to use the
product within the range of the absolute maximum ratings.

V

C

°

C

°

Recommended operating range

Parameter Symbol MIN. TYP. MAX. Unit
Supply voltage (4-fold voltage mode) V
Supply voltage (3-fold voltage mode) V
Driver supply voltage
Logic system input vol t age V

Driver system input volt age V

Note

When to use external LCD driving, this parameter is recommended.

Remarks1.

2.

3.

Note

LC1

When to use external LCD driving, keep V
When power on or power off moment, keep V
When to use internal LCD driving circuit and not to use D/A converter, keep voltage inputted to

IN(+)

AMP

pin to 1.0V to VDD.

LCD

V

to V

DD

DD

2.4 3.0 V

2.4 4.0 V

5.0 10 12 V

IN

LC5

0V
0V

SS

LC5 < VLC4

V

<

DD

≤

V

LCD

< V

LC3

LC2

V

< V

<

LC1

≤ V

LCD

DD

V
V

LCD

Data Sheet S12694EJ2V0DS00

35

µµµµ

PD16680

Electrical characteristics

Parameter Symbol Conditions MIN. TYP. MAX. Unit

★

High-level input voltage V
Low-level input voltage V
High-level input current I
Low-level input current I
High-level output voltage V
Low-level output voltage V
High-level leakage current I

Low -level leakage current I

Common output ON resistance R

Segment output ON resistance R

★

★

Current consumption (VDD)
Level condenser mode

Current consumption (VDD)

★

LCD driving mode

Driver current consumpti on

DD

(V

, Standby)

(Unless otherwise specified,

TA = –40 to +85°C, 4-fold voltage mode : VDD = 2.7 to 3.0V or

3-fold voltage mode : VDD = 2.7 to 4.0 V)

IH

IL

IH1

Except DO/DATA, D1 to D

IL1

Except DO/DATA, D1 to D

OH

OUT

I

= –1.5 mA, Except OSC

OL

OUT

I

= 4 mA, Except OSC

DD11

I

DD12

I

DD21

I

LOH

DO/DATA, D1 to D

IN/OUT

V

LOL

DO/DATA, D1 to D

IN/OUT

V

COM

LCn

V
lIOl = 50 µA

SEG

LCn

V
lIOl = 50 µA

LCD

3-fold voltage mode
4-fold voltage mode

OSC

f

DD

= 3.0 V,3-fold voltage m ode

V
Not to access to RAM.

OSC

f

DD

= 3.0 V,4-fold voltage m ode

V
Not to access to RAM.

OSC

f

DD

= 3.0 V,3-fold voltage m ode

V
Not to access to RAM.

OSC

f

DD

= 3.0 V,4-fold voltage m ode

V
Not to access to RAM.
VDD = 3.0 V

= V

= V

→

COM

→

SEG

= 32 kHz, Display-off data output

= 32 kHz, Display-off data output

= 32 kHz, Display-off data output

= 32 kHz, Display-off data output

7

DD

7

SS

n

LCD

≥ 3V

≥ 3V

DD

DD

, V

n

LCD

, V

7

7

OUT

OUT

0.8 V

VDD–0.5

2.7 V

3.6 V

DD

0.2 V
1

–1

V
V

DD

A

µ

A

µ

V

0.5 V
10

–10

2k

4k

DD

DD

3.0 V

4.0 V

95

125

160

250

10

A

µ

A

µ

Ω

Ω

VDriver voltage (Booster voltage) V

DD

V

DD

A

µ

A

µ

A

µ

A

µ

A

µ

36

Data Sheet S12694EJ2V0DS00

µµµµ

PD16680

Switching characteristics

Parameter Symbol Conditions MIN. TYP. MAX. Unit
Oscillation frequency F
Transfer delay time 1 t
Transfer delay time 2 t

★

Remarks 1.

The TYP. value is a reference value when T

2.

The time for one frame is found from the following formula.

1 frame = 1/fosc x 8 x number of duties

(Example)

(Unless otherwise specified, T

OSC

Self-oscillation 25 32 38 kHz

PHL

SCK↓ → DATA

PLH

SCK↓ → DATA

OSC

f

= 32 kHz, 1/53, then the result is :

1 frame = 33

s x 8 x 53 = 13.25 ms ≅ 75.5 Hz

µ

A

= –40 to +85°C, VDD = 2.7 to 3.3 V)

↓
↑

A

=+25°C.

100 ns
300 ns

Data Sheet S12694EJ2V0DS00

37

µµµµ

PD16680

Required conditions for timing

(Unless otherwise specified, T

1. Common

Parameter Symbol Conditions MIN. TYP. MAX. Unit

Clock frequency f

WHC1

High-level clock puls e width
Low -level clock pulse width
High-level clock puls e width
Low -level clock pulse width

t

t

WHC2

t

WLC2

t
Rise/Fall time tr, t
Reset pulse width t

Remark

The TYP. value is a reference value when T

2. Serial interface

Parameter Synbol Conditions MIN. TYP. MAX. Unit

Shift clock cycle t
High-level shift clock pulse width

Low-level shift clock puls e width
Shift clock hold time

Data setup time t
Data hold time t
STB hold time t
STB pulse width t
Wait time

Note

CYK

WHK

t

WLK

t

HSTBK

t

DS1

DH1

HKSTB

WSTB

WAIT

t

OSC

WLC1

WRE

A

= –40 to +85°C, VDD = 2.7 to 3.3 V)

IN

OSC

external clock 20 32 50 kHz

IN

OSC

external clock 10 25

IN

OSC

external clock 10 25

BRI

OSC

external clock 400 ns

BRI

OSC

external clock 400 ns

f

BRI

OSC

external clock 100 ns

/RESET pin 50

A

=+25°C.

SCK 900 ns
SCK 295 ns
SCK 295 ns
STB↓ → SCK
DATA → SCK

↓

↑

400 ns

40 ns
SCK↑ → DATA 40 ns
SCK↑ → STB

↑

400 ns
210 ns

8th CLK↑ →1st CLK

↓

100 ns

s

µ

s

µ

s

µ

Note

11.1.3 Transmission (Command/Data read)

See

3. Parallel interface

Parameter Symbol Conditions MIN. TYP. MAX. Unit

Enable cycle time
High-level enable pulse width
Low-level enable pulse width

t
t

t
STB pulse width t
STB hold time t
Enable hold time t
Data setup time t
Data hold time t

38

CYCE

WHE

WLE

WSTB

HKSTB

HSTBK

DS2

DH2

.

E↑ → E

↑

E 295 ns
E 295 ns

7

D0 to D
D0 to D

→ E↑

7

→ E↓

Data Sheet S12694EJ2V0DS00

900 ns

210 ns
400 ns
400 ns

40 ns
40 ns

Switching characteristics waveforms

AC measurement point

Input

Output

AC characteristics waveform

OSC

IN

t

WHC1

1/f

µµµµ

PD16680

V

IH

V

IL

V

OH

V

OL

t

WLC1

OSC

t

f

t

r

OSC

BR1

Serial interface (Input)

STB

tHSTBK

SCK

DATA

Serial interface (Output)

t

WHC2

tCYK

tWHK

tDS1 tDH1

t

WLC2

tHKSTB

tWSTB

SCK

DATA

t

PHL

Data Sheet S12694EJ2V0DS00

t

PLH

39

4-bit parallel interface

STB

t

HSTBK

E

D

n

STB

E

µµµµ

PD16680

t

CYCE

t

t

WLE

t

DS2

WHE

t

DH2

Upper bit Upper bit

Lower bit

t

HKSTB

t

WSTB

D

n

8-bit parallel interface

STB

t

HSTBK

E

n

D

Reset

/RESET

Upper bit Upper bit

t

CYCE

t

t

WLE

t

DS2

WHE

t

DH2

Lower bit

t

HKSTB

t

WSTB

40

t

WRE

Data Sheet S12694EJ2V0DS00

[MEMO]

µµµµ

PD16680

Data Sheet S12694EJ2V0DS00

41

[MEMO]

µµµµ

PD16680

42

Data Sheet S12694EJ2V0DS00

NOTES FOR CMOS DEVICES

1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS

Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.

2 HANDLING OF UNUSED INPUT PINS FOR CMOS

Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused

DD

pin should be connected to V
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.

or GND with a resistor, if it is considered to have a possibility of

µµµµ

PD16680

3 STATUS BEFORE INITIALIZATION OF MOS DEVICES

Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.

Data Sheet S12694EJ2V0DS00

43

µµµµ

PD16680

• The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.

• No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
this document.

• NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property
rights of third parties by or arising from use of a device described herein or any other liability arising from use
of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other
intellectual property rights of NEC Corporation or others.

• Descriptions of circuits, software, and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these circuits,
software, and information in the design of the customer's equipment shall be done under the full responsibility
of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third
parties arising from the use of these circuits, software, and information.

• While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.

• NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a
customer designated "quality assurance program" for a specific application. The recommended applications of
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.

M7 98. 8