DATA SHEET
MOS INTEGRATED CIRCUIT
µµµµ
PD16432B
1/8, 1/15 DUTY LCD CONTROLLER/DRIVER
DESCRIPTION
The µPD16432B is a controller/driver with 1/8 and 1/15 duty dot matrix LCD display capability. It has 60 segment
outputs, 10 common outputs, and 5 dual segment/common outputs, giving a maximum display capability of 12
columns × 2 lines (at 1/15 duty).
LED drive outputs, key scanning key source outputs, and key data inputs are also provided, making it ideal for use
in a car stereo front panel, etc.
FEATURES
• Dot matrix LCD controller/driver
• Pictograph display segment drive capability (max. 64)
• LCD driver unit power supply V
• On-chip key scan circuit (8 × 4 matrix)
• Alphanumeric character and symbol display capability provided by on-chip ROM (5 × 7 dots)
240 characters + 16 user-defined characters
• Display contents
1/8 duty: 13 columns × 1 line, 64 pictograph displays, 4 LEDs
1/15 duty: 12 columns × 2 lines, 60 pictograph displays, 4 LEDs
• Serial data input/output (SCK, STB, DATA)
• On-chip oscillator
• Reduced power consumption possible using standby mode
LCD
independently settable (Max. 10 V)
ORDERING INFORMATION
Part Number Package
µ
PD16432BGC-001-9EU 100-pin plastic QFP (0.5 pit ch, 14 × 14), Standard ROM code
Document No. S11092EJ5V0DS00 (5th edition)
Date Published April 1998 N CP(K)
Printed in Japan
1998©
BLOCK DIAGRAM
4
LED1LED
1
/KS
1
SEG
8
/KS
8
9
SEG
SEG
14
/COM
61
SEG60SEG
10
/COM
65
SEG
9
COM
µµµµ
PD16432B
0
COM
4
LED
Driver
4
4-Bit LED
Output Latch
4
Segment Driver
65-Bit Output Latch
65-Bit Shift Register
Parallel/Serial Conversion
5
CG
RAM
5 × 7
5
CG ROM
5 × 7 × 240
× 16
65
65
5
5
5
Common Driver
15
15-Bit Shift Register
2
Timing Generator
8
OSC
IN
8
Display
Data RAM
8 × 25
Character
Display
RAM
OSC
OSC
OUT
64 Bits
2
STB
SCK
DATA
RESET
LCD OFF
SYNC
Serial I/F
Command
Decoder
5
KEY REQ
8
KEY
Key Data
1
RAM
4 × 8
SS
DD
V
LC1VLC2VLC3VLC4VLC5
LCD
V
V
V
KEY
4
PIN CONFIGURATION
µµµµ
PD16432B
SEG50
SEG49
SEG48
SEG47
SEG46
SEG45
SEG44
SEG43
SEG42
SEG41
SEG40
SEG39
SEG38
SEG37
SEG36
SEG35
SEG34
SEG33
SEG32
SEG31
SEG30
SEG29
SEG28
SEG27
SEG26
SEG51
SEG52
SEG53
SEG54
SEG55
SEG56
SEG57
SEG58
SEG59
SEG60
SEG61/COM14
SEG62/COM13
SEG63/COM12
SEG64/COM11
SEG65/COM10
COM9
COM8
COM7
COM6
COM5
COM4
COM3
COM2
COM1
COM0
75 51
76
100
125
50
26
SEG25
SEG24
SEG23
SEG22
SEG21
SEG20
SEG19
SEG18
SEG17
SEG16
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10
SEG9
SEG8/KS8
SEG7/KS7
SEG6/KS6
SEG5/KS5
SEG4/KS4
SEG3/KS3
SEG2/KS2
SEG1/KS1
VSS
VLC5
VLC4
VLC3
LED1
LED2
LED3
LED4
VLC2
VLC1
VLCD
VDD
SYNC
LCD OFF
SCK
RESET
KEY REQ
STB
DATA
IN
OSC
OSCOUT
KEY1
KEY2
KEY3
KEY4
3
PIN DESCRIPTIONS
Pin Symbol Pin Name Pin No. Function
µµµµ
PD16432B
SEG1/KS1 to
8
8
/KS
SEG
SEG9 to SEG
SEG61/COM14 to
85
/COM
SEG
Segment output/key source
output dual-function pins
60
Segment outputs 34 to 85 Dot matrix LCD segment outputs
Segment output/common
10
output dual-function pins
26 to 33 Pins with dual function as dot matrix LCD segment outputs and
key scanning key source outputs
86 to 90 Switchable to either dot matrix LCD segment outputs or com-
mon outputs
COM0 to COM9Common outputs 91 to 100 Dot matrix LCD common outputs
LED1 to LED
4
LED output pins 1 to 4 LED outputs are Nch open-drain.
SCK Shift clock input 17 Data shift clock
Data is read on rising edge, and output on falling edge.
DATA Data input/output 18 Performs input of commands, key data, etc., and key data
output. Input is performed from the MSB on the rise of the shift
clock, and the first 8 bits are recognized as a command. Output
is performed from the MSB on the fall of the shift clock.
Output is Nch open-drain.
STB Strobe input 19 Data input is enabled when “H”. Command processing is
performed on a fall.
KEY REQ Key request output 16 “H” if there is key data, “L” if the r e is none. Key data can be read
irrespective of the state of this pin. Output is CMOS output.
RESET Reset input 15 Initial state is set when “L”.
LCD OFF LCD off input 14 When “L”, a forced LCD off operation is performed, and SEG
n
& COMn output the unselected waveform.
SYNC Synchro 13 Synchronization signal input/output pin. When 2 or more chips
are used, wired-OR connection is made to each chip. A pull-up
resistor is also required when one chip is used.
IN
OSC
OUT
OSC
KEY1 to KEY
DD
V
SS
V
LCD
V
LC1
to V
LC5
V
Oscillation pins
4
Key data inputs 22 to 25 Key scanning key data inputs.
Logic power supply pin 12 Internal logic power supply pin
GND pin 5 GND pin
LCD drive voltage pin 11 LCD drive power supply pin
LCD drive power supply 10 to 6 Dot matrix LCD drive power supply
20
21
Connect oscillator resistor.
4
µµµµ
PD16432B
LCD DISPLAY
In the µPD16432B LCD display, a 5 × 7-segment display and pictograph display segments can be driven. The
0
pictograph display segment common output is allocated to COM
(1) Example of 1/8 duty connections
1
SEG
2345
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM0
, and up to 64 can be driven.
616263 64 65678910
(2) Example of 1/15 duty connections
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM0
1SEG
2345
64 Pictograph Segments
565758 59 60678910
60 Pictograph Segments
5
µµµµ
PD16432B
CHARACTER CODES AND CHARACTER PATTERNS
The relation between character codes and character patterns is shown below. Character codes 00H to 0FH are
allocated to CGRAM.
Character codes 10H to 1FH and E0H to FFH are undefined.
Higher
Lower
Bits
Bits
0XH
1XH 2XH 3XH
4XH 5XH 6XH
7XH 8XH 9XH AXH BXH CXH DXH EXH FXH
X0HRAM
X1HRAM
X2HRAM
X3HRAM
X4HRAM
X5HRAM
X6HRAM
X7HRAM
X8HRAM
CG
(1)
CG
(2)
CG
(3)
CG
(4)
CG
(5)
CG
(6)
CG
(7)
CG
(8)
CG
(9)
X9HRAM
XAHRAM
XBHRAM
XCHRAM
XDHRAM
XEHRAM
XFHRAM
CG
(10)
CG
(11)
CG
(12)
CG
(13)
CG
(14)
CG
(15)
CG
(16)
6
DISPLAY RAM ADDRESSES
Display RAM addresses are allocated as shown below irrespective of the display mode.
Column No.12345678910111213
Line 1 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH
Line 2 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H
PICTOGRAPH DISPLAY RAM ADDRESSES
Pictograph display RAM addresses are allocated as shown below.
µµµµ
PD16432B
Address
00H 12345678
01H 9 10111213141516
02H 17 18 19 20 21 22 23 24
03H 25 26 27 28 29 30 31 32
04H 33 34 35 36 37 38 39 40
05H 41 42 43 44 45 46 47 48
06H 49 50 51 52 53 54 55 56
07H 57 58 59 60 61 62 63 64
Note
b7 b6 b5 b4 b3 b2 b1 b0
When 1/15 duty is used (12 columns × 2 lines), 61 to 64 are disabled.
Segment Output No.
7
µµµµ
PD16432B
CGRAM COLUMN ADDRESSES
A maximum of any sixteen 5 × 7-dot characters can be written in CGRAM. The row address within one character is
allocated as shown below, and is specified by bits b7 to b5.
The character code for which a write is to be performed must be specified beforehand with an address setting
command.
Row
Address
00H 0 0 0
01H 0 0 1
02H 0 1 0
03H 0 1 1
04H 1 0 0
05H 1 0 1
06H 1 1 0
Font data (1: on, 0: off)
*
b7 b6 b5 b4 b3 b2 b1 b0
Row Address Font Data
Dot Data
*****
*****
*****
*****
*****
*****
*****
(5 × 7 Dots)
8
KEY MATRIX AND KEY DATA RAM CONFIGURATION
The key matrix has an 8 × 4 configuration, as shown below.
KEY1
µµµµ
PD16432B
KEY2
=
KEY3
KEY4
KS1 KS2 KS3 KS4 KS5 KS6 KS7 KS8
Key data is stored as shown below, and is read in MSB-first order by a read command.
b7 b4 b3
KS
8
KS
6
KS
4
KS
2
KEY
KEY
3
4
KEY
KS
KS
KS
KS
2
7
5
3
1
KEY
b0
Key data is as follows:
1: On
0: Off
Read Order
1
Key Input Equivalent Circuit
VDD
Pull-Up
Control Signal
R
To Key
Data RAM
In the event of key source output, the pull-up control signal
becomes “H”, and the pull-up transistor is turned on.
KEYn
9
KEY REQUEST (KEY REQ)
A key request is output as shown below according to the state.
µµµµ
PD16432B
State
In key scan operation High level is output while any key
data is “1”.
In standby mode or when SEG
& COMn are fixed at V
When key scanning is stopped Fixed at low level Always OFF
KEY REQ does not become low until the key data is all “0”.
Note
LC5
n
High level is output in case of key
input only.
KEY REQ
Note
Note
Key Scan Internal Pull-Up Resistor
During key scan : ON
During display : OFF
Always ON
(It is not synchronized with the key data reads.)
LED OUTPUT LATCH CONFIGURATION
The low-order 4 bits of the LED output latch are enabled, and the high-order 4 bits disabled, as shown below.
LSBMSB
b3 b2 b1 b0
××××
Latch data is as follows:
1: On
0: Off
×
: Don’t Care
LED1
LED2
LED3
LED4
10
µµµµ
PD16432B
COMMANDS
Commands set the display mode and status.
The first byte after a rise edge on the STB pin is regarded as a command.
If STB is driven low during command/data transfer, serial communication is initialized and the command/data being
transferred is invalidated. (However, a command or data that has already been transferred is valid.)
(1) Display Setting Command
This command initializes the
slave operation, and the drive voltage supply method.
The state set when this command is executed is: LCD off, LED on, key scanning stopped. To restart the display,
it is necessary to execute “status command” normal operation. However, nothing is done if the same mode is
selected.
×
00
After powering on
Note
××
×
××
When multiple chips are used, only the chip that sent the command is enabled. If initialization is
performed during display, the display may be affected (especially when multiple chips are used).
PD16432B
µ
b2 b1 b0
000
Note
, and sets the duty, number of segments, number of commons, master/
LSBMSB
×
: Don’t Care
Duty setting
0: 1/8 duty (SEG61/COM14 to SEG65/COM10 → segment outputs)
1: 1/15 duty (SEG61/COM14 to SEG65/COM10 → common outputs)
Master/slave setting
0: Master
1: Slave
Drive voltage supply method selection
0: External
1: Internal
11
(2) Data Setting Command
Sets the data write mode, read mode, and address increment mode.
LSBMSB
b3 b2 b1 b0
10
After powering on
××
0000
××
×
: Don’t Care
Data write mode/read mode setting
000: Write to display data RAM
001: Write to character display RAM
010: Write to CGRAM
011: Write to LED output latch
100: Read key data
Address increment mode setting
(Display data RAM, character display RAM)
0: Increment after data write
1: Address fixed
(3) Address Setting Command
Sets the display data RAM or character display RAM address.
µµµµ
PD16432B
LSBMSB
×
01
After powering on
×
If an unspecified address is set, data cannot be written until a correct address is next set. The address
Note
b3 b2 b1 b0b4
00000
×
: Don’t Care
Address
Display data RAM
Character display RAM
CGRAM
: 00H to 18H
: 00H to 07H
: 00H to 0FH
is not incremented even in increment mode.
12
(4) Status Command
Controls the status of the
b3 b2 b1 b0b4b511
PD16432.
µ
µµµµ
PD16432B
LSBMSB
After powering on
The following states are use prohibited modes, and key scanning does not operate if these states are
Note
set.
LCD cotrol
00: LCD forced off (SEGn, COMn = V
01: LCD forced off (SEGn, COMn = unselected waveform)
10: Normal operation
11: Normal operation
LED control
0: LED forced off
1: Normal operation
Key scan control
0: Key scanning stopped
1: Key scan operation
Standby mode setting
0: Normal operation
1: Standby mode
Test mode setting
0: Normal operation
1: Test mode
000000
LC5
)
Note
100000
110000
13
µµµµ
PD16432B
STANDBY MODE
If standby mode is selected with bit b4 of the status command, the following state is set irrespective of bits b3 to b0
of the status command.
(1) LCD forced off (SEG
n
, COMn = V
LC5
)
(2) LED forced off
n
(3) Key scanning stopped (but KEY
= key input wait)
(4) OSC stopped
There are two ways of releasing standby mode, as follows:
(1) Using Status Command
Select normal operation with bit b4 of the status command.
Example of Use of Status Command
Item STB
b7 b6 b5 b4 b3 b2 b1 b0
Standby mode L
Status command H 1 1 0 0 0 0 0 0 Standby release (OSC oscillation start), LCD
Standby transition time L
Status command H 1 1 0 0 1 1 1 0 Normal operation
End L
Command/Data
Description
n
control off (SEG
off, key scanning stopped
Note
10
µ
s
, COMn = V
LC5
), LED forced
If LCD normal operation or key scan operation is initiated within the standby transition time, the LCD
Note
may flicker.
14
µµµµ
PD16432B
(2) Using KEY
n
If any key is set to the ON state, the standby mode is released and OSC oscillation starts. Also, KEY REQ is set
to “H”, informing the microcomputer that a key has been pressed and standby mode has been released. In this
state, the key data is not memorized, and therefore it is necessary to set key scanning to the normal state after
the standby transition time, and fetch the key data.
Example of Use of KEY
Item STB
Standby mode L
Key data present L Standby release (KEY REQ = H,
Standby transition time L
Status command H 1 1 0 0 1 0 0 1 LCD forced off (unselected waveform),
Key scan L 1 frame or more
Data setting command H 0 1 0 0 0 1 0 0 Key dat a read, address increment
Key data H
Key data H
Key data H
Key data H
End L Key distinction
b7 b6 b5 b4 b3 b2 b1 b0
********
********
********
********
Command/Data
n
Description
OSC oscillation start)
Note
10
µ
s
LED forced off, key scan operation
For KS8, KS
For KS6, KS
For KS4, KS
For KS2, KS
7
5
3
1
If LCD normal operation or key scan operation is initiated within the standby transition time, the LCD
Note
may flicker.
15
SERIAL COMMUNICATION FORMATS
(1) Reception (Command/Data Write)
STB
µµµµ
PD16432B
If data continues
DATA b7
SCK 123 678
b6 b5 b1 b0b2
(2) Transmission (Command/Data Read)
STB
DATA
SCK
b7 b6 b5 b2 b1 b0 b7 b6 b5 b4 b3
1 2 3 6 7 8 1 2 3 4 5 6
1 s
µ
Wait Time t
WAIT
Data ReadData Read Command Setting
Caution As the DATA pin is an Nch open-drain output, a pull-up resistor must be connected
externally. (1 k
to 10 k
Ω
Ω
Ω Ω
)
ΩΩΩΩ
16
ABSOLUTE MAXIMUM RATINGS (TA = 25°C, VSS = 0 V)
Parameter Symbol Rating Unit
µµµµ
PD16432B
LC1
to V
V
DD
IN
OUT
LCD
OUT2
Logic supply voltage V
Logic input voltage V
Logic output voltage (Dout, LED) V
LCD drive supply voltage V
LCD drive power supply input voltage V
Driver output voltage
(Segment, Common)
LED drive current I
Package allowable dissipation P
Operating ambient temperature T
Storage temperature range T
OL1
T
A
stg
RECOMMENDED OPERATING RANGES
Parameter Symbol MIN. TYP. MAX. Unit
LCD1
DD
LCD
IN
to V
OL1
Logic supply voltage V
LCD drive supply voltage V
Logic input voltage V
Driver input voltage V
LED drive current I
–0.3 to +7.0 V
–0.3 to +VDD + 0.3 V
–0.3 to +7.0 V
–0.3 to +12.0 V
LC5
–0.3 to +V
–0.3 to +V
20 mA
1000 mW
–40 to +85 °C
–55 to +150 ° C
2.7 5.0 5.5 V
DD
V
0V
LCD5
0V
LCD
+ 0.3 V
LCD
+ 0.3 V
8.0 10.0 V
DD
LCD
15 mA
V
V
17
ELECTRICAL SPECIFICATIONS
(UNLESS SPECIFIED OTHERWISE, T
Parameter Symbol Test Conditions MIN. TYP. MAX. Unit
A
= –40 to +85°C, VDD = 5 V
10%, V
±±±±
LCD
= 8 V
10%)
±±±±
µµµµ
PD16432B
High-level input voltage V
Low-level input voltage V
High-level input current I
Low-level input current I
Low-level output voltage V
High-level output voltage V
Low-level output voltage V
High-level leak cur r en t I
Low-level leak current I
Common output ON-
R
resistance
Segment output ON-
R
resistance
Current consumption
(Logic)
Current consumption
(Driver)
IH
IL
IH
IL
OL1
OH2
OL2
LOH2
LOL2
COM
SEG
DD1
I
DD2
I
LCD1
I
LCD2
I
SCK, STB, LCDOFF, RESET, KEY1 to KEY
SCK, STB, LCDOFF, RESET, KEY1 to KEY
LED1 to LED4, I
OUT
OSC
, KEY REQ, I
DATA, OSC
OUT
DATA, SYNC, V
DATA, SYNC, V
LCD
LCD
LC5
to V
→ COM0 to COM14, | IO | = 100 µA2.4k
LC5
to V
→ SEG1 to SEG60, | IO | = 100 µA4.0k
V
V
Normal operation
OSC
= 250 kHz
f
Standby mode, VI = VDD or VSS, f
Normal operation, internal bias selected, no load 1 000
Standby mode, internal bias used, no load 5
DD
0.7 V
0 0.3 V
4
4
OL1
= 15 mA 1.0 V
OH2
= –1 mA 0.9 V
, SYNC, I
OL2
IN/OUT
= V
IN/OUT
= V
Note
, VI = VDD or VSS,
= 4 mA 0.1 V
DD
SS
OSC
stopped 5
DD
DD
V
1
–1
1
–1
500
DD
DD
V
V
A
µ
A
µ
V
V
A
µ
A
µ
Ω
Ω
A
µ
A
µ
A
µ
A
µ
Normal operation: V
Note
Remarks
TYP. values are reference values for T
DD
= 5 V, V
LCD
= 8 V
A
= 25°C.
18
SWITCHING SPECIFICATIONS
(UNLESS SPECIFIED OTHERWISE, T
Parameter Symbol Test Conditions MIN. TYP. MAX. Unit
A
= –40 to +85°C, VDD = V
LCD
= 5 V
10%, RL = 5 k
±±±±
µµµµ
PD16432B
, CL = 150 pF)
ΩΩΩΩ
Oscillator frequency f
Output data delay time t
Output data delay time t
SYNC delay time t
The time for one frame is found as follows.
Note
1 frame = 1/f
OSC
If f
= 250 kHz and duty = 1/15, 1 frame = 4 µs × 128 × 15 + 4 µs × 64 = 7.94 ms
OSC
PZL
PLZ
DSYNC
OSC
× 128 clocks × duty number + 1/f
R = 100 k
SCK ↓ → DATA
SCK ↓ → DATA
REQUIRED TIMING CONDITIONS
(UNLESS SPECIFIED OT H ER WIS E, T
L
= 150 pF)
C
Parameter Symbol Test Conditions MIN. T YP. MAX. Unit
Clock frequency f
High-level clock pulse width t
Low-level clock pulse width t
Shift-clock cycle t
High-level shift clock pulse width t
Low-level shift clock pulse width t
Shift clock hold time t
Data setup time t
Data hold time t
STB hold time t
STB hold time t
Wait time t
SYNC removal time t
Standby transition time t
Reset pulse width t
Power-ON reset time t
OSC
WHC
WLC
CYK
WHK
WLK
HSTBK
DS
DH
HKSTB
WSTB
WAIT
SREM
PSTB
WRS
PON
Ω
↓
↑
OSC
× 64 clocks
A
= –40 to +85°C , VDD = 5 V
±±±±
175 250 325 kHz
10%, V
LCD
= 8 V
10%, RL = 5 k
±±±±
100 ns
300 ns
1.5
µ
s
OSCIN external clock 100 500 kHz
OSCIN external clock 1 5
OSCIN external clock 1 5
µ
µ
SCK 900 ns
SCK 400 ns
SCK 400 ns
STB ↑ → SCK
DATA → SCK
↓
↑
1.5
µ
100 ns
SCK ↑ → DATA 200 ns
SCK ↑ → STB
↓
8th SCK ↑ → 9th SCK ↓, in data read 1
1
1
µ
µ
µ
250 ns
10
RESET 0.1
µ
µ
From Power-ON 4 CLK
,
ΩΩΩΩ
s
s
s
s
s
s
s
s
19
OUTPUT LOAD CIRCUIT
V
DD
5 kΩ
DATA
150 pF
SWITCHING SPECIFICATION WAVEFORM DIAGRAMS
1/f
C
V
IH
OSC
IN
V
IL
t
WHC
µµµµ
PD16432B
STB
SCK
DATA
t
WLC
V
IH
t
HSTBK
t
CYK
t
WLK
V
IH
V
IL
V
V
t
WLK
t
DS
t
DH
IH
IL
t
HKSTB
V
IH
V
IL
t
WSTB
20
SWITCHING SPECIFICATION WAVEFORM DIAGRAMS
µµµµ
PD16432B
f
OSC
SYNC
Internal Reset
SCK
SYNC Timing (Master)
One Frame One Frame
t
DSYNC
V
IL
t
PZL
SYNC Timing (Slave)
One Frame One Frame
t
SREM
t
PLZ
DATA
RESET
RESET
t
WRE
V
OL2
21
OUTPUT WAVEFORMS
(1) 1/8 Duty (1/4 Bias: VLC2: VLC3)
0 1 2 3 4 5 6 7 K 0 1
V
LCD
V
LC1
V
COM
COM
COM
LC2
0
V
LC4
V
LC5
LCD
V
V
LC1
V
LC2
1
V
LC4
V
LC5
V
LCD
V
LC1
V
LC2
7
V
LC4
V
LC5
µµµµ
PD16432B
* Key scan period
*
SEG
SEG
SEG1-COM
SEG1-COM
1
2
0
–1/4V
–2/4V
–3/4V
1
–1/4V
–2/4V
–3/4V
3/4V
2/4V
1/4V
–V
3/4V
2/4V
1/4V
–V
V
LCD
V
LC1
V
LC2
V
LC4
V
LC5
V
LCD
V
LC1
V
LC2
V
LC4
V
LC5
V
LCD
LCD
LCD
LCD
0
LCD
LCD
LCD
LCD
V
LCD
LCD
LCD
LCD
0
LCD
LCD
LCD
LCD
µ µ
256 s512 s
22
4.4 ms
Enlargement of Key Scan Period
µµµµ
PD16432B
COM0
SEG1KSEG1
SEG2
SEG8
SEG9 to SEG65
VLCD
VLC1
VLC2
VLC4
VLC5
V
LCD
VLC1
VLC2
VLC4
VLC5
VLCD
VLC1
VLC2
VLC4
VLC5
VLCD
VLC1
VLC2
VLC4
VLC5
VLCD
VLC1
VLC2
VLC4
VLC5
7
1 2 3 4 5 6 7 8
0
= Key source output
23
(2) 1/15 Duty (1/5 Bias)
COM
0
1/2V
LCD
COM
1
1/2V
LCD
COM
14
1/2V
LCD
µµµµ
PD16432B
* Key scan period
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 K 1 2
LCD
V
V
LC1
V
LC2
V
LC3
V
LC4
V
LC5
V
LCD
V
LC1
V
LC2
V
LC3
V
LC4
V
LC5
V
LCD
V
LC1
V
LC2
V
LC3
V
LC4
V
LC5
*
SEG
SEG1-COM
1
0
–1/5V
–1/2V
–3/5V
3/5V
1/2V
1/5V
–V
V
LCD
V
LC1
V
LC2
V
LC3
V
LC4
V
LC5
V
LCD
LCD
LCD
LCD
0
LCD
LCD
LCD
LCD
512 s
µ µ
256 s
7.9 ms
24
Enlargement of Key Scan Period
µµµµ
PD16432B
COM
1/2V
SEG
SEG
SEG
SEG9 to SEG
LCD
14
K
0
1 2 3 4 5 6 7 8
LCD
V
V
LC1
0
V
LC2
V
LC3
V
LC4
LC5
V
V
LCD
V
LC1
1
V
LC2
V
LC3
V
LC4
V
LC5
V
LCD
V
LC1
2
V
LC2
V
LC3
V
LC4
V
LC5
V
LCD
V
LC1
8
V
LC2
V
LC3
V
LC4
V
LC5
V
LCD
V
LC1
65
V
LC2
V
LC3
V
LC4
V
LC5
= Key source output
25
ACCESS PROCEDURES
Access procedures are illustrated below by means of flowcharts and timing charts.
1. Initialization
(1) Flowchart
Start
µµµµ
PD16432B
Initial state
initialization
Key scan start
Display data RAM
write
Address setting
Display data
All data written?
YES
NO
Display setting command (command 1)
LSBMSB
01010000
Status command (command 2)
LSBMSB
10010011
Data setting command (command 3)
LSBMSB
00000010
Address setting command (command 4)
LSBMSB
00000001
(1/15 duty, master, internal drive)
(LCD off, LED off, key scan operation)
(Display data RAM, increment)
(Display data RAM: 0H)
26
Character display
RAM write
Character data
All data written?
YES
NO
Data setting command (command 5)
00010010
LSBMSB
(Character display RAM, increment)
µµµµ
PD16432B
LED output latch
write
LED data
LCD, LED on
To next processing
(2) Timing chart
DATA
SCK
STB
DATA
Data setting command (command 6)
LSBMSB
00110010
Status command (command 7)
11100011
Command 1 Command 2 Command 3 Command 4 Data 1
Data n-1 Data n Command 5 Data 1
(LED latch, increment)
LSBMSB
(LCD on, LED on, key scan operation)
SCK
STB
DATA
SCK
STB
Data n Command 6 Data Command 7
27
2. Display Data Rewrite (Address Setting)
(1) Flowchart
Start
µµµµ
PD16432B
Display data RAM
write
Address setting
Display data
To next processing
(2) Timing chart
DATA
SCK
STB
Data setting command (command 1)
LSBMSB
10000010
Address setting command (command 2)
01010001
Command 1 Command 2 Data
(Display data RAM, address fixed)
LSBMSB
(Display data RAM: 5H)
28
3. Key Data Read
(1) Flowchart
Start
KEY REQ
recognition
µµµµ
PD16432B
(2) Timing chart
KEY REQ = H?
YES
Key data read
Wait OK?
YES
Key data
All data read?
YES
To next processing
NO
NO
NO
Data setting command (command 1)
01000010
Wait time: 1 s
µ
LSBMSB
(Key data)
DATA
SCK
STB
KEY REQ
DATA
SCK
STB
KEY REQ
Command 1 Data 1 Data 2 Data 3
Cautions 1. Wait time t
until the fall of the 1st shift clock of data 1.
2. KEY REQ does not become low until the key data is all “0”.
(It is not synchronized with the key data reads.)
Data 4
WAIT
t
WAIT
(1
s) is necessary from the rise of the 8th shift clock of command 1
µµµµ
29
4. CGRAM Write
(1) Flowchart
Start
CGRAM write
Address setting
CGRAM data
Data setting command (command 1)
LSBMSB
00100010
Address setting command (command 2)
LSBMSB
00000001
µµµµ
(CGRAM, increment)
(CGRAM character code: 0H)
PD16432B
All data written?
YES
To next processing
(2) Timing chart
DATA
SCK
STB
DATA
SCK
STB
NO
Command 1 Command 2 Data 1 Data 2
Data 6 Data 7
30
5. Standby (Released by Status Command)
(1) Flowchart
Start
Status command (command 1)
Standby
Status command (command 2)
Standby release
µµµµ
PD16432B
LSBMSB
00001011
00000011
(Standby)
LSBMSB
(Standby release)
Transition
time OK?
YES
Normal operation
To next processing
(2) Timing chart
DATA
SCK
STB
NO
Standby transition time: 10 s
Status command (command 3)
Command 1 Command 2 Command 3
µ
LSBMSB
11100011
(LCD on, LED on, key scan operation)
t
STBY
31
6. Standby (Released by KEYN)
(1) Flowchart
Start
Standby
Status command (command 1)
00001011
LSBMSB
(Standby)
µµµµ
PD16432B
Key request
Transition
time OK?
YES
Normal operation
To next processing
(2) Timing chart
KEY REQ
DATA
SCK
STB
NO
Key (KEYn) input →
KEY REQ = H, OSC oscillation start
Standby transition time: 10 s
Status command (command 2)
Command 1 Command 2
µ
LSBMSB
11100011
(LCD on, LED on, key scan operation)
t
STBY
32
PACKAGE INFORMATION (UNIT: mm)
100 PIN PLASTIC TQFP (FINE PITCH) ( 14)
A
B
µµµµ
PD16432B
75
76
100
F
1
G
H
M
I
51
25
J
50
26
K
P
N
NOTE
Each lead centerline is located within 0.10 mm (0.004 inch) of
its true position (T.P.) at maximum material condition.
L
detail of lead end
C
D
S
Q
R
M
ITEM MILLIMETERS INCHES
A 16.0±0.2 0.630±0.008
B 14.0±0.2 0.551
C 14.0±0.2 0.551
D
16.0±0.2 0.630±0.008
F 1.0
G 1.0 0.039
H 0.22 0.009±0.002
I
J 0.5 (T.P.)
K 1.0±0.2 0.039
L 0.5±0.2 0.020
M 0.145 0.006±0.002
N 0.10 0.004
P 1.0±0.1 0.039
Q 0.1±0.05
R3° 3°
S 1.27 MAX. 0.050 MAX.
+0.05
–0.04
0.10 0.004
+0.055
–0.045
+7°
–3°
+0.009
–0.008
+0.009
–0.008
0.039
0.020 (T.P.)
+0.009
–0.008
+0.008
–0.009
+0.005
–0.004
0.004±0.002
+7°
–3°
S100GC-50-9EU-1
33
REFERENCE DOCUMENTS
NEC Semiconductor Device Reliability/Quality Control System (IEI-1212)
Semiconductor Device Mounting Technology Manual (C10535E)
µµµµ
PD16432B
34
[MEMO]
µµµµ
PD16432B
35
µµµµ
PD16432B
No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this
document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual
property rights of third parties by or arising from use of a device described herein or any other liability arising
from use of such device. No license, either express, implied or otherwise, is granted under any patents,
copyrights or other intellectual property rights of NEC Corporation or others.
While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on
a customer designated "quality assurance program" for a specific application. The recommended applications
of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each
device before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
Anti-radioactive design is not implemented in this product.
M4 96. 5
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