Page 1
DATA SHEET
MOS INTEGRATED CIRCUIT
µ
PD16335
96-Bit AC-PDP DRIVER
The µPD16335 is a high-voltage CMOS driver designed for flat display panels such as PDPs, VFDs and ELs. It
consists of a 96-bit bi-directional shift register, 96-bit latch and high-voltage CMOS driver. The logic block is designed
to operate using a 5-V power supply enabling direct connection to a gate array or a microcontroller. In addition, the
µ
PD16335 achieves low power dissipation by employing CMOS structure while having a high withstand voltage output
(80 V, +50/–75 mA).
FEATURES
• Selectable by IBS pin; three 32-bit bi-directional shift register circuits configuration or six 16-bit bi-directional shift
register circuits configuration
• Data control with transfer clock (external) and latch
• High-speed data transfer (f
• High withstand output voltage (80 V, +50/–75 mA
• 5 V CMOS input interface
• High withstand voltage CMOS structure
• Capable of reversing all driver outputs by PC pin
max. = 25 MHz min. at data fetch)
(fmax. = 16 MHz min. at cascade connection)
MAX.)
ORDERING INFORMATION
Part Number Package
µ
PD16335 COB
Note Please consult with an NEC sales representative about COB.
Note
Document No. S12192EJ2V0DS00 (2nd edition)
Date Published May 1998 N CP(K)
Printed in Japan
©
1998
Page 2
BLOCK DIAGRAM (IBS = H, 3-BIT INPUT, 32-BIT LENGTH SHIFT REGISTER)
OE
PC
BLK
LE
SR1
L
A
1
A
1
CLK CLK
R/L
B
A
1
2
R/L
B
A
1
2
CLK
R/L
B
2
A
3
B
2
A
3
CLK
R/L
B
3
B
3
SR2
SR3
1
S
S
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2
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µ
PD16335
V
DD2
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O
96
SRn: 32-bit shift register
V
SS2
2
Page 3
BLOCK DIAGRAM (IBS = L, 6-BIT INPUT, 16-BIT LENGTH SHIFT REGISTER)
OE
PC
µ
PD16335
BLK
LE
SR1
A
1
A
1
CLK CLK S
R/L
B
1
R/L
B
S
1
SR2
A
2
A
2
CLK S
R/L
B
2
S
B
2
SR3
A
3
A
3
CLK S
R/L
B
3
S
B
3
SR4
A
4
A
4
CLK S
R/L
B
4
S
B
4
SR5
A
5
A
5
CLK S
R/L
B
5
S
B
5
SR6
A
6
A
6
CLK S
R/L
B
6
S
B
6
V
DD2
1
S
7
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91
2
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O
96
SRn: 16-bit shift register
V
SS2
3
Page 4
PIN DESCRIPTION
Symbol Pin Name Description
PC Polarity change input PC = L: All driver output invert
BLK Blank input BLK = H: All output = H or L
LE Latch enable input Data latch by rising edge of this signal.
OE Output enable Make output high impedance by input H
A1 to A3 (6) RIGHT data input/output
B1 to B3 (6) LEFT data input/output
CLK Clock input Shift executed on fall
R/L Shift control input Right shift mode when R/L = H
IBS Input mode switch H: 32-bit length shift register, 3-bit input
O1 to O96 High withstand voltage output 80 V, +50/–75 mA MAX.
VDD1 Power supply for logic block 5 V ±10%
VDD2 Power supply for driver block 10 to 70 V
VSS1 Logic GND Connect to system GND
VSS2 Driver GND Connect to system GND
Note When input mode is 3-bit, set unused input and output pins “L” level.
Note
Note
When R/L = H (values in parentheses are for 6-bit input)
A1 to A3 (6): Input B1 to B3 (6): Output
When R/L = L (values in parentheses are for 6-bit input)
A1 to A3 (6): Output B1 to B3 (6): Input
SR1: A1 → S1 ··· S94 → B1 (Same direction for SR2 to SR6)
Left shift mode when R/L = L
SR1: B1 → S94 ··· S1 → A1 (Same direction for SR2 to SR6)
L: 16-bit length shift register, 6-bit input
µ
PD16335
TRUTH TABLE 1 (Shift Register Block)
Input Output
R/L CLK A B
H ↓ Input Output
H H or L Output Hold
L ↓ Output
L H or L Output Hold
Note 2
Note 1
Input Left shift execution
Right shift execution
Notes 1. The data of S91 to S93 (S85 to S90) shifts to S94 to S96 (S91 to S96) and is output from B1 to B3 (B1 to B6)
at the falling edge of the clock, respectively. (Values in parentheses are for 6-bit input)
2. The data of S4 to S6 (S7 to S12) shifts to S1 to S3 (S1 to S6) and is output from A1 to A3 (A1 to A6) at the
falling edge of the clock, respectively (Values in parentheses are for 6-bit input)
Shift Register
TRUTH TABLE 2 (Latch Block)
LE Output State of Latch Block (Ln)
↑ Latch Sn data
H or L Hold latch data
TRUTH TABLE 3 (Driver Block)
Ln BLK PC OE Output State of Driver Block
X H H L H (All driver outputs: H)
X H L L L (All driver outputs: L)
X L H L Output latch data (Ln)
X L L L Output inverted latch data (Ln)
X X X H Set output impedance high
X: H or L, H: High level, L: Low level
4
Page 5
TIMING CHART (WHEN IBS = “H”: 3-BIT INPUT, RIGHT SHIFT)
Values in parentheses in the following chart are when R/L = L.
CLK
A1 (B3)
A2 (B2)
A3 (B1)
S1 (S96)
S2 (S95)
S3 (S94)
S4 (S93)
µ
PD16335
S5 (S92)
S6 (S91)
LE
BLK
PC
OE
O1 (O96)
O2 (O95)
O3 (O94)
O4 (O93)
O5 (O92)
Latch by rising edge
High impedance
O6 (O91)
5
Page 6
TIMING CHART (WHEN IBS = “L”: 6-BIT INPUT, RIGHT SHIFT)
Values in parentheses in the following chart are when R/L = L.
CLK
A1 (B6)
A2 (B5)
A3 (B4)
A
4
(B3)
A5 (B2)
A6 (B1)
S1 (S96)
S2 (S95)
µ
PD16335
S3 (S94)
S4 (S93)
S5 (S92)
S6 (S91)
S7 (S90)
LE
BLK
PC
OE
O1 (O96)
O2 (O95)
Latch by rising edge
High impedance
O3 (O94)
O4 (O93)
O5 (O92)
O6 (O91)
O7 (O90)
6
Page 7
µ
PD16335
ABSOLUTE MAXIMUM RATINGS (TA = 25°C, VSS1 = VSS2 = 0 V)
Parameter Symbol Ratings Unit
Logic Block Supply Voltage VDD1 –0.5 to +7.0 V
Driver Block Supply Voltage VDD2 –0.5 to +80 V
Logic Block Input Voltage VI –0.5 to VDD1 +0.5 V
Driver Block Output Current IO2 +50/–75 mA
Junction Temperature Tj ±125 °C
Storage Temperature Tstg. –65 to +150 °C
RECOMMENDED OPERATING CONDITIONS (TA = –40 to +85°C, VSS1 = VSS2 = 0 V)
Parameter Symbol MIN. TYP. MAX. Unit
Logic Block Supply Voltage VDD1 4.5 5.0 5.5 V
Driver Block Supply Voltage VDD2 10 70 V
High-Level Input Voltage VIH 0.7 VDD1 VDD1 V
Low-Level Input Voltage VIL 0 0.2 VDD1 V
Driver Output Current IOH2 –60 mA
IOL2 +40 mA
Caution In order to prevent latch-up breakage, be sure to enter the power to VDD1, logic signal and VDD2 in
that order, and turn off the power in the reverse order, keep this order also during a transition period.
ELECTRICAL SPECIFICATIONS (TA = 25°C, VDD1 = 5.0 V, VDD2 = 70 V, VSS1 = VSS2 = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
High-Level Output Voltage VOH1 Logic, IOH1 = –1.0 mA
Low-Level Output Voltage VOL1 Logic, IOL1 = 1.0 mA 0 0.1 VDD1 V
High-Level Output Voltage VOH21 O1 to O96, IOH2 = –1.3 mA 69 V
VOH22 O1 to O96, IOH2 = –13 mA 65 V
Low-Level Output Voltage V OL21 O1 to O96, IOL2 = 5 mA 1.0 V
VOL22 O1 to O96, IOL2 = 40 mA 10 V
Input Leakage Current IIL VI = VDD1 or VSS1 ±1.0
High-Level Input Voltage VIH 0.7 VDD1 V
Low-Level Input Voltage VIL 0.2 VDD1 V
Static Current Dissipation IDD1 Logic, TA = –40 to +85° 100
IDD1 Logic, TA = 25°C10
IDD2 Driver, TA = –40 to +85° 1000
IDD2 Driver, TA = 25°C 100
0.9 VDD1
VDD1 V
µ
A
µ
A
µ
A
µ
A
µ
A
7
Page 8
µ
PD16335
SWITCHING CHARACTERISTICS (TA = 25°C, VDD1 = 5.0 V, VDD2 = 130 V, VSS1 = VSS2 = 0 V, logic CL
= 15 pF, driver CL = 50 pF, tr = tf = 6.0 ns)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Transmission Delay Time tPHL1 CLK ↓ → A/B 55 ns
tPLH1 55 ns
tPHL2 CLK ↑ (LE = H) → O1 to O96 180 ns
tPLH2 180 ns
tPHL3 BLK → O1 to O96 165 ns
tPLH3 165 ns
tPHL4 PC → O1 to O96 160 ns
tPLH4 160 ns
tPHZ OE → O1 to O96 300 ns
tPZH RL = 10 kΩ 180 ns
tPLZ 300 ns
tPZL 180 ns
Rise Time tTLH O 1 to O96 120 ns
tTLZ RL = 10 kΩ 3
tTZH O1 to O96 120 ns
Fall Time tTHL O1 to O96 150 ns
tTHZ RL = 10 kΩ 3
tTZL O1 to O96 150 ns
Maximum Clock Frequency fmax. When data is read, duty 50% 25 MHz
cascade connection, Duty 50% 16 MHz
Input Capacitance CI 15 pF
µ
s
µ
s
TIMING REQUIREMENT (TA = –40 to +85°C, VDD1 = 4.5 to 5.5 V, VSS1, 2 = 0 V, tr = tf = 6.0 ns)
Parameter Symbol Condition MIN. TYP. MAX. Unit
Clock Pulse Width PWCLK 20 ns
Latch Enable Pulse Width PWLE 20 ns
Blank Pulse Width PWBLK 200 ns
PC Pulse Width PWPC 200 ns
OE Pulse Width PWOE RL = 10 kΩ 3.3
Data Setup Time tsetup 7ns
Data Hold Time thold 10 ns
Latch Enable Time 1 tLE1 20 ns
Latch Enable Time 2 tLE2 20 ns
µ
s
8
Page 9
SWITCHING CHARACTERISTICS WAVEFORM
PWCLK (H) PWCLK (L)
CLK
tsetup thold
50% 50% 50%
1/fmax.
µ
PD16335
3.3 V
SS1
V
An/Bn
(Input)
Bn/An
(Output)
LE
CLK
50%50%
tPHL1
50% 50%
50% 50%
PWLE
tLE1 tLE2
tPLH1
3.3 V
SS1
V
VOH1
VOL1
3.3 V
SS1
V
3.3 V
50%50%
SS1
V
On
On
tPHL2
tPLH2
90%
10%
VOH2
VOL2
VOH2
VOL2
9
Page 10
BLK
PWBLK
50% 50%
µ
PD16335
3.3 V
VSS1
O
PC
On
OE
tPLH4tPHL4
50%50%
tPLH3
10%
10%
VOH2
VOL2
3.3 V
VSS1
VOH2
VOL2
3.3 V
VSS1
tPHL3
n
50% 50%
90%
PWPC
90%
PWOE
10
On
O
tPZL
90%
10%
90%
n
10%
90%
10%
tPZH tTZHtPHZ tTHZ
tTZLtPLZ tTLZ
VO (H)
10%
VOL2
VOH2
90%
VO (L)
Page 11
[MEMO]
µ
PD16335
11
Page 12
µ
PD16335
No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
this document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property
rights of third parties by or arising from use of a device described herein or any other liability arising from use
of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other
intellectual property rights of NEC Corporation or others.
While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a
customer designated "quality assurance program" for a specific application. The recommended applications of
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
Anti-radioactive design is not implemented in this product.
M4 96.5
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