PC8182TB is a silicon monolithic integrated circuit designed as amplifier for mobile communications. This
µ
IC is low current consumption and wide band than µPC2771TB.
This IC is manufactured using NEC’s 25 GHz fT UHS0 silicon bipolar process. This process uses direct silicon
nitride passivation film and gold electrodes. These materials can protect the chip surface from pollution and prevent
corrosion/migration. Thus, this IC has excellent performance, uniformity and reliability.
PC2762T2.9+8.0 @ f = 0.9 GHz13.0 @ f = 0.9 GHz26.56-pin m i ni m ol dC1Z
µ
PC2762TB+7.0 @ f = 1.9 GHz15.5 @ f = 1.9 GHz6-pin super minimold
µ
PC2763T2.7+9.5 @ f = 0.9 GHz20.0 @ f = 0.9 GHz27.06-pin m i ni m ol dC2A
µ
PC2763TB+6.5 @ f = 1.9 GHz21.0 @ f = 1.9 GHz6-pin super minimold
µ
PC2771T2.2+11.5 @ f = 0.9 GHz21.0 @ f = 0.9 GHz36.06-pin m i ni m ol dC2H
µ
PC2771TB+9.5 @ f = 1.5 GHz21.0 @ f = 1.5 GHz6-pin super minimold
µ
PC8182TB
µ
f
(GHz)
2.9+9.0 @ f = 1.9 GHz20.5 @ f = 1.9 GHz30.0C3F
+8.0 @ f = 2.4 GHz20.5 @ f = 2.4 GHz
O (1 dB)
P
(dBm)
(Bottom View)
4
5
6
out
= 3.0 V, ZS = ZL = 50
3
2
1
)
ΩΩΩΩ
G
(dB)
P
CC
I
(mA)
Pin No.Pin Name
1INPUT
2GND
3GND
4OUTPUT
5GND
6V
PackageMarking
6-pin super minimold
CC
Remark
Notice
Typical performance. Please refer to ELECTRICAL CHARACTERISTICS in detail.
The package size distinguishes between minimold and super minimold.
2
Preliminary Data Sheet P14543EJ1V0DS00
Page 3
SYSTEM APPLICATION EXAMPLE
Digital cellular telephone
µµµµ
PC8182TB
TX
SW
RX
PA
µ
PC8182TB
÷N
PLL
Phase
shifter
0 °
90 °
DEMO
PLL
I
Q
I
Q
Preliminary Data Sheet P14543EJ1V0DS00
3
Page 4
PIN EXPLANATION
µµµµ
PC8182TB
Applied
Pin No. Pin Name
1INPUT––Signal input pi n. A internal
4OUTPUTVol t age
6VCC2.7 to 3.3–Power supply pi n, whi ch biases
2
3
5
GND0–Ground pin. This pi n should be
Voltage
(V)
as same
CC
as V
through
external
inductor
Pin
Voltage
Note
(V)
–Signal output pi n. The inductor
Function and ApplicationsInternal Equivalent Circ ui t
matching circuit, configured with
resistors, enables 50
connection over a wide band.
A multi-feedback ci rcuit is
designed to cancel the
deviations of h
This pin must be coupled to
signal source with capac i t or for
DC cut.
must be attached between V
and output pins to supply
current to the internal output
transistors.
the internal input transis tor.
This pin should be externally
equipped with bypass capaci t or
to minimize its i m pedance.
connected to system ground
with minimum inductanc e.
Ground pattern on the board
should be formed as wide as
possible.
All the ground pins must be
connected together with wide
ground pattern to decrease
impedance difference.
Ω
FE
and resistance.
6
CC
4
1
3
GNDGND
52
Pin voltage is measured at V
Note
4
CC
= 3.0 V.
Preliminary Data Sheet P14543EJ1V0DS00
Page 5
ABSOLUTE MAXIMUM RATINGS
ParameterSymbolConditionsRatingsUnit
µµµµ
PC8182TB
Supply VoltageV
Total Circuit CurrentI
Power DissipationP
CC
CC
TA = +25 °C, pin 4 and 63.6V
TA = +25 °C60mA
D
Mounted on double copper clad
50 × 50 × 1.6 mm epoxy glass P WB
COMPONENTS OF TEST CIRCUITEXAMPLE OF ACTUAL APPLICATION COMPONENTS
FOR MEASURING ELECTRICAL
CHARACTERISTICS
TypeValueTypeV al ueOperating Frequency
2
C1, C
3
C
LBias Tee1 000 nH10 nH2.0 GHz or hi gher
Bias Tee1 000 pFC1 to C3Chip capacitor1 000 pF100 MHz or hi gher
Capacitor1 000 pFLChip inductor100 nH100 MHz or higher
INDUCTOR FOR THE OUTPUT PIN
The internal output transistor of this IC consumes 20 mA, to output medium power. To supply current for output
transistor, connect an inductor between the Vcc pin (pin 6) and output pin (pin 4). Select large value inductance, as
listed above.
The inductor has both DC and AC effects. In terms of DC, the inductor biases the output transistor with minimum
voltage drop to output enable high level. In terms of AC, the inductor make output-port-impedance higher to get
enough gain. In this case, large inductance and Q is suitable.
For above reason, select an inductance of 100 Ω or over impedance in the operating frequency. The gain is a
peak in the operating frequency band, and suppressed at lower frequencies.
The recommendable inductance can be chosen from example of actual application components list as shown
above.
CAPACITORS FOR THE VCC, INPUT, AND OUTPUT PINS
Capacitors of 1 000 pF are recommendable as the bypass capacitor for the Vcc pin and the coupling capacitors
for the input and output pins.
The bypass capacitor connected to the Vcc pin is used to minimize ground impedance of Vcc pin. So, stable bias
can be supplied against Vcc fluctuation.
The coupling capacitors, connected to the input and output pins, are used to cut the DC and minimize RF serial
impedance. Their capacitance are therefore selected as lower impedance against a 50 Ω load. The capacitors thus
perform as high pass filters, suppressing low frequencies to DC.
To obtain a flat gain from 100 MHz upwards, 1 000 pF capacitors are used in the test circuit. In the case of under
10 MHz operation, increase the value of coupling capacitor such as 10 000 pF. Because the coupling capacitors are
determined by equation, C = 1/(2πRfc).
Preliminary Data Sheet P14543EJ1V0DS00
7
Page 8
ILLUSTRATION OF THE TEST CIRCUIT ASSEMBLED ON EVALUATION BOARD
(1) Observe precautions for handling because of electro-static sensitive devices.
(2) Form a ground pattern as widely as possible to minimize ground impedance (to prevent undesired oscillation).
All the ground pins must be connected together with wide ground pattern to decrease impedance difference.
(3) The bypass capacitor should be attached to the VCC pin.
(4) The inductor must be attached between VCC and output pins. The inductance value should be determined in
accordance with desired frequency.
(5) The DC cut capacitor must be attached to input pin.
RECOMMENDED SOLDERING CONDITIONS
This product should be soldered under the following recommended conditions. For soldering methods and
conditions other than those recommended below, contact your NEC sales representative.
Soldering MethodSoldering ConditionsRecommended Condition Symbol
Infrared ReflowPackage peak temperature: 235 ° C or bel ow
Time: 30 seconds or less (at 210 °C)
Count: 3, Exposure limi t: None
VPSPackage peak temperature: 215 °C or below
Time: 40 seconds or less (at 200 °C)
Count: 3, Exposure limi t: None
Wave SolderingSoldering bath temperature: 260 °C or below
Time: 10 seconds or less
Count: 1, Exposure limi t: None
Partial HeatingPin temperature: 300 °C
Time: 3 seconds or less (per side of device)
Exposure limit: None
After opening the dry pack, keep it in a place below 25 °C and 65 % RH for the allowable storage period.
Note
Note
Note
Note
Note
IR35-00-3
VP15-00-3
WS60-00-1
–
Caution Do not use different soldering methods together (except for partial heating).
For details of recommended soldering conditions for surface mounting, refer to information document
• The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
• No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
this document.
• NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property
rights of third parties by or arising from use of a device described herein or any other liability arising from use
of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other
intellectual property rights of NEC Corporation or others.
• Descriptions of circuits, software, and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these circuits,
software, and information in the design of the customer's equipment shall be done under the full responsibility
of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third
parties arising from the use of these circuits, software, and information.
• While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
• NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a
customer designated "quality assurance program" for a specific application. The recommended applications of
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
M7 98. 8
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