Datasheet UPC8182TB-E3, UPC8182TB Datasheet (NEC)

Page 1
PRELIMINARY DATA SHEET
BIPOLAR ANALOG INTEGRATED CI RCUIT
PC8182TB
µµµµ
3 V, 2.9 GHz SILICON MMIC
MEDIUM OUTPUT POWER AMPLIFIER
FOR MOBILE COMMUNICATIONS
DESCRIPTION
The
PC8182TB is a silicon monolithic integrated circuit designed as amplifier for mobile communications. This
µ
IC is low current consumption and wide band than µPC2771TB.
This IC is manufactured using NEC’s 25 GHz fT UHS0 silicon bipolar process. This process uses direct silicon nitride passivation film and gold electrodes. These materials can protect the chip surface from pollution and prevent corrosion/migration. Thus, this IC has excellent performance, uniformity and reliability.
FEATURES
• High-density surface mounting : 6-pin super minimold package (2.0 × 1.25 × 0.9 mm)
• Supply voltage : VCC = 2.7 to 3.3 V
• Circuit current : ICC = 30 mA TYP. @ VCC = 3.0 V
• Medium output power : P
• Power gain : GP = 21.5 dB TYP. @ f = 0.9 GHz
• Upper limit operating frequency : fu = 2.9 GHz TYP. @ 3 dB bandwidth
O(1dB)
= +9.5 dBm TYP. @ f = 0.9 GHz
O(1dB)
P
= +9.0 dBm TYP. @ f = 1.9 GHz
O(1dB)
P
= +8.0 dBm TYP. @ f = 2.4 GHz
GP = 20.5 dB TYP. @ f = 1.9 GHz GP = 20.5 dB TYP. @ f = 2.4 GHz
APPLICATION
• Buffer amplifiers on 1.9 GHz to 2.4 GHz mobile communications system.
ORDERING INFORMATION
Part Number Package Marking Supplying Form
µ
PC8182TB-E3 6-pin super minimold C3F Embossed tape 8 mm wide.
1, 2, 3 pins face to perforat i on side of the tape. Qty 3 kp/reel.
Remark
To order evaluation samples, please contact your local NEC sales office.
(Part number for sample order:
Caution Electro-static sensitive devices
The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for availability and additional information.
PC8182TB)
µ
©
1999
Page 2
PIN CONNECTIONS
µµµµ
PC8182TB
(Top View)
3
2
1
4
5
6
C3F
PRODUCT LINE-UP (TA = +25 °C, VCC = V
u
Part No.
PC2762T 2.9 +8.0 @ f = 0.9 GHz 13.0 @ f = 0.9 GHz 26.5 6-pin m i ni m ol d C1Z
µ
PC2762TB +7.0 @ f = 1.9 GHz 15.5 @ f = 1.9 GHz 6-pin super minimold
µ
PC2763T 2.7 +9.5 @ f = 0.9 GHz 20.0 @ f = 0.9 GHz 27.0 6-pin m i ni m ol d C2A
µ
PC2763TB +6.5 @ f = 1.9 GHz 21.0 @ f = 1.9 GHz 6-pin super minimold
µ
PC2771T 2.2 +11.5 @ f = 0.9 GHz 21.0 @ f = 0.9 GHz 36.0 6-pin m i ni m ol d C2H
µ
PC2771TB +9.5 @ f = 1.5 GHz 21.0 @ f = 1.5 GHz 6-pin super minimold
µ
PC8182TB
µ
f
(GHz)
2.9 +9.0 @ f = 1.9 GHz 20.5 @ f = 1.9 GHz 30.0 C3F +8.0 @ f = 2.4 GHz 20.5 @ f = 2.4 GHz
O (1 dB)
P
(dBm)
(Bottom View)
4
5
6
out
= 3.0 V, ZS = ZL = 50
3
2
1
)
ΩΩΩΩ
G
(dB)
P
CC
I
(mA)
Pin No. Pin Name
1 INPUT 2GND 3GND 4OUTPUT 5GND 6V
Package Marking
6-pin super minimold
CC
Remark
Notice
Typical performance. Please refer to ELECTRICAL CHARACTERISTICS in detail.
The package size distinguishes between minimold and super minimold.
2
Preliminary Data Sheet P14543EJ1V0DS00
Page 3
SYSTEM APPLICATION EXAMPLE
Digital cellular telephone
µµµµ
PC8182TB
TX
SW
RX
PA
µ
PC8182TB
÷N
PLL
Phase shifter
0 °
90 °
DEMO
PLL
I
Q
I
Q
Preliminary Data Sheet P14543EJ1V0DS00
3
Page 4
PIN EXPLANATION
µµµµ
PC8182TB
Applied
Pin No. Pin Name
1 INPUT Signal input pi n. A internal
4 OUTPUT Vol t age
6VCC2.7 to 3.3 Power supply pi n, whi ch biases
2 3 5
GND 0 Ground pin. This pi n should be
Voltage
(V)
as same
CC
as V through external inductor
Pin Voltage
Note
(V)
Signal output pi n. The inductor
Function and Applications Internal Equivalent Circ ui t
matching circuit, configured with resistors, enables 50 connection over a wide band. A multi-feedback ci rcuit is designed to cancel the deviations of h This pin must be coupled to signal source with capac i t or for DC cut.
must be attached between V and output pins to supply current to the internal output transistors.
the internal input transis tor. This pin should be externally equipped with bypass capaci t or to minimize its i m pedance.
connected to system ground with minimum inductanc e. Ground pattern on the board should be formed as wide as possible. All the ground pins must be connected together with wide ground pattern to decrease impedance difference.
FE
and resistance.
6
CC
4
1
3
GND GND
52
Pin voltage is measured at V
Note
4
CC
= 3.0 V.
Preliminary Data Sheet P14543EJ1V0DS00
Page 5
ABSOLUTE MAXIMUM RATINGS
Parameter Symbol Conditions Ratings Unit
µµµµ
PC8182TB
Supply Voltage V Total Circuit Current I Power Dissipation P
CC
CC
TA = +25 °C, pin 4 and 6 3.6 V TA = +25 °C60mA
D
Mounted on double copper clad 50 × 50 × 1.6 mm epoxy glass P WB
(T Operating Ambient Temperature T Storage Temperature T Input Power P
A
stg
in
TA = +25 °C +10 dBm
RECOMMENDED OPERATING CONDITIONS
Parameter Symbol MIN. TYP. MAX. Unit Remark
Supply Voltage V
Operating Ambient Temperature T
CC
A
200 mW
A
= +85 °C)
40 to +85
55 to +150
C
°
C
°
2.7 3.0 3.3 V Same voltage should be applied to pin 4 and 6.
40 +25 +85 °C
Preliminary Data Sheet P14543EJ1V0DS00
5
Page 6
µµµµ
PC8182TB
ELECTRICAL CHARACTERISTICS (TA = +25 °C, VCC = V
Parameter Symbol Test Conditions MIN. TYP. MAX. Unit
O (1dB)
P
O (sat)
CC
No signal 22.0 30. 0 38.0 mA
P
f = 0.9 GHz f = 1.9 GHz f = 2.4 GHz
f = 1.9 GHz f = 2.4 GHz
u
3 dB down below from gain at f = 0.1 GHz 2.8 2.9
f = 1.9 GHz f = 2.4 GHz
in
f = 0.9 GHz f = 1.9 GHz f = 2.4 GHz
out
f = 0.9 GHz f = 1.9 GHz f = 2.4 GHz f = 0.9 GHz f = 1.9 GHz f = 2.4 GHz f = 0.9 GHz, Pin = −5 dBm
in
f = 1.9 GHz, P f = 2.4 GHz, P
= −5 dBm
in
= −5 dBm
Circuit Current I Power Gain G
Noise Figure NF f = 0.9 GHz
Upper Limit Operating Frequency f Isolation ISL f = 0.9 GHz
Input Return Loss RL
Output Return Loss RL
1 dB Gain Compression Output Level
Saturated Output Power Level P
out
= 3.0 V, ZS = ZL = 50
)
ΩΩΩΩ
19.0
17.5
18.0
30 27 28
6 8 9 8 9
11 +7.5 +7.0 +5.5
21.5
20.5
20.5
4.5
4.5
5.0
33 32 31
8 10 12 10 11 14
+9.5 +9.0
+8.0 +10.5 +10.0
+9.5
25.0
23.5
24.0
6.0
6.0
6.5
dB
dB
GHz
dB
dB
dB
dBm
dBm
6
Preliminary Data Sheet P14543EJ1V0DS00
Page 7
TEST CIRCUIT
1 000 pF
3
C
µµµµ
PC8182TB
V
CC
1
C
1 000 pF
6
1
2, 3, 5
4
L
C
2
1 000 pF
50 50
OUTIN
COMPONENTS OF TEST CIRCUIT EXAMPLE OF ACTUAL APPLICATION COMPONENTS FOR MEASURING ELECTRICAL CHARACTERISTICS
Type Value Type V al ue Operating Frequency
2
C1, C
3
C
L Bias Tee 1 000 nH 10 nH 2.0 GHz or hi gher
Bias Tee 1 000 pF C1 to C3Chip capacitor 1 000 pF 100 MHz or hi gher
Capacitor 1 000 pF L Chip inductor 100 nH 100 MHz or higher
INDUCTOR FOR THE OUTPUT PIN
The internal output transistor of this IC consumes 20 mA, to output medium power. To supply current for output transistor, connect an inductor between the Vcc pin (pin 6) and output pin (pin 4). Select large value inductance, as listed above.
The inductor has both DC and AC effects. In terms of DC, the inductor biases the output transistor with minimum voltage drop to output enable high level. In terms of AC, the inductor make output-port-impedance higher to get enough gain. In this case, large inductance and Q is suitable.
For above reason, select an inductance of 100 Ω or over impedance in the operating frequency. The gain is a peak in the operating frequency band, and suppressed at lower frequencies.
The recommendable inductance can be chosen from example of actual application components list as shown above.
CAPACITORS FOR THE VCC, INPUT, AND OUTPUT PINS
Capacitors of 1 000 pF are recommendable as the bypass capacitor for the Vcc pin and the coupling capacitors for the input and output pins.
The bypass capacitor connected to the Vcc pin is used to minimize ground impedance of Vcc pin. So, stable bias can be supplied against Vcc fluctuation.
The coupling capacitors, connected to the input and output pins, are used to cut the DC and minimize RF serial impedance. Their capacitance are therefore selected as lower impedance against a 50 Ω load. The capacitors thus perform as high pass filters, suppressing low frequencies to DC.
To obtain a flat gain from 100 MHz upwards, 1 000 pF capacitors are used in the test circuit. In the case of under 10 MHz operation, increase the value of coupling capacitor such as 10 000 pF. Because the coupling capacitors are determined by equation, C = 1/(2πRfc).
Preliminary Data Sheet P14543EJ1V0DS00
7
Page 8
ILLUSTRATION OF THE TEST CIRCUIT ASSEMBLED ON EVALUATION BOARD
AMP-2
Top View
321
C3F
Mounting direction
456
IN OUT
CC
L
V
CC
C
µµµµ
PC8182TB
COMPONENT LIST
C 1 000 pF
L Example: 10 nH
Value
Notes
1.
30 × 30 × 0.4 mm double sided copper clad polyimide board.
2.
Back side: GND pattern
3.
Solder plated on pattern
4.
: Through holes
8
Preliminary Data Sheet P14543EJ1V0DS00
Page 9
PACKAGE DIMENSIONS
6 PIN SUPER MINIMOLD (UNIT: mm)
µµµµ
PC8182TB
0.22 ±0.1 0.13
0.1 MIN.
2.1 ±0.1
1.25 ±0.1
0.65 0.65
1.3
2.0 ±0.2
0.9 ±0.1
0.7
+0.1 –0.02
0 to 0.1
Preliminary Data Sheet P14543EJ1V0DS00
9
Page 10
µµµµ
PC8182TB
NOTES ON CORRECT USE
(1) Observe precautions for handling because of electro-static sensitive devices. (2) Form a ground pattern as widely as possible to minimize ground impedance (to prevent undesired oscillation).
All the ground pins must be connected together with wide ground pattern to decrease impedance difference. (3) The bypass capacitor should be attached to the VCC pin. (4) The inductor must be attached between VCC and output pins. The inductance value should be determined in
accordance with desired frequency. (5) The DC cut capacitor must be attached to input pin.
RECOMMENDED SOLDERING CONDITIONS
This product should be soldered under the following recommended conditions. For soldering methods and
conditions other than those recommended below, contact your NEC sales representative.
Soldering Method Soldering Conditions Recommended Condition Symbol
Infrared Reflow Package peak temperature: 235 ° C or bel ow
Time: 30 seconds or less (at 210 °C) Count: 3, Exposure limi t: None
VPS Package peak temperature: 215 °C or below
Time: 40 seconds or less (at 200 °C) Count: 3, Exposure limi t: None
Wave Soldering Soldering bath temperature: 260 °C or below
Time: 10 seconds or less Count: 1, Exposure limi t: None
Partial Heating Pin temperature: 300 °C
Time: 3 seconds or less (per side of device) Exposure limit: None
After opening the dry pack, keep it in a place below 25 °C and 65 % RH for the allowable storage period.
Note
Note
Note
Note
Note
IR35-00-3
VP15-00-3
WS60-00-1
Caution Do not use different soldering methods together (except for partial heating).
For details of recommended soldering conditions for surface mounting, refer to information document
SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY MANUAL (C10535E)
.
10
Preliminary Data Sheet P14543EJ1V0DS00
Page 11
[MEMO]
µµµµ
PC8182TB
Preliminary Data Sheet P14543EJ1V0DS00
11
Page 12
µµµµ
PC8182TB
ATTENTION
OBSERVE PRECAUTIONS
FOR HANDLING
ELECTROSTATIC
SENSITIVE
DEVICES
The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.
No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others.
Descriptions of circuits, software, and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software, and information in the design of the customer's equipment shall be done under the full responsibility of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits, software, and information.
While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features.
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M7 98. 8
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