1.2W fully differential audio power amplifier
with selectable standby and 6db fixed gain
■ Differential inputs
■ 90dB PSRR @ 217Hz with grounded inputs
■ Operating from Vcc = 2.5V to 5.5V
■ 1.2W rail to rail output power @ Vcc=5V,
THD+N=1%, F=1kHz, with 8Ω load
■ 6dB integrated fixed gain
■ Ultra-low consumption in standby mode (10nA)
■ Selectable standby mode (active low or active
high)
■ Ultra-fast startup time: 10ms typ. at Vcc=3.3V
■ Available in 9-bump flip-chip (300mm bump
diameter)
■ Ultra-low pops&clicks
Description
The TS4995 is an audio power amplifier capable
of delivering 1.2W of continuous RMS output
power into an 8Ω load at 5V. Thanks to its
differential inputs, it exhibits outstanding noise
immunity.
An external standby mode control reduces the
supply current to less than 10nA. A STBY MODE
pin allows the standby pin to be active HIGH or
LOW. An internal thermal shutdown protection is
also provided, making the device capable of
sustaining short-circuits.
The TS4995 features an internal fixed gain at 6dB
which reduces the number of external
components on the application board.
TS4995 - Flip-Chip9
Pin connections (top view)
Gnd
Gnd
V
V
BypassStdby
BypassStdby
V
V
765
765
O-
O-
8
8
IN+
IN+
1
1
9
9
2
2
V
V
CC
CC
V
V
O+
O+
4
4
V
V
3
3
IN-
IN-
Stdby Mode
Stdby Mode
The device is equipped with Common Mode
Feedback circuitry allowing outputs to be always
biased at Vcc/2 regardless of the input common
mode voltage.
The TS4995 has been designed for high quality
audio applications such as mobile phones and
requires few external components.
Applications
■ Mobile phones (cellular / cordless)
■ PDAs
■ Laptop / notebook computers
■ Portable audio devices
Device summary table
Part NumberTemperature RangePackagePackingMarking
TS4995EIJT-40°C to +85°CLead free flip-chip9Tape & Reel95
Figure 44. Frequency responseFigure 45. Frequency response
8
7
6
5
4
3
Gain (dB)
2
1
0
20
Cin=4.7µF
Cin=330n F
Vcc = 3.3V
Gain = 6dB
ZL = 8Ω + 500pF
Tamb = 25°C
100100010000
Frequency (Hz)
Figure 46. SNR vs. power supply voltage
with unweighted filter
120
F = 1kHz
118
G = 6dB
Cb = 1µF
116
THD + N < 0.7%
114
Tamb = 25°C
112
110
108
106
104
Signal to Noise Ratio (dB)
102
100
2.53.03.54.04.55.05.5
RL=16
Ω
Power Supply Voltage (V)
RL=8
Ω
20k
8
7
6
5
4
3
Gain (dB)
2
1
0
20
Cin=4.7µF
Cin=330n F
Vcc = 2.6V
Gain = 6dB
ZL = 8Ω + 500pF
Tamb = 25°C
100100010000
Frequency (Hz)
Figure 47. SNR vs. power supply voltage
with A-weighted filter
120
F = 1kHz
118
G = 6dB
Cb = 1µF
116
THD + N < 0.7%
114
Tamb = 25°C
112
RL=8
110
108
106
104
Signal to Noise Ratio (dB)
102
100
2.53.03.54.04.55.05.5
RL=16
Ω
Power Supply Voltage (V)
Ω
20k
Figure 48. Power derating curves
1.2
1.0
0.8
0.6
0.4
No Heat sink
0.2
Flip-Chip Package Power Dissipation (W)
0.0
0 255075100125
Heat sink surface ≈ 100mm
Ambiant Temperature (°C)
2
15/24
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Application informationTS4995
4 Application information
4.1 Differential configuration principle
The TS4995 is a monolithic full-differential input/ output power amplifier with fixed +6 dB gain. The
TS4995 also includes a common mode feedback loop that controls the output bias value to average it at
Vcc/2 for any DC common mode input voltage. This allows maximum output voltage swing, and therefore,
maximize the output power. Moreover, as the load is connected differentially instead of single-ended,
output power is four times higher for the same power supply voltage.
The advantages of a full-differential amplifier are:
●very high PSRR (Power Supply Rejection Ratio),
●high common mode noise rejection,
●virtually no pops&clicks without additional circuitry, giving a faster start-up time compared
to conventional single-ended input amplifiers,
●easier interfacing with differential output audio DAC,
●no input coupling capacitors required thanks to common mode feedback loop.
In theory, the filtering of the internal bias by an external bypass capacitor is not necessary. However to
reach maximum performance in all tolerance situations, it is recommended to keep this option.
4.2 Common mode feedback loop limitations
As explained previously, the common mode feedback loop allows the output DC bias voltage to be
averaged at Vcc/2 for any DC common mode bias input voltage.
Due to VIC limitation of the input stage (see
Table 4 on page 5
), the common mode feedback loop can
ensure its role only within defined range.
4.3 Low frequency response
The input coupling capacitors block the input signal DC part at the amplifier inputs. Cin and Rin form a
first-order high pass filter with -3 dB cut-off frequency.
1
=
F
CL
××π×
CR2
Note:The Input impedance for the TS4995 is typically 20 kΩ and there is tolerance around this
value.
From
Figure 49
, one can easily establish the Cin value required for a -3 dB cut-off frequency.
)Hz(
inin
16/24
Page 17
TS4995Application information
Figure 49. -3dB lower cut-off frequency vs. input capacitance
All gain se tting
100
Typical Input
Impedance
10
Low -3dB Cut Off Frequency (Hz)
0.1
Maximum Input
Impedance
Input C apacito r Cin (µF)
Tamb=25°C
Minimum Input
Impedance
0.51
4.4 Power dissipation and efficiency
Assumptions:
●load voltage and current are sinusoidal (V
●supply voltage is a pure DC source (V
Regarding the load we have:
V
= V
PEAK
out
and
I
=
out
and
V
P
=
---------------------- (W )
out
Therefore, the average current delivered by the supply voltage is:
I
CC
= 2
AVG
The power delivered by the supply voltage is:
P
= Vcc Icc
supply
Then, the power dissipated by each amplifier is
P
diss
= P
supply
- P
out
(W)
P
diss
22V
----------------------
π R
out
)
cc
sin ωt (V)
V
out
-------------- ( A )
L
R
2
PEAK
2R
L
V
PEAK
-------------------- (A)
πR
AVG
CC
P
outPout
L
and I
L
(W)
–=
out
)
17/24
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Application informationTS4995
and the maximum value is obtained when:
∂Pdiss
---------------------- = 0
∂P
out
and its value is:
2
Vcc2
maxPdiss
=
π
)W(
2
R
L
Note:This maximum value is only dependent on power supply voltage and load values.
The efficiency is the ratio between the output power and the power supply
η =
P
out
--------------------- =
P
supply
PEAK
π V
----------------------4VCC
The maximum theoretical value is reached when Vpeak = Vcc, so
π
----- = 78.5%
4
The maximum die temperature allowable for the TS4995 is 125°C. However, in case of overheating, a
thermal shutdown set to 150°C, puts the TS4995 in standby until the temperature of the die is reduced by
about 5°C.
To calculate the maximum ambient temperature T
●power supply voltage value, Vcc
●load resistor value, RL
●the package type, RTH
Example: Vcc=5V, RL=8Ω, RTH
We calculate P
dissmax
= 633mW.
JA
Flip-Chip=100°C/W (100mm2 copper heatsink).
JA
allowable, we need to know:
AMB
with
)C(PRTHC125T
°×−°=
dissJAAMB
= 125-100x0.633=61.7°C
T
AMB
4.5 Decoupling of the circuit
Two capacitors are needed to correctly bypass the TS4995: a power supply bypass capacitor CS and a
bias voltage bypass capacitor C
Capacitor C
has particular influence on THD+N at high frequency (above 7kHz) and an indirect
S
influence on power supply disturbances. With a value for C
similar to that shown in the datasheet.
In the high frequency region, if C
power supply rail are less filtered.
.
B
of 1µF, one can expect THD+N performance
S
is lower than 1µF, then THD+N increases and disturbances on the
S
On the other hand, if C
is larger than 1µF, then those disturbances on the power supply rail are more
S
filtered.
Capacitor C
has an influence on THD+N at lower frequencies, but also impacts PSRR performance
b
(with grounded input and in the lower frequency region).
18/24
Page 19
TS4995Application information
4.6 Wake-up Time: T
WU
When the standby is released to put the device ON, the bypass capacitor Cb will not be charged
immediately. As C
voltage is correct. The time to reach this voltage is called the wake-up time or T
Table 4 on page 5
is directly linked to the bias of the amplifier, the bias will not work properly until the Cb
b
and is specified in
WU
, with Cb=1µF. During the wake-up time phase, the TS4995 gain is close to zero. After
the wake-up time period, the gain is released and set to its nominal value.
has a value different than 1µF, then refer to the graph in
If C
b
Figure 50
to establish the corresponding
wake-up time value.
Figure 50. Startup time vs. bypass capacitor
15
Tamb=25°C
10
5
Startup Time (ms)
Vcc=2.6V
0
0.00.4 0.81.21.62.0
Vcc=5V
Vcc= 3.3V
Bypass Capac itor Cb (µF)
4.7 Shutdown time
When the standby command is set, the time required to put the two output stages in high impedance and
the internal circuitry in shutdown mode is a few microseconds.
Note:In shutdown mode, the Bypass pin and Vin+, Vin- pins are shorted to ground by internal
switches. This allows a quick discharge of C
and Cin.
b
4.8 Pop performance
In theory, due to a fully differential structure, the TS4995 pop performance should be perfect. However,
due to R
, R
in
, and Cin mismatching, some startup noise could remain. In the TS4995 a built-in pop
feed
reduction circuitry allows to reach the theoretical pop (with mismatched components). With this circuitry,
the TS4995 is close to zero pop for all common applications possible.
In addition, when the TS4995 is set in standby, due to the high impedance output stage configuration in
this mode, no pop is possible.
4.9 Single-ended input configuration
It is possible to use the TS4995 in a single-ended input configuration. However, input coupling capacitors
are needed in this configuration. The schematic in
Figure 51
shows this configuration as example.
19/24
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Application informationTS4995
Figure 51. Typical single-ended input application
VCC
Cs1
1uF
2
TS4995
Ve
P1
Cin1
330nF
Cin2
330nF
Cbypass1
1uF
3
1
8
VCC
Vin-
Vin+
BYP ASS
3
STD BY
2
1
BIAS
STB Y
4
STDBY / Operation
Vcc
STD BY MODE
9
2
3
1
+
STDBY MODE
TS4995 FlipChip
Vo -
Vo+
GND
6
7
5
8 Ohms
20/24
Page 21
TS4995Package mechanical data
5 Package mechanical data
To meet environmental requirements, STMicroelectronics offers these devices in ECOPACK
®
packages.
These packages have a lead-free second level interconnect. The category of second level interconnect is
marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The
maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an
STMicroelectronics trademark. ECOPACK specifications are available at: www.st.com
Figure 52. Pin out (top view)Figure 53. Marking (top view)
Gnd
Gnd
E
V
V
BypassStdby
BypassStdby
V
V
765
765
O-
O-
8
8
IN+
IN+
1
1
4
4
9
9
2
2
3
3
V
V
CC
CC
Stdby Mode
Stdby Mode
– Balls are underneath
V
V
O+
O+
95
A94
V
V
IN-
IN-
A94
YWW
YWW
E
22/24
Page 23
TS4995Revision history
6 Revision history
Table 7.Document revision history
DateRevisionChanges
June 20061Final datasheet.
23/24
Page 24
TS4995
y
y
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