Datasheet TP3076N-G Datasheet (NATIONAL SEMICONDUCTOR)

TP3076
COMBO

®

II Programmable PCM CODEC/Filter for ISDN

and Digital Phone Applications

General Description

The TP3076 is a second-generation combined PCM CODEC
and Filter devices optimized for digital switching applications
on subscriber line and trunk cards and digital phone applica­tions. Using advanced switched capacitor techniques,
COMBO II combines transmit bandpass and receive low­pass channel filters with a companding PCM encoder and
decoder. The devices are A-law and µ-law selectable and
employ a conventional serial PCM interface capable of being
clocked up to 4.096 MHz. A number of programmable func­tions may be controlled via a serial control port.

Channel gains are programmable over a 25.4 dB range in
each direction.

To enable COMBO II to interface to the SLIC control leads, a
number of programmable latches are included; each may be
configured as either an input or an output. The TP3076 pro­vides 4 latches.

Features

n Complete CODEC and Filter system including:

— Transmit and receive PCM channel filters
— µ-law or A-law companding coder and decoder
— Receive power amplifier drives 300Ω
— 4.096 MHz serial PCM data (max)

n Programmable functions:

— Transmit gain: 25.4 dB range, 0.1 dB steps
— Receive gain: 25.4 dB range, 0.1 dB steps
— Time-slot assignment; to 64 slots/frame
— 4 interface latches
— A or µ-law
— Analog loopback
— Digital loopback

n Direct interface to solid-state SLICs
n Standard serial control interface
n 80 mW operating power (typ)
n 1.5 mW standby power (typ)
n Designed for CCITT and LSSGR specifications
n TTL and CMOS compatible digital interfaces

Note: See also AN-614 COMBO II application guide.

Block Diagram

TRI-STATE®and COMBO®are registered trademarks of National Semiconductor Corporation.
MICROWIRE/PLUS

™

is a trademark of National Semiconductor Corporation.

DS009758-1

FIGURE 1.

April 1994

TP3076 COMBO II Programmable PCM CODEC/Filter for ISDN and Digital Phone Applications

© 1999 National Semiconductor Corporation DS009758 www.national.com

Connection Diagram

Pin Descriptions

Pin Description

V

CC

+5V±5%power supply.

V

BB

−5V±5%power supply.

GND Ground. All analog and digital signals are

referenced to this pin.

FS

X

Transmit Frame Sync input. Normally a pulse
or squarewave with an 8 kHz repetition rate is
applied to this input to define the start of the
transmit time slot assigned to this device
(non-delayed data timing mode), or the start of
the transmit frame (delayed data timing mode
using the internal time-slot assignment
counter).

FS

R

Receive Frame Sync input. Normally a pulse
or squarewave with an 8 kHz repetition rate is
applied to this input to define the start of the
receive time slot assigned to this device
(non-delayed data timing mode), or the start of
the receive frame (delayed data timing mode
using the internal time-slot assignment
counter).

BCLK Bit clock input used to shift PCM data into and

out of the D

R

and DXpins. BCLK may vary
from 64 kHz to 4.096 MHz in 8 kHz
increments, and must be synchronous with
MCLK.

MCLK Master clock input used by the switched

capacitor filters and the encoder and decoder
sequencing logic. Must be 512 kHz,

1.536/1.544 MHz, 2.048 MHz or 4.096 MHz
and synchronous with BCLK.

VF

X

I The Transmit analog high-impedance input.

Voice frequency signals present on this input
are encoded as an A-law or µ-law PCM bit
stream and shifted out on the selected D

X

pin.

VF

R

O The Receive analog power amplifier output,

capable of driving load impedances as low as
300Ω (depending on the peak overload level
required). PCM data received on the assigned
D

R

pin is decoded and appears at this output

as voice frequency signals.

Pin Description

D

X

1 This transmit data TRI-STATE®output

remains in the high impedance state except
during the assigned transmit time slot on the
assigned port, during which the transmit PCM
data byte is shifted out on the rising edges of
BCLK.

TS

X

1 Normally this open drain output is floating in a

high impedance state except when a time-slot
is active on the D

X

output, when the TSX1
output pulls low to enable a backplane
line-driver.

D

R

1 This receive data input is inactive except

during the assigned receive time slot of the
assigned port when the receive PCM data is
shifted in on the falling edges of BCLK.

CCLK Control Clock input. This clock shifts serial

control information into CI or out from CO
when the CS input is low, depending on the
current instruction. CCLK may be
asynchronous with the other system clocks.

CI Control Data Input pin. Serial control

information is shifted into COMBO II on this
pin when CS is low. Byte 1 of control
information is always written into COMBO II,
while the direction of byte 2 data is
determined by bit 2 of byte 1, as defined in

Table 1

.

CO Control Data Output pin. Serial control or

status information is shifted out of COMBO II
on this pin when CS is low.

CS Chip Select input. When this pin is low, control

information can be written to or read from
COMBO II via CI or CO.

IL3–IL0 Each Interface Latch I/O pin may be

individually programmed as an input or an
output determined by the state of the
corresponding bit in the Latch Direction
Register (LDR). For pins configured as inputs,
the logic state sensed on each input is latched
into the Interface Latch Register (ILR)
whenever control data is written to COMBO II,
while CS is low, and the information is shifted
out on the CO pin. When configured as
outputs, control data written into the ILR
appears at the corresponding IL pins.

Functional Description

POWER-ON INITIALIZATION

When power is first applied, power-on reset circuitry initial­izes the COMBO II and puts it into the power-down state.
The gain control registers for the transmit and receive gain
sections are programmed for no output, the power amp is
disabled and the device is in the non-delayed timing mode.
The Latch Direction Register (LDR) is pre-set with all IL pins
programmed as inputs, placing the SLIC interface pins in a
high impedance state. The CO pin is in TRI-STATE condi­tion. Other initial states in the Control Register are indicated
in Section 2.0.

DS009758-4

Order Number TP3076J

See NS Package Number J20A

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Functional Description (Continued)

The desired modes for all programmable functions may be
initialized via the control port prior to a Power-up command.

POWER-DOWN STATE

Following a period of activity in the powered-up state the
power-down state may be re-entered by writing any of the
control instructions into the serial control port with the “P” bit
set to “1” as indicated in

Table1

. It is recommended that the
chip be powered down before writing any additional instruc­tions. In the power-down state, all non-essential circuitry is
de-activated and the D

X

1 output is in the high impedance

TRI-STATE condition.
The data stored in the Gain Control registers, the LDR and

ILR, and all control bits remain unchanged in the
power-down state unless changed by writing new data via
the serial control port, which remains active. The outputs of
the Interface Latches also remain active, maintaining the
ability to monitor and control the SLIC.

TRANSMIT FILTER AND ENCODER

The Transmit section input, VF

X

I, is a high impedance input.
No external components are necessary to set the gain. Fol­lowing this is a programmable gain/attenuation amplifier
which is controlled by the contents of the Transmit Gain Reg­ister (see Programmable Functions section). An active
pre-filter then precedes the 3rd order high-pass and 5th or-

der low-pass switched capacitor filters. The A/D converter
has a compressing characteristic according to the standard
CCITT A or µ255 coding laws, which must be selected by a
control instruction during initialization (see

Table1

and

Table

2

). A precision on-chip voltage reference ensures accurate
and highly stable transmission levels. Any offset voltage aris­ing in the gain-set amplifier, the filters or the comparator is
canceled by an internal auto-zero circuit.

Each encode cycle begins immediately following the as­signed Transmit time-slot. The total signal delay referenced
to the start of the time-slot is approximately 165 µs (due to
the Transmit Filter) plus 125 µs (due to encoding delay),
which totals 290 µs. Data is shifted out on D

X

1 during the se-

lected time slot on eight rising edges of BCLK.

DECODER AND RECEIVER FILTER

PCM data is shifted into the Decoder’s Receive PCM Regis­ter via the D

R

1 pin during the selected time-slot on the 8 fall­ing edges of BCLK. The Decoder consists of an expanding
DAC with either A or µ255 law decoding characteristic, which
is selected by the same control instruction used to select the
Encode law during initialization. Following the Decoder is a
5th order low-pass switched capacitor filter with integral Sin
x/x correction for the 8 kHz sample and hold. A program­mable gain amplifier, which must be set by writing to the Re­ceive Gain Register, is included, and finally a Power Ampli­fier capable of driving a 300Ω load to

±

3.5V,a 600Ω load to

±

3.8V or a 15 kΩ load to±4.0V at peak overload.

TABLE 1. Programmable Register Instructions

Function Byte 1 (Notes 1, 2, 3) Byte 2 (Note 1)

7654321076543210

Single Byte Power-Up/Down PXXXXX0X None
Write Control Register P 000001X See

Table 2

Read-Back Control Register P 000011X See

Table 2

Write to Interface Latch Register P 000101X See

Table 4

Read Interface Latch Register P 000111X See

Table 4

Write Latch Direction Register P 001001X See

Table 3

Read Latch Direction Register P 001011X See

Table 3

Write Receive Gain Register P 010001X See

Table 8

Read Receive Gain Register P 010011X See

Table 8

Write Transmit Gain Register P 010101X See

Table 7

Read Transmit Gain Register P 010111X See

Table 7

Write Receive Time-Slot/Port P 100101X See

Table 6

Read-Back Receive Time-Slot/Port P 100111X See

Table 6

Write Transmit Time-Slot/Port P 101001X See

Table 6

Read-Back Transmit Time-Slot/Port P 101011X See

Table 6

Note 1: Bit 7 of bytes 1 and 2 is always the first bit clocked into or out from the CI or CO pin. X=don’t care.
Note 2: “P” is the power-up/down control bit, see Power-up/Down Control section. (“0”=Power Up, “1”=Power Down)
Note 3: Other register address codes are invalid and should not be used.

A decode cycle begins immediately after the assigned re­ceive timeslot, and 10 µs later the Decoder DAC output is
updated. The total signal delay is 10 µs plus 120 µs (filter de­lay) plus 62.5 µs (

1

⁄2frame) which gives approximately 190

µs.

PCM INTERFACE

The FS

X

and FSRframe sync inputs determine the begin­ning of the 8-bit transmit and receive time-slots respectively.
They may have any duration from a single cycle of BCLK
HIGH to one MCLK period LOW. Two different relationships
may be established between the frame sync inputs and the
actual time-slots on the PCM busses by setting bit 3 in the
Control Register (see

Table 2

). Non-delayed data mode is

similar to long-frame timing on the TP3050/60 series of de-

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Functional Description (Continued)

vices (COMBO); time-slots begin nominally coincident with
the rising edge of the appropriate FS input. The alternative is
to use Delayed Data mode, which is similar to shortframe
sync timing on COMBO, in which each FS input must be high
at least a half-cycle of BCLK earlier than the timeslot. The
Time-SlotAssignment circuit on the device can only be used
with Delayed Data timing.

When using Time-Slot Assignment, the beginning of the first
time-slot in a frame is identified by the appropriate FS input.
The actual transmit and receive time-slots are then deter­mined by the internal Time-Slot Assignment counters.

Transmit and Receive frames and time-slots may be skewed
from each other by any number of BCLK cycles. During each
assigned Transmit time-slot, the D

X

1 output shifts data out

from the PCM register on the rising edges of BCLK. TS

X

1
also pulls low for the first 71⁄2bit times of the time-slot to con­trol the TRI-STATE Enable of a backplane line-driver. Serial
PCM data is shifted into the D

R

1 input during each assigned

Receive time-slot on the falling edges of BCLK.

SERIAL CONTROL PORT

Control information and data are written into or read-back
from COMBO II via the serial control port consisting of the
control clock CCLK, the serial data input, CI, and output, CO,
and the Chip Select input, CS. All control instructions require
2 bytes, as listed

Table1

, with the exception of a single byte
power-up/down command. The Byte 1 bits are used as fol­lows: bit 7 specifies power up or power down; bits 6, 5, 4 and
3 specify the register address, bit 2 specifies whether the in­struction is read or write; bit 1 specifies a one or two byte in­struction; and bit 0 is not used.

To shift control data into COMBO II, CCLK must be pulsed
high 8 times while CS is low. Data on the CI input is shifted
into the serial input register on the falling edge of each CCLK
pulse. After all data is shifted in, the contents of the input
shift register are decoded, and may indicate that a 2nd byte
of control data will follow.This second byte may either be de­fined by a second byte-wide CS pulse or may follow the first
contiguously,i.e, it is not mandatory for CS to return high be­tween the first and second control bytes. At the end of
CCLK8 in the 2nd control byte the data is loaded into the ap­propriate programmable register. CS may remain low con­tinuously when programming successive registers, if de­sired. However, CS must be set high when no data transfers
are in progress.

To readback Interface Latch data or status information from
COMBO II, the first byte of the appropriate instruction is
strobed while CS is low, as defined in

Table 1

. CS must be
kept low, or be taken low again for a further 8 CCLK cycles,
during which the data is shifted onto the CO pin on the rising
edges of CCLK. When CS is high the CO pin is in the
high-impedance TRI-STATE, enabling the CI and CO pins of
many devices to be multiplexed together.

If CS returns high during either byte 1 or byte 2 before all
eight CCLK pulses of that byte occur, both the bit count and
byte count are reset and register contents are not affected.
This prevents loss of synchronization in the control interface
as well as corruption of register data due to processor inter­rupt or other problem. When CS returns low again, the de­vice will be ready to accept bit 1 of byte 1 of a new instruc­tion.

Programmable Functions

POWER-UP/DOWN CONTROL

Following power-on initialization, power-up and power-down
control may be accomplished by writing any of the control in­structions listed in

Table1

into COMBO II with the “P” bit set
to “0” for power-up or “1” for power-down. Normally it is rec­ommended that all programmable functions be initially pro­grammed while the device is powered down. Power state
control can then be included with the last programming in­struction or the separate single-byte instruction. Any of the
programmable registers may also be modified while the de­vice is powered-up or down by setting the “P” bit as indi­cated. When the power-up or down control is entered as a
single byte instruction, bit one (1) must be reset to a 0.

When a power-up command is given, all de-activated circuits
are activated, but the TRI-STATEPCM output(s), D

X

1 will re-

main in the high impedance state until the second FS

X

pulse

after power-up.

CONTROL REGISTER INSTRUCTION

The first byte of a READ or WRITE instruction to the Control
Register is as shown in

Table1

. The second byte has the fol-

lowing bit functions:

TABLE 2. Control Register Byte 2 Functions

Bit Number and Name

76543210 Function

F

1F0

MA IA DN DL AL PP

0 0 MCLK=512 kHz
0 1 MCLK=1.536 MHz

or 1.544 MHz
1 0 MCLK=2.048 MHz (Note 4)
1 1 MCLK=4.096 MHz

0 X Select µ255 Law (Note 4)
1 0 A-Law, Including

Even Bit

Inversion

1 1 A-Law, No Even Bit

Inversion

0 Delay Data Timing
1 Non-Delayed

Data Timing (Note 4)

0 0 Normal Operation (Note 4)
1 X Digital Loopback
0 1 Analog Loopback

0 Power Amp

Enabled in PDN

1 Power Amp

Disabled in PDN (Note 4)

Note 4: state at power-on initialization.

Master Clock Frequency Selection

A Master clock must be provided to COMBO II for operation
of the filter and coding/decoding functions. The MCLK fre­quency must be either 512 kHz, 1.536 MHz, 1.544 MHz,

2.048 MHz, or 4.096 MHz and must be synchronous with
BCLK. Bits F

1

and F0(see

Table2

) must be set during initial-

ization to select the correct internal divider.

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Programmable Functions (Continued)

Coding Law Selection

Bits “MA” and “IA” in

Table 2

permit the selection of µ255

coding or A-law coding, with or without even bit inversion.

Analog Loopback

Analog Loopback mode is entered by setting the “AL” and
“DL” bits in the Control Register as shown in

Table 2

.Inthe

analog loopback mode, the Transmit input VF

X

I is isolated

from the input pin and internally connected to the VF

R

O out­put, forming a loop from the Receive PCM Register back to
the Transmit PCM Register. The VF

R

O pin remains active,
and the programmed settings of the Transmit and Receive
gains remain unchanged, thus care must be taken to ensure
that overload levels are not exceeded anywhere in the loop.

Digital Loopback

Digital Loopback mode is entered by setting the “AL” and
“DL” bits in the Control Register as shown in

Table 2

. This
mode provides another stage of path verification by enabling
data written into the Receive PCM Register to be read back
from that register in any Transmit time-slot at D

X

1. PCM de-

coding continues and analog output appears at VF

R

0. The
output can be disabled by programming ‘No Output’ in the
Receive Gain Register (see

Table 8

).

INTERFACE LATCH DIRECTIONS

Immediately following power-on, all Interface Latches as­sume they are inputs, and therefore all IL pins are in a high
impedance state. Each IL pin may be individually pro­grammed as a logic input or output by writing the appropriate
instruction to the LDR, see

Table 1

and

Table 3

. For mini­mum power dissipation, unconnected latch pins should be
programmed as outputs. For the TP3076, bits 2 and 3 should
always be programmed as “1” (outputs).

Bits L

3–L0

must be set by writing the specific instruction to

the LDR with the L bits in the second byte set as follows:

TABLE 3. Byte 2 Functions of Latch Direction Register

Byte 2 Bit Number

76543210

L

0

L1L2L311XX

L

n

Bit IL Direction
0 Input
1 Output

X=Don’t Care

INTERFACE LATCH STATES

Interface Latches configured as outputs assume the state
determined by the appropriate data bit in the 2-byte instruc­tion written to the Interface Latch Register (ILR) as shown in

Table1

and

Table4

. Latches configured as inputs will sense
the state applied by an external source, such as the
Off-Hook detect output of a SLIC. All bits of the ILR, i.e.
sensed inputs and the programmed state of outputs, can be
read back in the 2nd byte of a READ from the ILR.

It is recommended that during initialization, the state of IL
pins to be configured as outputs should be programmed first
followed immediately by the Latch Direction Register.

TABLE 4. Interface Latch Data Bit Order

Bit Number

76543210

D

0

D1D2D3D4D5XX

TABLE 5. Coding Law Conventions

µ255 Law True A-Law with A-Law without

Even Bit Inversion Even Bit Inversion

MSB LSB MSB LSB MSB LSB

V

IN

=

+Full Scale 10000000 10101010 111111111

V

IN

=

0V 11111111 11010101 100000000

11111111 01010101 000000000

V

IN

=

−Full Scale 00000000 00101010 011111111

Note 5: The MSB is always the first PCM bit shifted in or out of COMBO II.

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Programmable Functions (Continued)

TABLE 6. Time-Slot and Port Assignment Instruction

Bit Number and Name Function

7 6 5 43210

EN PS T

5

T

4

T

3

T

2

T

1

T

0

(Note 6) (Note 7)

0 1 X XXXXXDisable D

X

1 Output (Transmit Instruction)

Disable D

R

1 Input (Receive Instruction)

1 1 Assign One Binary Coded Time-Slot from 0–63 Enable D

X

1 Output (Transmit Instruction)

Assign One Binary Coded Time-Slot from 0–63 Enable D

R

1 Input (Transmit Instruction)

Note 6: The “PS” bit MUST be set to “1” for both transmit and receive for the TP3076.
Note 7: T5 is the MSB of the time-slot assignment bit field. Time-slot bits should be set to “000000” for both transmit and receive when operating in non-delayed data

timing mode.

TIME-SLOT ASSIGNMENT

COMBO II can operate in either fixed time-slot or time-slot
assignment mode for selecting the Transmit and Receive
PCM time-slots. Following power-on, the device is automati­cally in Non-Delayed Timing mode, in which the time-slot al­ways begins with the leading (rising) edge of frame sync in­puts FS

X

and FSR. Time-Slot Assignment may only be used

with Delay Data timing; see

Figure 4

.FSXand FSRmay
have any phase relationship with each other in BCLK period
increments.

Alternatively, the internal time-slot assignment counters and
comparators can be used to access any time-slot in a frame,
using the frame sync inputs as marker pulses for the begin­ning of transmit and receive time-slot 0. In this mode, a
frame may consist of up to 64 time-slots of 8 bits each. A
time-slot is assigned by a 2-byte instruction as shown in

Table 1

and

Table 6

. The last 6 bits of the second byte indi­cate the selected time-slot from 0–63 using straight binary
notation. When writing a time-slot and port assignment reg­ister,if the PCM interface is currently active, it is immediately
deactivated to prevent possible bus clashes. A new assign­ment becomes active on the second frame following the end
of the Chip-Select for the second control byte. Rewriting of
the register contents should not be performed during the
talking period of a connection to prevent waveform distortion
caused by loss of a sample which will occur with each regis­ter write. The “EN” bit allows the PCM input, D

R

1, or output,

D

X

1, as appropriate, to be enabled or disabled.

Time-Slot Assignment mode requires that the FS

X

and FS

R

pulses conform to the delayed data timing format shown in

Figure 4

.

PORT SELECTION

On the TP3076, the “PS” bit MUST always be set to 1.

Table 6

shows the format for the second byte of both trans-

mit and receive time-slot and port assignment instructions.

TRANSMIT GAIN INSTRUCTION BYTE 2

The transmit gain can be programmed in 0.1 dB steps by
writing to the Transmit Gain Register as defined in

Table 1

and

Table7

. This corresponds to a range of 0 dBm0 levels at

VF

X

I between 1.375 Vrms and 0.074 Vrms (equivalent to

+5.0 dBm to −20.4 dBm in 600Ω).
To calculate the binary code for byte 2 of this instruction for

any desired input 0 dBm0 level in Vrms, take the nearest in­teger to the decimal number given by:

200 x log

10

(V/0.07299)

and convert to the binary equivalent. Some examples are
given in

Table 7

. A complete tabulation is given in Appendix

I of AN-614.
It should be noted that the Transmit (idle channel) Noise and

Transmit Signal to Total Distortion are both specified with
transmit gain set to 0 dB (gain register set to all ones). At
high transmit gains there will be some degradation in noise
performance for these parameters. See Application Note
AN-614 for more information on this subject.

TABLE 7. Byte 2 of Transmit Gain Instruction

Bit Number 0 dBm0 Test Level (Vrms)

76543210 atVF

X

I

00000000 NoOutput (Note 8)
00000001 0.074
00000010 0.075

——
11111110 1.359
11111111 1.375

Note 8: Analog signal path is cut off, but DXremains active and will output
codes representing idle noise.

RECEIVE GAIN INSTRUCTION BYTE 2

The receive gain can be programmed in 0.1 dB steps by writ­ing to the Receive Gain Register as defined in

Table 1

and

Table8

. Note the following restrictions on output drive capa-

bility:

1. 0 dBm0 levels ≤ 1.96 Vrms at VF

R

O may be driven into
a load of ≥ 15 kΩ to GND; Receive Gain set to 0 dB (gain
register set to all ones).

2. 0 dBm0 levels ≤ 1.85 Vrms at VF

R

O may be driven into
a load of ≥ 600Ω to GND; Receive Gain set to 0.5 dB.

3. 0 dBm0 levels ≤ 1.71 Vrms at VF

R

O may be driven into
a load of ≥ 300 Ω to GND. Receive Gain set to −1.2 dB.

To calculate the binary code for byte 2 of this instruction for
any desired output 0 dBm0 level in Vrms, take the nearest in­teger to the decimal number given by:

200 x log

10

(V/0.1043)

and convert to the binary equivalent. Some examples are
given in

Table8

.A complete tabulation is given in Appendix I

or AN-614.

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Programmable Functions (Continued)

TABLE 8. Byte 2 of Receive Gain Instruction
Bit Number 0 dBm0 Test Level (Vrms)

76543210 atVF

R

O

00000000 NoOutput (Low Z to GND)
00000001 0.105
00000010 0.107

——
11111110 1.941
11111111 1.964

Applications Information

Figure 2

shows a typical ISDN phone application of the
TP3076 together with a TP3420 ISDN Transceiver “S” Inter­face Device and HPC16400 High-Performance Microcontrol­ler with HDLC Controller. The TP3076 device is programmed
over its serial control interface via the HPC16400
MICROWIRE/PLUS

™

serial I/O port.

POWER SUPPLIES

While the pins of the TP3076 COMBO II device are well pro­tected against electrical misuse, it is recommended that the
standard CMOS practice of applying GND to the device be­fore any other connections are made should always be fol­lowed. In applications where the printed circuit card may be
plugged into a hot socket with power and clocks already
present, an extra long ground pin on the connector should be
used and a Schottky diode connected between V

BB

and

GND.
To minimize noise sources all ground connections to each

device should meet at a common point as close as possible
to the GND pin in order to prevent the interaction of ground
return currents flowing through a common bus impedance.
Power supply decoupling capacitors of 0.1 µF should be
connected from this common point to V

CC

and VBBas close

to the device pins as possible.
Further guidelines on PCB layout techniques are provided in

Application Note AN-614, “COMBO II

™

Programmable PCM

CODEC/Filter Family Application Guide”.

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Applications Information

DS009758-5

Note 9: Primo type EM80–PMI2 or similar.

Note 10: Primo type DH31 or similar.

Note 11: Sidetone

≅

−9.2 dB for 200Ω,

Sidetone

≅

−21.5 dB for 1200Ω.

FIGURE 2. Typical Application in an ISDN Phone

www.national.com 8

Absolute Maximum Ratings (Note 12)

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.

V

CC

to GND 7V

Voltage at VF

X

IV

CC

+0.5V to VBB−0.5V

Voltage at Any Digital Input V

CC

+0.5V to GND −0.5V

Storage Temperature Range −65˚C to +150˚C
V

BB

to GND −7V

Current at VF

R

0

±

100 mA

Current at Any Digital Output

±

50 mA

Lead Temperature

(Soldering, 10 sec.) 300˚C

Electrical Characteristics

Unless otherwise noted, limits printed in BOLD characters are guaranteed for V

CC

=

+5V

±

5%,V

BB

=

−5V

±

5%;T

A

=

0˚C to

+70˚C by correlation with 100%electrical testing at T

A

=

25˚C. All other limits are assured by correlation with other production

tests and/or product design and characterization. All signals referenced to GND. Typicals specified at V

CC

=

+5V, V

BB

=

−5V,

T

A

=

25˚C.

Symbol Parameter Conditions Min Typ Max Units
DIGITAL INTERFACES

V

IL

Input Low Voltage All Digital Inputs (DC Meas.) 0.7 V

V

IH

Input High Voltage All Digital Inputs (DC Meas.) (Note 13) 2.0 V

V

OL

Output Low Voltage DX1, TSX1, and CO, I

L

=

3.2 mA,

0.4 V

All Other Digital Outputs, I

L

=

1mA

V

OH

Output High Voltage DX1 and CO, I

L

=

−3.2 mA, 2.4 V

All Other Digital Outputs (except TS

X

), I

L

=

−1 mA

All Digital Outputs, I

L

=

−100 µA V

CC

− 0.5 V

I

IL

Input Low Current Any Digital Input, GND<V

IN

<

V

IL

−10 10 µA

I

IH

Input High Current Any Digital Input, except MR, V

IH

<

V

IN

<

V

CC

−10 10 µA

MR Only −10 100

I

OZ

Output Current in DX1, TSX1and CO
High Impedance IL3–IL0 when Selected as Inputs −10 10 µA
State (TRI-STATE ) GND

<

V

OUT

<

V

CC

ANALOG INTERFACES

I

VFXI

Input Current, VFXI −3.3V<VFXI<3.3V −1.0 1.0 µA

R

VFXI

Input Resistance −3.3V<VFXI<3.3V 1.0 MΩ

VOS

X

Input Offset Voltage Transmit Gain=0 dB 200 mV
Applied at VF

X

I Transmit Gain=25.40 dB 10 mV

RL

VFRO

Load Resistance Receive Gain=0 dB 15k

Receive Gain=−0.5 dB 600 Ω
Receive Gain=−1.2 dB 300

CL

VFRO

Load Capacitance RL

VFRO

≥ 300Ω 200 pF

CL

VFRO

from VFROtoGND

RO

VFRO

Output Resistance Steady Zero PCM Code Applied to DR1 1.0 3.0 Ω

VOS

R

Output Offset Voltage Alternating±Zero PCM Code Applied −200 200 mV
at V

FRO

DR1, Maximum Receive Gain

POWER DISSIPATION

I

CC

0 Power Down Current CCLK, CI, CO=0.4V, CS=2.4V

Interface Latches Set as Outputs with No Load, 0.1 0.6 mA
All Other Inputs Active, Power Amp Disabled

I

BB

0 Power Down Current As Above −0.1 −0.3 mA

I

CC

1 Power Up Current CCLK, CI, CO=0.4V, CS=2.4V

No Load on Power Amp 8.0 11.0 mA
Interface Latches Set as Outputs with No Load

I

BB

1 Power Up Current As Above −8.0 −11.0 mA

I

CC

2 Power Down Current As Above, Power Amp Enabled 2.0 3.0 mA

I

BB

2 Power Down Current As Above, Power Amp Enabled −2.0 −3.0 mA

Note 12: “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional, but do not guarantee specific performance limits.

www.national.com9

Electrical Characteristics (Continued)

Note 13: See definitions and timing conventions section.

Timing Specifications

Unless otherwise noted, limits printed in BOLD characters are guaranteed for V

CC

=

+5V

±

5%;V

BB

=

−5V

±

5%;T

A

=

0˚C to

+70˚C by correlation with 100%electrical testing at T

A

=

25˚C. All other limits are assured by correlation with other production

tests and/or product design and characterization. All signals referenced to GND. Typicals specified at V

CC

=

+5V, V

BB

=

−5V,

T

A

=

25˚C.

All timing parameters are measured at V

OH

=

2.0V and V

OL

=

0.7V.

See Definitions and Timing Conventions section for test methods information.

Symbol Parameter Conditions Min Typ Max Units

MASTER CLOCK TIMING

f

MCLK

Frequency of MCLK Selection of Frequency is Programmable 512 kHz

(See

Table 5

) 1536 kHz

1544 kHz
2048 kHz
4096 kHz

t

WMH

Period of MCLK High Measured from VIHto VIH(Note 14) 80 ns

t

WML

Period of MCLK Low Measured from VILto VIL(Note 14) 80 ns

t

RM

Rise Time of MCLK Measured from VILto V

IH

30 ns

t

FM

Fall Time of MCLK Measured from VIHto V

IL

30 ns

t

HBM

HOLD Time, BCLK LOW 50 ns
to MCLK HIGH

t

WFL

Period of FS

X

Measured from VILto V

IL

1 MCLK

or FS

R

Low Period

PCM INTERFACE TIMING

f

BCLK

Frequency of BCLK May Vary from 64 kHz to 4096 kHz 64 4096 kHz

in 8 kHz Increments

t

WBH

Period of BCLK High Measured from VIHto V

IH

80 ns

t

WBL

Period of BCLK Low Measured from VILto V

IL

80 ns

t

RB

Rise Time of BCLK Measured from VILto V

IH

30 ns

t

FB

Fall Time of BCLK Measured from VIHto V

IL

30 ns

t

HBF

Hold Time, BCLK Low 30 ns
to FS

X/R

High or Low

t

SFB

Setup Time, FS

X/R

30 ns

High to BCLK Low

t

DBD

Delay Time, BCLK High Load=100 pF Plus 2 LSTTL Loads 80 ns
to Data Valid

t

DBZ

Delay Time, BCLK Low to DX1D

X

1 disabled is measured

Disabled if FS

X

Low, FSXLow to at VOLor VOHaccording

D

X

1 disabled if 8th BCLK to

Figure 5

15 80 ns

Low, or BCLK High to D

X

1

Disabled if FS

X

High

t

DBT

Delay Time, BCLK High to Load=100 pF Plus 2 LSTTL Loads
TS

X

Low if FSXHigh, or 60 ns

FS

X

High to TSXLow if
BCLK High (Nondelayed mode); BCLK
High to TS

X

Low (delayed data mode)

t

ZBT

TRI-STATE Time, BCLK Low to
TS

X

High if FSXLow, FSXLow
to TSXHigh if 8th BCLK Low, or 15 60 ns
BCLK High to TS

X

High if FSXHigh

t

DFD

Delay Time, FS

X/R

Load=100 pF Plus 2 LSTTL Loads,

www.national.com 10

Timing Specifications (Continued)

Unless otherwise noted, limits printed in BOLD characters are guaranteed for V

CC

=

+5V

±

5%;V

BB

=

−5V

±

5%;T

A

=

0˚C to

+70˚C by correlation with 100%electrical testing at T

A

=

25˚C. All other limits are assured by correlation with other production

tests and/or product design and characterization. All signals referenced to GND. Typicals specified at V

CC

=

+5V, V

BB

=

−5V,

T

A

=

25˚C.

All timing parameters are measured at V

OH

=

2.0V and V

OL

=

0.7V.

See Definitions and Timing Conventions section for test methods information.

Symbol Parameter Conditions Min Typ Max Units

PCM INTERFACE TIMING

High to Data Valid Applies if FS

X/R

Rises Later Than 80 ns
BCLK Rising Edge in Non-Delayed Data
Mode Only

t

SDB

Setup Time, DR1 30 ns
Valid to BCLK Low

t

HBD

Hold Time, BCLK 15 ns
Low to D

R

1 Invalid

SERIAL CONTROL PORT TIMING

f

CCLK

Frequency of CCLK 2048 kHz

t

WCH

Period of CCLK High Measured from VIHto V

IH

160 ns

t

WCL

Period of CCLK Low Measured from VILto V

IH

160 ns

t

RC

Rise Time of CCLK Measured from VILto V

IH

50 ns

t

FC

Fall Time of CCLK Measured of VIHto V

IL

50 ns

t

HCS

Hold Time, CCLK Low CCLK1 10 ns
to CS Low

t

HSC

Hold Time, CCLK CCLK8 100 ns
Low to CS High

t

SSC

Setup Time, CS 60 ns
Transition to CCLK Low

t

SSC0

Setup Time, CS To Insure CO is Not Enabled 60 ns
Transition to CCLK High for Single Byte

t

SDC

Setup Time, CI 50 ns
Data In to CCLK Low

t

HCD

Hold Time, CCLK 50 ns
Low to CO Invalid

t

DCD

Delay Time, CCLK High Load=100 pF Plus 2 LSTTL Loads 80 ns
to CO Data Out Valid

t

DSD

Delay Time, CS Low Applies Only if Separate 80 ns
to CO Valid CS Used for Byte 2

t

DDZ

Delay Time, CS or 9th CCLK Applies to Earlier of CS 15 80 ns
High to CO High Impedance High or 9th CCLK High

INTERFACE LATCH TIMING

t

SLC

Setup Time, IL to Interface Latch Inputs Only 100 ns
CCLK 8 of Byte 1

t

HCL

Hold Tme, IL Valid from 50 ns
8th CCLK Low (Byte 1)

t

DCL

Delay Time CCLK8 of Interface Latch Outputs Only 200 ns
Byte2toIL C

L

=

50 pF

Note 14: Applies only to MCLK Frequencies ≥ 1.536 MHz. At 512 kHz a 50:50±2%Duty Cycle must be used.

www.national.com11

Timing Diagrams

DS009758-6

FIGURE 3. Non-Delayed Data Timing Mode

DS009758-7

FIGURE 4. Delayed Data Timing Mode

www.national.com 12

Timing Diagrams (Continued)

DS009758-8

FIGURE 5. Control Port Timing

www.national.com13

Transmission Characteristics

Unless otherwise noted, limits printed in BOLD characters are guaranteed for V

CC

=

+5V

±

5%,V

BB

=

−5V

±

5%;T

A

=

0˚C to

+70˚C by correlation with 100%electrical testing at T

A

=

25˚C. f=1015.625 Hz, VF

X

I=0 dBm0, DR1=0 dBm0 PCM code.
Transmit and receive gains programmed for maximum 0 dBm0 test levels (0 dB Gain). All other limits are assured by correla­tion with other production tests and/or product design and characterization. All signals referenced to GND. Typicals specified
at V

CC

=

+5V, V

BB

=

−5V, T

A

=

25˚C.

Symbol Parameter Conditions Min Typ Max Units

AMPLITUDE RESPONSE

Absolute Levels The Maximum 0 dBm0 Levels Are:

VF

X

I 1.375 Vrms

VF

R

O (15 kΩ Load) 1.964 Vrms
The Minimum 0 dBm0 Levels are:
VF

X

I 73.8 mVrms
VF

R

O (Any Load ≥ 300Ω) 105.0 mVrms

G

XA

Transmit Gain Transmit Gain Programmed for Maximum
Absolute Accuracy 0 dBm0 Test Level.

Measure Deviation of Digital Code from
Ideal 0 dBm0 PCM Code at D

X

1.

T

A

=

25˚C −0.15 0.15 dB

G

XAG

Transmit Gain T

A

=

25˚C, V

CC

=

5V, V

BB

=

5V
Variation with Programmed Gain from 0 dB to 19 dB
Programmed Gain (0 dBm0 Levels of 1.619 Vrms to 0.182 Vrms) −0.1 0.1 dB

Programmed Gain from 19.1 dB to 25.4 dB
(0 dBm0 Levels of 0.180 Vrms to 0.087 Vrms) −0.3 0.3 dB

Note:±0.1 dB Min/Max is Available as a Selected Part

G

XAF

Transmit Gain Relative to 1015.625 Hz, (Note 18)
Variation with Minimum Gain

<

G

X

<

Maximum Gain

Frequency f=60 Hz −26 dB

f=200 Hz −1.8 −0.1 dB
f=300 Hz to 3000 Hz −0.15 0.15 dB
f=3400 Hz −0.7 0.0 dB
f=400 Hz −14 dB
f ≥ 4600 Hz. Measure Response −32 dB
at Alias Frequency from 0 kHz to 4 kHz
G

X

=

0.0 dB, VF

X

I=1.375 Vrms
Relative to 1015.625 Hz
f=62.5 Hz −24.9 dB
f=203.125 Hz −1.7 −0.1 dB
f=343.75 Hz −0.15 0.15 dB
f=515.625 Hz −0.15 0.15 dB
f=2140.625 Hz −0.15 0.15 dB
f=3156.25 Hz −0.15 0.15 dB
f=3406.250 Hz −0.74 0.0 dB
f=3984.375 Hz −13.5 dB
Relative to 1062.5 Hz (Note 18)
f=5250 Hz, Measure 2750 Hz −32 dB
f=11750 Hz, Measure 3750 Hz −32 dB
f=49750 Hz, Measure 1750 Hz −32 dB

G

XAT

Transmit Gain Measured Relative to GXA,V

CC

=

5V,

Variation with V

BB

=

−5V, −0.1 0.1 dB

Temperature Minimum gain

<

G

X

<

Maximum Gain

www.national.com 14

Transmission Characteristics (Continued)

Unless otherwise noted, limits printed in BOLD characters are guaranteed for V

CC

=

+5V

±

5%,V

BB

=

−5V

±

5%;T

A

=

0˚C to

+70˚C by correlation with 100%electrical testing at T

A

=

25˚C. f=1015.625 Hz, VF

X

I=0 dBm0, DR1=0 dBm0 PCM code.
Transmit and receive gains programmed for maximum 0 dBm0 test levels (0 dB Gain). All other limits are assured by correla­tion with other production tests and/or product design and characterization. All signals referenced to GND. Typicals specified
at V

CC

=

+5V, V

BB

=

−5V, T

A

=

25˚C.

Symbol Parameter Conditions Min Typ Max Units

AMPLITUDE RESPONSE

G

XAL

Transmit Gain Sinusoidal Test Method.
Variation with Reference Level=0 dBm0
Signal Level VF

X

I=−40 dBm0 to +3 dBm0 −0.2 0.2 dB

VF

X

I=−50 dBm0 to −40 dBm0 −0.4 0.4 dB

VF

X

I=−55 dBm0 to −50 dBm0 −1.2 1.2 dB

G

RA

Receive Gain Receive Gain Programmed for Maximum
Absolute Accuracy 0 dBm0 Test Level. Apply 0 dBm0 −0.15 0.15 dB

PCM Code to D

R

1. Measure VFR0.

T

A

=

25˚C

G

RAG

Receive Gain T

A

=

25˚C, V

CC

=

5V, V

BB

=

−5V
Variation with Programmed Gain from 0 dB to 19 dB
Programmed Gain (0 dBm0 Levels of 1.964 Vrms to 0.220 Vrms) −0.1 0.1 dB

Programmed Gain from 19.1 dB to 25.4 dB
(0 dBm0 Levels of 0.218 Vrms to 0.105 Vrms) −0.3 0.3 dB

Note:±0.1 dB Min/Max is Available as a Selected Part

G

RAT

Receive Gain Measured Relative to GRA.
Variation with V

CC

=

5V, V

BB

=

−5V. −0.1 0.1 dB

Temperature Minimum Gain

<

G

R

<

Maximum Gain

G

RAF

Receive Gain Relative to 1015.625 Hz, (Note 18)
Variation with D

R

1=0 dBm0 Code.

Frequency Minimum Gain

<

G

R

<

Maximum Gain
f=200 Hz −0.25 0.15 dB
f=300 Hz to 3000 Hz −0.15 0.15 dB
f=3400 Hz −0.7 0.0 dB
f=4000 Hz −14 dB
G

R

=

0 dB, D

R

1=0 dBm0 Code,

G

X

=

0 dB (Note 18)
f=296.875 Hz −0.15 0.15 dB
f=1875.00 Hz −0.15 0.15 dB
f=2906.25 Hz −0.15 0.15 dB
f=2984.375 Hz −0.15 0.15 dB
f=3406.250 Hz −0.74 0.0 dB
f=3984.375 Hz −13.5 dB

G

RAL

Receive Gain Sinusoidal Test Method.
Variation with Reference Level=0 dBm0.
Signal Level D

R

1=−40 dBm0 to +3 dBm0 −0.2 0.2 dB

D

R

1=−50 dBm0 to −40 dBm0 −0.4 0.4 dB

D

R

1=−55 dBm0 to −50 dBm0 −1.2 1.2 dB

DR

1

=

3.1 dBm0 −0.5

R

L

=

600Ω,G

R

=

−0.5 dB −0.2 0.2 dB

R

L

=

300Ω,G

R

=

1.2 dB −0.2 0.2 dB

ENVELOPE DELAY DISTORTION WITH FREQUENCY

D

XA

Tx Delay, Absolute f=1600 Hz 315 µs

www.national.com15

Transmission Characteristics (Continued)

Unless otherwise noted, limits printed in BOLD characters are guaranteed for V

CC

=

+5V

±

5%,V

BB

=

−5V

±

5%;T

A

=

0˚C to

+70˚C by correlation with 100%electrical testing at T

A

=

25˚C. f=1015.625 Hz, VF

X

I=0 dBm0, DR1=0 dBm0 PCM code.
Transmit and receive gains programmed for maximum 0 dBm0 test levels (0 dB Gain). All other limits are assured by correla­tion with other production tests and/or product design and characterization. All signals referenced to GND. Typicals specified
at V

CC

=

+5V, V

BB

=

−5V, T

A

=

25˚C.

Symbol Parameter Conditions Min Typ Max Units

ENVELOPE DELAY DISTORTION WITH FREQUENCY

D

XR

Tx Delay, Relative to DXA f=500 Hz–600 Hz 220 µs

f=600 Hz–800 Hz 145 µs
f=800 Hz–1000 Hz 75 µs
f=1000 Hz–1600 Hz 40 µs
f=1600 Hz–2600 Hz 75 µs
f=2600 Hz–2800 Hz 105 µs
f=2800 Hz–3000 Hz 155 µs

D

RA

Rx Delay, Absolute f=1600 Hz 200 µs

D

RR

Rx Delay, Relative to DRA f=500 Hz–1000 Hz −40 µs

f=1000 Hz–1600 Hz −30 µs
f=1600 Hz–2600 Hz 90 µs
f=2600 Hz–2800 Hz 125 µs
f=2800 Hz–3000 Hz 175 µs

NOISE

N

XC

Transmit Noise, C Message (Note 15) 11111111 12 15 dBrnC0
Weighted, µ-Law Selected in Gain Register

N

XP

Transmit Noise, P Message (Note 15) 11111111 −74 −67 dBm0p
Weighted, A-Law Selected in Gain Register

N

RC

Receive Noise, C Message PCM Code is Alternating Positive 8 11 dBrnC0
Weighted, µ-Law Selected

N

RP

Receive Noise, P Message PCM Code Equals Positive Zero −82 −79 dBm0p
Weighted, A-Law Selected

N

RS

Noise, Single Frequency f=0 kHz to 100 kHz, Loop Around −53 dBm0

Measurement, VF

X

I=0 Vrms

PPSR

X

Positive Power Supply V

CC

=

5.0 V

DC

+ 100 mVrms

Rejection, Transmit f=0 kHz–4 kHz (Note 16) 36 dBC

f=4 kHz–50 kHz 30 dBC

NPSR

X

Negative Power Supply V

BB

=

−5.0 V

DC

+100 mVrms

Rejection, Transmit f=0 kHz–4 kHz (Note 16) 36 dBC

f=4 kHz–50 kHz 30 dBC

PPSR

R

Positive Power Supply PCM Code Equals Positive Zero
Rejection, Receive V

CC

=

5.0 V

DC

+ 100 mVrms

Measure VF

R

O
f=0 Hz–4000 Hz 36 dBC
f=4 kHz–25 kHz 40 dB
f=25 kHz–50 kHz 36 dB

NPSR

R

Negative Power Supply PCM Code Equals Positive Zero
Rejection, Receive V

BB

=

−5.0 V

DC

+ 100 mVrms

Measure VF

R

O
f=0 Hz–4000 Hz 36 dBC
f=4 kHz–25 kHz 40 dB
f=25 kHz–50 kHz 36 dB

www.national.com 16

Transmission Characteristics (Continued)

Unless otherwise noted, limits printed in BOLD characters are guaranteed for V

CC

=

+5V

±

5%,V

BB

=

−5V

±

5%;T

A

=

0˚C to

+70˚C by correlation with 100%electrical testing at T

A

=

25˚C. f=1015.625 Hz, VF

X

I=0 dBm0, DR1=0 dBm0 PCM code.
Transmit and receive gains programmed for maximum 0 dBm0 test levels (0 dB Gain). All other limits are assured by correla­tion with other production tests and/or product design and characterization. All signals referenced to GND. Typicals specified
at V

CC

=

+5V, V

BB

=

−5V, T

A

=

25˚C.

Symbol Parameter Conditions Min Typ Max Units

NOISE

SOS Spurous Out-of-Band 0 dBm0 300 Hz to 3400 Hz Input PCM Code

Signals Applied at the at D

R

1

Channel Output 4600 Hz–7600 Hz −30 dB

7600 Hz–8400 Hz −40 dB
8400 Hz–50,000 Hz −30 dB

DISTORTION

STD

X

Signal to Total Distortion Sinusoidal Test Method

STD

R

Transmit or Receive Level=3.0 dBm0 33 dBC
Half-Channel, µ-Law

=

0 dBm0 to −30 dBm0 36 dBC

Selected

=

−40 dBm0 30 dBC

=

−45 dBm0 25 dBC

STD

RL

Single to Total Distortion Sinusoidal Test Method
Receive with Resistive Level=+3.1 dBm0
Load R

L

=

600Ω,G

R

=

−0.5 dB 33 dBC

R

L

=

300Ω,G

R

=

−1.2 dB 33 dBC

SFD

X

Single Frequency −46 dB
Distortion, Transmit

SFD

R

Single Frequency −46 dB
Distortion, Receive

IMD Intermodulation Distortion Transmit or Receive

Two Frequencies in the Range −41 dB
300 Hz–3400 Hz

CROSSTALK

CT

X-R

Transmit to Receive Crosstalk, f=300 Hz–3400 Hz −90 −75 dB
0 dBm0 Transmit Level D

R

=

Idle Code

CT

R-X

Receive to Transmit Crosstalk, f=300 Hz–3400 Hz −90 −70 dB
0 dBm0 Receive Level (Note 16)

Note 15: Measured by grounded input at V

FXI

.

Note 16: PPSR

X

, NPSRX, and CT

R-X

are measured with a −50 dBm0 activation signal applied to VFXI.

Note 17: A signal is Valid if it is above V

IH

or below VILand Invalid if it is between VILand VIH. For the purposes of this specification the following conditions apply:

a) All input signals are defined as: V

IL

=

0.4V, V

IH

=

2.7V, t

R

<

10 ns, t

F

<

10 ns.

b) t

R

is measured from VILto VIH.tFis measured from VIHto VIL.
c) Delay Times are measured from the input signal Valid to the output signal Valid.
d) Setup Times are measured from the data input Valid to the clock input Invalid.
e) Hold Times are measured from the clock signal Valid to the data input Invalid.
f) Pulse widths are measured from V

IL

to VILor from VIHto VIH.

Note 18: A multi-tone test technique is used.

www.national.com17

Physical Dimensions inches (millimeters) unless otherwise noted

LIFE SUPPORT POLICY

NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DE­VICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMI­CONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or sys­tems which, (a) are intended for surgical implant into
the body, or (b) support or sustain life, and whose fail­ure to perform when properly used in accordance
with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
to the user.

2. A critical component is any component of a life support
device or system whose failure to perform can be rea­sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.

National Semiconductor
Corporation

Americas
Tel: [phone]
Fax: [phone]
Email: [e-mail]

www.national.com

National Semiconductor
Europe

Fax: [phone]

Email: [e-mail]
Deutsch Tel: [phone]
English Tel: [phone]
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Italiano Tel: [phone]

National Semiconductor
Asia Pacific Customer
Response Group

Tel: [phone]
Fax: [phone]
Email: [e-mail]

National Semiconductor
Japan Ltd.

Tel: [phone]
Fax: [phone]

Ceramic Dual-In-Line Package (J)

Order Number TP3076J

NS Package Number J20A

TP3076 COMBO II Programmable PCM CODEC/Filter for ISDN and Digital Phone Applications

National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.