Datasheet TP3067V-X, TP3067WM, TP3067V, TP3067N Datasheet (NATIONAL SEMICONDUCTOR)

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Page 1

TL/H/5070

TP3064, TP3067 ‘‘Enhanced’’ Serial Interface CMOS CODEC/Filter COMBO

October 1991

TP3064, TP3067 ‘‘Enhanced’’ Serial Interface CMOS CODEC/Filter COMBO

General Description

The TP3064 (m-law) and TP3067 (A-law) are monolithic PCM CODEC/Filters utilizing the A/D and D/A conversion architecture shown in

Figure 1

, and a serial PCM interface. The devices are fabricated using National’s advanced double-poly CMOS process (microCMOS).

Similar to the TP305X family, these devices feature an additional Receive Power Amplifier to provide push-pull balanced output drive capability. The receive gain can be adjusted by means of two external resistors for an output level of up to

6.6V across a balanced 600X load.

Also included is an Analog Loopback switch and a TS

out-

put.

See also AN-370, ‘‘Techniques for Designing with CODEC/ Filter COMBO Circuits.’’

COMBOÉand TRI-STATEÉare registered trademarks of National Semiconductor Corporation.

Features

Complete CODEC and filtering system including: Ð Transmit high-pass and low-pass filtering Ð Receive low-pass filter with sin x/x correction Ð Active RC noise filters Ð m-law or A-law compatible COder and DECoder Ð Internal precision voltage reference Ð Serial I/O interface Ð Internal auto-zero circuitry Ð Receive push-pull power amplifiers

m-lawÐTP3064

A-lawÐTP3067

Designed for D3/D4 and CCITT applications

5V operation

Low operating powerÐtypically 70 mW

Power-down standby modeÐtypically 3 mW

Automatic power-down

TTL or CMOS compatible digital interfaces

Maximizes line interface card circuit density

Block Diagram

TL/H/5070– 1

FIGURE 1

1995 National Semiconductor Corporation RRD-B30M115/Printed in U. S. A.

Page 2

Connection Diagrams

Dual-In-Line Package

TL/H/5070– 2

Top View

Plastic Chip Carrier

TL/H/5070– 6

Top View

Order Number TP3064J or TP3067J

See NS Package J20A

Order Number TP3064WM or TP3067WM

See NS Package M20B

Order Number TP3064N or TP3067N

See NS Package N20A

Order Number TP3064V or TP3067V

See NS Package V20A

Pin Description

Symbol Function

VPO

The non-inverted output of the receive power amplifier.

GNDA Analog ground. All signals are referenced to

this pin.

VPO

The inverted output of the receive power

amplifier. VPI Inverting input to the receive power amplifier. VF

O Analog output of the receive filter.

Positive power supply pin. V

5Vg5%.

Receive frame sync pulse which enables

BCLK

to shift PCM data into DR.FSRis an

8 kHz pulse train. See

Figures 2

and3for

timing details. D

Receive data input. PCM data is shifted into

following the FSRleading edge.

BCLK

/ The bit clock which shifts data into DRafter

the FS

leading edge. May vary from 64 kHz

CLKSEL

to 2.048 MHz. Alternatively, may be a logic

input which selects either

1.536 MHz/1.544 MHz or 2.048 MHz for

master clock in synchronous mode and

BCLK

is used for both transmit and receive

directions (see Table I). MCLK

/ Receive master clock. Must be 1.536 MHz,

1.544 MHz or 2.048 MHz. May be

PDN

asynchronous with MCLK

, but should be

synchronous with MCLK

for best

performance. When MCLK

is connected

continuously low, MCLK

is selected for all

internal timing. When MCLK

is connected continuously high, the device is powered down.

Symbol Function

MCLK

Transmit master clock. Must be 1.536 MHz,

1.544 MHz or 2.048 MHz. May be asynchronous with MCLK

. Best performance is realized from synchronous operation.

BCLK

The bit clock which shifts out the PCM data on D

. May vary from 64 kHz to 2.048 MHz,

but must be synchronous with MCLK

The TRI-STATEÉPCM data output which is enabled by FS

Transmit frame sync pulse input which enables BCLK

to shift out the PCM data on

.FSXis an 8 kHz pulse train, see

Figures 2

and3for timing details.

Open drain output which pulses low during the encoder time slot.

ANLB Analog Loopback control input. Must be set

to logic ‘0’ for normal operation. When pulled to logic ‘1’, the transmit filter input is disconnected from the output of the transmit preamplifier and connected to the VPO

output of the receive power amplifier.

Analog output of the transmit input amplifier. Used to externally set gain.

Inverting input of the transmit input amplifier.

Non-inverting input of the transmit input amplifier.

Negative power supply pin. V

5Vg5%.

Page 3

Functional Description

POWER-UP

When power is first applied, power-on reset circuitry initializes the COMBO

and places it into a power-down state. All

non-essential circuits are deactivated and the D

,VFRO,

VPO

and VPOaoutputs are put in high impedance states. To power-up the device, a logical low level or clock must be applied to the MCLK

/PDN pin

and

FSXand/or FSRpulses must be present. Thus, 2 power-down control modes are available. The first is to pull the MCLK

/PDN pin high; the

alternative is to hold both FS

and FSRinputs continuously lowÐthe device will power-down approximately 2 ms after the last FS

or FSRpulse. Power-up will occur on the first

or FSRpulse. The TRI-STATE PCM data output, DX,

will remain in the high impedance state until the second FS

pulse.

SYNCHRONOUS OPERATION

For synchronous operation, the same master clock and bit clock should be used for both the transmit and receive directions. In this mode, a clock must be applied to MCLK

and the MCLKR/PDN pin can be used as a power-down control. A low level on MCLK

/PDN powers up the device and a high level powers down the device. In either case, MCLK

will be selected as the master clock for both the transmit and receive circuits. A bit clock must also be applied to BCLK

and the BCLKR/CLKSEL can be used to select the proper internal divider for a master clock of 1.536 MHz, 1.544 MHz or 2.048 MHz. For 1.544 MHz operation, the device automatically compensates for the 193rd clock pulse each frame.

With a fixed level on the BCLK

/CLKSEL pin, BLCKXwill be selected as the bit clock for both the transmit and receive directions. Table I indicates the frequencies of operation which can be selected, depending on the state of BCLK

CLKSEL. In this synchronous mode, the bit clock, BCLK

, may be from 64 kHz to 2.048 MHz, but must be synchronous with MCLK

Each FSXpulse begins the encoding cycle and the PCM data from the previous encode cycle is shifted out of the enabled D

output on the positive edge of BCLKX. After 8

bit clock periods, the TRI-STATE D

output is returned to a

high impedance state. With an FS

pulse, PCM data is

latched via the D

input on the negative edge of BCLKX(or

BCLK

if running). FSXand FSRmust be synchronous with

MCLK

X/R

TABLE I. Selection of Master Clock Frequencies

Master Clock

BCLK

/CLKSEL

Frequency Selected

TP3067 TP3064

Clocked 2.048 MHz 1.536 MHz or

1.544 MHz

0 1.536 MHz or 2.048 MHz

1.544 MHz

1 2.048 MHz 1.536 MHz or

1.544 MHz

ASYNCHRONOUS OPERATION

For asynchronous operation, separate transmit and receive clocks may be applied. MCLK

and MCLKRmust be 2.048 MHz for the TP3067, or 1.536 MHZ, 1.544 MHz for the TP3064, and need not be synchronous. For best transmis-

sion performance, however, MCLK

should be synchronous

with MCLK

, which is easily achieved by applying only static

logic levels to the MCLK

/PDN pin. This will automatically

connect MCLK

to all internal MCLKRfunctions (see Pin Description). For 1.544 MHz operation, the device automatically compensates for the 193rd clock pulse each frame. FS

starts each encoding cycle and must be synchronous

with MCLK

and BCLKX.FSRstarts each decoding cycle

and must be synchronous with BCLK

. BCLKRmust be a clock, the logic levels shown in Table I are not valid in asynchronous mode. BCLK

and BCLKRmay operate from 64

kHz to 2.048 MHz.

SHORT FRAME SYNC OPERATION

The COMBO can utilize either a short frame sync pulse (the same as the TP3020/21 CODECs) or a long frame sync pulse. Upon power initialization, the device assumes a short frame mode. In this mode, both frame sync pulses, FS

and

, must be one bit clock period long, with timing relation-

ships specified in

Figure 2

. With FSXhigh during a falling

edge of BCLK

, the next rising edge of BCLKXenables the

TRI-STATE output buffer, which will output the sign bit. The following seven rising edges clock out the remaining seven bits, and the next falling edge disables the D

output.

With FS

high during a falling edge of BCLKR(BCLKXin

synchronous mode), the next falling edge of BCLK

latches in the sign bit. The following seven falling edges latch in the seven remaining bits. All devices may utilize the short frame sync pulse in synchronous or asynchronous operating mode.

LONG FRAME SYNC OPERATION

To use the long (TP5116A/56 CODECs) frame mode, both the frame sync pulses, FS

and FSR, must be three or more

bit clock periods long, with timing relationships specified in

Figure 3

. Based on the transmit frame sync, FSX, the COMBO will sense whether short or long frame sync pulses are being used. For 64 kHz operation, the frame sync pulse must be kept low for a minimum of 160 ns. The D

TRI-

STATE output buffer is enabled with the rising edge of FS

or the rising edge of BCLKX, whichever comes later, and the first bit clocked out is the sign bit. The following seven BCLK

rising edges clock out the remaining seven bits. The

output is disabled by the falling BCLKXedge following

the eighth rising edge, or by FS

going low, whichever comes later. A rising edge on the receive frame sync pulse, FS

, will cause the PCM data at DRto be latched in on the

next eight falling edges of BCLK

(BCLKXin synchronous mode). All devices may utilize the long frame sync pulse in synchronous or asynchronous mode.

TRANSMIT SECTION

The transmit section input is an operational amplifier with provision for gain adjustment using two external resistors, see

Figure 4

. The low noise and wide bandwidth allow gains in excess of 20 dB across the audio passband to be realized. The op amp drives a unity-gain filter consisting of RC active pre-filter, followed by an eighth order switched-capacitor bandpass filter clocked at 256 kHz. The output of this filter directly drives the encoder sample-and-hold circuit. The A/D is of companding type according to m-law (TP3064) or A-law (TP3067) coding conventions. A precision voltage reference is trimmed in manufacturing to provide an input overload (t

MAX

) of nominally 2.5V peak (see

Page 4

Functional Description (Continued)

table of Transmission Characteristics). The FS

frame sync pulse controls the sampling of the filter output, and then the successive-approximation encoding cycle begins. The 8-bit code is then loaded into a buffer and shifted out through D

at the next FSXpulse. The total encoding delay will be approximately 165 ms (due to the transmit filter) plus 125 ms (due to encoding delay), which totals 290 ms. Any offset voltage due to the filters or comparator is cancelled by sign bit integration.

RECEIVE SECTION

The receive section consists of an expanding DAC which drives a fifth order switched-capacitor low pass filter clocked at 256 kHz. The decoder is A-law (TP3067) or m-law (TP3064) and the 5th order low pass filter corrects for the sin x/x attenuation due to the 8 kHz sample/hold. The filter is then followed by a 2nd order RC active post-filter with its output at VF

O. The receive section is unity-gain, but gain can be added by using the power amplifiers. Upon the occurrence of FS

, the data at the DRinput is clocked in

on the falling edge of the next eight BCLK

(BCLKX) peri-

ods. At the end of the decoder time slot, the decoding cycle begins, and 10 ms later the decoder DAC output is updated. The total decoder delay isE10 ms (decoder update) plus 110 ms (filter delay) plus 62.5 ms((/2 frame), which gives approximately 180 ms.

RECEIVE POWER AMPLIFIERS

Two inverting mode power amplifiers are provided for directly driving a matched line interface transformer. The gain of the first power amplifier can be adjusted to boost the

2.5V

peak output signal from the receive filter up to

3.3V peak

into an unbalanced 300X load, or

4.0V into an unbalanced 15 kX load. The second power amplifier is internally connected in unity-gain inverting mode to give 6 dB of signal gain for balanced loads.

Maximum power transfer to a 600X subscriber line termination is obtained by differentially driving a balanced transformer with a

2:1 turns ratio, as shown in

Figure 4

. A total peak power of 15.6 dBm can be delivered to the load plus termination.

ENCODING FORMAT AT D

OUTPUT

TP3064

TP3067

m-Law

A-Law

(Includes Even Bit Inversion)

Full-Scale 1 000000010101010

0V 1 111111111010101

Ð0 111111101010101

Full-Scale 0 000000000101010

Page 5

Absolute Maximum Ratings

If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications.

to GNDA 7V

VBBto GNDA

Voltage at any Analog Input

or Output V

0.3V to V

0.3V

Voltage at any Digital Input

or Output V

0.3V to GNDAb0.3V

Operating Temperature Range

25§Ctoa125§C

Storage Temperature Range

65§Ctoa150§C

Lead Temp. (Soldering, 10 sec.) 300§C

ESD (Human Body Model) J 1000V

ESD (Human Body Model) N 1500V

Latch-Up Immunity 100 mA on Any Pin

Electrical Characteristics Unless otherwise noted, limits printed in BOLD characters are guaranteed for V

5.0Vg5%, V

5.0Vg5%; T

0§Cto70§C by correlation with 100% electrical testing at T

25§C. All other limits are assured by correlation with other production tests and/or product design and characterization. All signals referenced to GNDA. Typicals specified at V

5.0V, V

5.0V, T

25§C.

Symbol Parameter Conditions Min Typ Max Units

POWER DISSIPATION (ALL DEVICES)

ICC0 Power-Down Current (Note) 0.5 1.5 mA

IBB0 Power-Down Current (Note) 0.05 0.3 mA

ICC1 Active Current VPIe0V; VFRO, VPOaand VPObunloaded 7.0 10.0 mA

IBB1 Active Current VPIe0V; VFRO, VPOaand VPObunloaded 7.0 10.0 mA

DIGITAL INTERFACE

Input Low Voltage 0.6 V

Input High Voltage 2.2 V

Output Low Voltage DX,I

3.2 mA 0.4 V

X,IL

3.2 mA, Open Drain 0.4 V

Output High Voltage DX,I

3.2 mA 2.4 V

Input Low Current GNDAsV

VIL, All Digital Inputs

10 10 mA

Input High Current V

10 10 mA

Output Current in High Impedance DX, GNDAsV

10 10 mA

State (TRI-STATE)

Note: I

CC0

and I

BB0

are measured after first achieving a power-up state.

Page 6

Electrical Characteristics (Continued)

Unless otherwise noted, limits printed in BOLD characters are guaranteed for V

5.0Vg5%, V

5.0Vg5%; T

0§Cto70§C by correlation with 100% electrical testing at T

25§C. All other limits are assured by correlation with other

production tests and/or product design and characterization. All signals referenced to GNDA. Typicals specified at V

5.0V, V

5.0V, T

25§C.

Symbol Parameter Conditions Min Typ Max Units

ANALOG INTERFACE WITH TRANSMIT INPUT AMPLIFIER (ALL DEVICES)

IIXA Input Leakage Current

2.5VsV

2.5V, VFXIaor VFXI

200 200 nA

RIXA Input Resistance

2.5VsV

2.5V, VFXIaor VFXI

10 MX

ROXA Output Resistance Closed Loop, Unity Gain 1 3 X

RLXA Load Resistance GS

10 kX

CLXA Load Capacitance GS

50 pF

VOXA Output Dynamic Range GSX,R

10 kX

2.8

2.8 V

AVXA Voltage Gain VFXIato GS

5000 V/V

FUXA Unity-Gain Bandwidth 1 2 MHz

VOSXA Offset Voltage

20 20 mV

VCMXA Common-Mode Voltage CMRRXAl60 dB

2.5 2.5 V

CMRRXA Common-Mode Rejection Ratio DC Test 60 dB

PSRRXA Power Supply Rejection Ratio DC Test 60 dB

ANALOG INTERFACE WITH RECEIVE FILTER (ALL DEVICES)

RORF Output Resistance Pin VFRO13X

RF Load Resistance VFRO

2.5V 10 kX

CLRF Load Capacitance Connect from VFRO to GNDA 25 pF

VOSRO Output DC Offset Voltage Measure from VFRO to GNDA

200 200 mV

ANALOG INTERFACE WITH POWER AMPLIFIERS (ALL DEVICES)

IPI Input Leakage Current

1.0VsVPIs1.0V

100 100 nA

RIPI Input Resistance

1.0VsVPIs1.0V 10 MX

VIOS Input Offset Voltage

25 25 mV

ROP Output Resistance Inverting Unity-Gain at 1 X

VPO

or VPO

Unity-Gain Bandwidth Open Loop (VPOb) 400 kHz

CLP Load Capacitance 100 pF

Gain from VPObto VPO

600X VPOato VPO

1 V/V

Level at VPO

1.77 Vrms

PSRR

Power Supply Rejection of VPObConnected to VPI V

or V

0 kHzb4 kHz 60 dB 4 kHz

50 kHz 36 dB

RLP Load Resistance Connect from VPOato VPO

600 X

Page 7

Timing Specifications

Unless otherwise noted, limits printed in BOLD characters are guaranteed for V

5.0Vg5%, V

5.0Vg5%, T

0§Cto70§C by correlation with 100% electrical testing at T

25§C. All other limits are assured by correlation with other

production tests and/or product design and characterization. All signals are referenced to GNDA. Typicals specified at V

5.0V, V

5.0V, T

25§C. All timing parameters are measured at V

2.0V and V

0.7V.

See Definitions and Timing Conventions section for test methods information.

Symbol Parameter Conditions Min Typ Max Units

1/t

Frequency of Master Clock 1.536 MHz

1.544 MHz

MCLK

and MCLK

2.048 MHz

Rise Time of Master Clock MCLKXand MCLK

50 ns

Fall Time of Master Clock MCLKXand MCLK

50 ns

Period Bit of Clock 485 488 15725 ns

Rise Time of Bit Clock BCLKXand BCLK

50 ns

Fall Time of Bit Clock BCLKXand BCLK

50 ns

WMH

Width of Master Clock High MCLKXand MCLK

160 ns

WML

Width of Master Clock Low MCLKXand MCLK

160 ns

SBFM

Set-Up Time from BCLKXHigh 100 ns to MCLK

Falling Edge

SFFM

Set-Up Time from FSXHigh Long Frame Only 100 ns to MCLK

Falling Edge

WBH

Width of Bit Clock High 160 ns

WBL

Width of Bit Clock Low 160 ns

HBFL

Holding Time from Bit Clock Long Frame Only 0 ns Low to Frame Sync

HBFS

Holding Time from Bit Clock Short Frame Only 0 ns High to Frame Sync

SFB

Set-Up Time for Frame Sync Long Frame Only 80 ns to Bit Clock Low

DBD

Delay Time from BCLKXHigh Loade150 pF plus 2 LSTTL Loads 0 180 ns to Data Valid

DBTS

Delay Time to TSXLow Loade150 pF plus 2 LSTTL Loads 140 ns

DZC

Delay Time from BCLKXLow to 50 165 ns Data Output Disabled

DZF

Delay Time to Valid Data from C

0 pF to 150 pF 20 165 ns

or BCLKX, Whichever

Comes Later

SDB

Set-Up Time from DRValid to 50 ns BCLK

R/X

Low

HBD

Hold Time from BCLK

R/X

Low to 50 ns

Invalid

Set-Up Time from FS

X/R

to Short Frame Sync Pulse (1 Bit Clock 50 ns

BCLK

X/R

Low Period Long)

Hold Time from BCLK

X/R

Low Short Frame Sync Pulse (1 Bit Clock 100 ns

to FS

X/R

Low Period Long)

HBFI

Hold Time from 3rd Period of Long Frame Sync Pulse (from 3 to 8 Bit 100 ns Bit Clock Low to Frame Sync Clock Periods Long) (FS

or FSR)

WFL

Minimum Width of the Frame 64k Bit/s Operating Mode 160 ns Sync Pulse (Low Level)

Page 8

Timing Diagrams

TL/H/5070– 3

FIGURE 2. Short Frame Sync Timing

Page 9

Timing Diagrams (Continued)

TL/H/5070– 4

FIGURE 3. Long Frame Sync Timing

Page 10

Transmission Characteristics

Unless otherwise noted, limits printed in BOLD characters are guaranteed for V

5.0Vg5%, V

5.0Vg5%; T

0§Cto70§C by correlation with 100% electrical testing at T

25§C. All other limits are assured by correlation with other

production tests and/or product design and characterization. GNDA

0V, fe1.02 kHz, V

0 dbm0, transmit input amplifier

connected for unity gain non-inverting. Typicals specified at V

5.0V, V

5.0V, T

25§C.

Symbol Parameter Conditions Min Typ Max Units

AMPLITUDE RESPONSE

Absolute Levels Nominal 0 dBm0 Level is 4 dBm (Definition of (600X) nominal gain) 0 dBm0 1.2276 Vrms

MAX

Virtual Decision Value Defined Max Transmit Overload Level per CCITT Rec. G711 TP3064 (3.17 dBm0) 2.501 V

TP3067 (3.14 dBm0) 2.492 V

Transmit Gain, Absolute T

25§C, V

5V, V

0.15 0.15 dB

Transmit Gain, Relative to G

fe16 Hz

40 dB

50 Hz

30 dB

60 Hz

26 dB

200 Hz

1.8

0.1 dB

300 Hz-3000 Hz

0.15 0.15 dB

3300 Hz

0.35 0.05 dB

3400 Hz

0.7 0 dB

fe4000 Hz

14 dB

4600 Hz and Up, Measure

32 dB

Response from 0 Hz to 4000 Hz

XAT

Absolute Transmit Gain Variation Relative to G

0.1 0.1 dB

with Temperature

XAV

Absolute Transmit Gain Variation Relative to G

0.05 0.05 dB

with Supply Voltage

XRL

Transmit Gain Variations with Sinusoidal Test Method Level Reference Level

10 dBm0

40 dBm0 toa3 dBm0

0.2 0.2 dB

50 dBm0 tob40 dBm0

0.4 0.4 dB

55 dBm0 tob50 dBm0

1.2 1.2 dB

Receive Gain, Absolute T

25§C, V

5V, V

0.15 0.15 dB

Input

Digital Code Sequence

for 0 dBm0 Signal

Receive Gain, Relative to G

fe0 Hz to 3000 Hz

0.15 0.15 dB

3300 Hz

0.35 0.05 dB

3400 Hz

0.7 0 dB

4000 Hz

14 dB

RAT

Absolute Receive Gain Variation Relative to G

0.1 0.1 dB

with Temperature

RAV

Absolute Receive Gain Variation Relative to G

0.05 0.05 dB

with Supply Voltage

RRL

Receive Gain Variations with Sinusoidal Test Method; Reference Level Input PCM Code Corresponds to an

Ideally Encoded

10 dBm0 Signal

PCM Level

40 dBm0 toa3 dBm0

0.2 0.2 dB

PCM Level

50 dBm0 tob40 dBm0

0.4 0.4 dB

PCM Level

55 dBm0 tob50 dBm0

1.2 1.2 dB

Receive Filter Output at VFRORL

10 kX

2.5 2.5 V

Page 11

Transmission Characteristics (Continued)

Unless otherwise noted, limits printed in BOLD characters are guaranteed for V

5.0Vg5%, V

5.0Vg5%; T

0§Cto70§C by correlation with 100% electrical testing at T

25§C. All other limits are assured by correlation with other

production tests and/or product design and characterization. GNDA

0V, fe1.02 kHz, V

0 dbm0, transmit input amplifier

connected for unity gain non-inverting. Typicals specified at V

5.0V, V

5.0V, T

25§C.

Symbol Parameter Conditions Min Typ Max Units

ENVELOPE DELAY DISTORTION WITH FREQUENCY

Transmit Delay, Absolute fe1600 Hz 290 315 ms

Transmit Delay, Relative to D

fe500 Hzb600 Hz 195 220 ms f

600 Hzb800 Hz 120 145 ms

800 Hzb1000 Hz 50 75 ms

1000 Hzb1600 Hz 20 40 ms

1600 Hzb2600 Hz 55 75 ms

2600 Hzb2800 Hz 80 105 ms

fe2800 Hzb3000 Hz 130 155 ms

Receive Delay, Absolute fe1600 Hz 180 200 ms

Receive Delay, Relative to D

fe500 Hzb1000 Hz

25 ms

1000 Hzb1600 Hz

20 ms

1600 Hzb2600 Hz 70 90 ms

2600 Hzb2800 Hz 100 125 ms

2800 Hzb3000 Hz 145 175 ms

NOISE

Transmit Noise, C Message TP3064 (Note 1) 12 15 dBrnC0 Weighted

Transmit Noise, Psophometric TP3067 (Note 1)

67 dBm0p

Weighted

Receive Noise, C Message PCM Code Equals Alternating Weighted Positive and Negative Zero

TP3064 8 11 dBrnCO

Receive Noise, Psophometric PCM Code Equals Positive Weighted Zero

TP3067

79 dBm0p

Noise, Single Frequency fe0 kHz to 100 kHz, Loop Around

53 dBm0

Measurement, VF

0 Vrms

PPSR

Positive Power Supply Rejection, V

5.0 V

100 mVrms

Transmit fe0 kHzb50 kHz (Note 2) 40 dBC

NPSR

Negative Power Supply Rejection, V

5.0 V

100 mVrms

Transmit f

0 kHzb50 kHz (Note 2) 40 dBC

PPSR

Positive Power Supply Rejection, PCM Code Equals Positive Zero Receive V

5.0 V

100 mVrms

Measure VF

0Hzb4000 Hz 38 dBC

4 kHzb50 kHz 25 dB

NPSR

Negative Power Supply Rejection, PCM Code Equals Positive Zero Receive V

5.0 V

100 mVrms

Measure VF

0Hzb4000 Hz 40 dBC

4 kHzb25 kHz 40 dB

25 kHzb50 kHz 36 dB

SOS Spurious Out-of-Band Signals 0 dBm0, 300 Hzb3400 Hz Input

at the Channel Output PCM Code Applied at DR

Measure Individual Image Signals at VF

4600 Hz–7600 Hz

32 dB

7600 Hz–8400 Hz

40 dB

8400 Hz–100,000 Hz

32 dB

Page 12

Transmission Characteristics (Continued)

Unless otherwise noted, limits printed in BOLD characters are guaranteed for V

5.0Vg5%, V

5.0Vg5%; T

0§Cto70§C by correlation with 100% electrical testing at T

25§C. All other limits are assured by correlation with other

production tests and/or product design and characterization. GNDA

0V, fe1.02 kHz, V

0 dbm0, transmit input amplifier

connected for unity gain non-inverting. Typicals specified at V

5.0V, V

5.0V, T

25§C.

Symbol Parameter Conditions Min Typ Max Units

DISTORTION

STD

Signal to Total Distortion Sinusoidal Test Method (Note 3)

STD

Transmit or Receive Levele3.0 dBm0 33 dBC Half-Channel

0 dBm0 tob30 dBm0 36 dBC

40 dBm0 XMT 29 dBC

RCV 30 dBC

55 dBm0 XMT 14 dBC

RCV 15 dBC

SFD

Single Frequency Distortion,

46 dB

Transmit

SFD

Single Frequency Distortion,

46 dB

Receive

IMD Intermodulation Distortion Loop Around Measurement,

41 dB

4 dBm0 tob21 dBm0, Two Frequencies in the Range 300 Hz

3400 Hz

CROSSTALK

X-R

Transmit to Receive Crosstalk fe300 Hzb3000 Hz

Quiet PCM Code

90b75 dB

R-X

Receive to Transmit Crosstalk fe300 Hzb3000 Hz, VFXIe0V

90b70 dB

(Note 2)

POWER AMPLIFIERS

VOPA Maximum 0 dBm0 Level Balanced Load, RLConnected Between

(Better than

0.1 dB Linearity over VPOaand VPOb.

the Range

10 dBm0 toa3 dBm0) R

600X 3.3 Vrms

1200X 3.5 Vrms

S/D

Signal/Distortion R

600X 50 dB

Note 1: Measured by extrapolation from the distortion test result atb50 dBm0.

Note 2: PPSR

, NPSRX, and CT

RbX

are measured with ab50 dBm0 activation signal applied to VFXIa.

Note 3: TP3064 is measured using C message weighted filter. TP3067 is measured using psophometric weighted filter.

Page 13

Applications Information

POWER SUPPLIES

While the pins of the TP3060 family are well protected against electrical misuse, it is recommended that the standard CMOS practice be followed, ensuring that ground is connected to the device before any other connections are made. In applications where the printed circuit board may be plugged into a ‘‘hot’’ socket with power and clocks already present, an extra long ground pin in the connector should be used.

All ground connections to each device should meet at a common point as close as possible to the GNDA pin. This

minimizes the interaction of ground return currents flowing through a common bus impedance. 0.1 mF supply decoupling capacitors should be connected from this common ground point to V

and VBB, as close to the device as

possible.

For best performance, the ground point of each CODEC/ FILTER on a card should be connected to a common card ground in ‘‘STAR’’ formation, rather than via a ground bus. This common ground point should be decoupled to V

and

with 10 mF capacitors.

Note: See Application Note 370 for further details

Typical Asynchronous Application

TL/H/5070– 5

Note 1: Transmit gaine20clog

R1aR2

,(R1aR2)t10 kX

Note 2: Receive gain

20clog

2cR3

,R4t10 kX

FIGURE 4

Page 14

Definitions and Timing Conventions

DEFINITIONS

VIHis the d.c. input level above which an input level is guaranteed to appear as a logical one. This parameter is to be measured by performing a functional test at reduced clock speeds and nominal timing, (i.e. not minimum setup and hold times or output strobes), with the high level of all driving signals set to V

and maximum supply voltages applied to the device

VILis the d.c. input level below which an input level is guaranteed to appear as a logical zero to the device. This parameter is measured in the same manner as V

but with all driving

signal low levels set to V

and minimum supply voltages applied to the device.

VOHis the minimum d.c. output level to which an output placed in a logical one state will converge when loaded at the maximum specified load current.

VOLis the maximum d.c. output level to which an output placed in a logical zero state will converge when loaded at the maximum specified load current.

Threshold Region The threshold region is the range of

input voltages between V

and VIH.

Valid Signal A signal is Valid if it is in one of the

valid logic states, (i.e. above V

below V

). In timing specifiations, a signal is deemed valid at the instant it enters a valid state.

Invalid Signal A signal is Invalid if it is not in a valid

logic state, i.e. when it is in in the threshold region between V

and VIH. In timing specifications, a signal is deemed Invalid at the instant it enters the threshold region.

TIMING CONVENTIONS

For the purposes of this timing specification, the following conventions apply:

Input Signals All input signals may be characterized

as: V

0.4V, V

2.4V, t

10 ns,

10 ns.

Period The period of clock signal is

designated as t

Pxx

where xx represents the mnemonic of the clock signal being specified.

Rise Time Rise times are designated as t

Ryy

, where yy represents a mnemonic of the signal whose rise time is being specified. t

Ryy

is measured from VILto

Fall Time Fall times are designated as t

Fyy

, where yy represents a mnemonic of the signal whose fall time is being specified. t

Fyy

is measured from VIHto

Pulse Width High The high pulse width is designated as

WzzH

, where zz represents the mnemonic of the input or output signal whose pulse width is being specified. High pulse widths are measured from V

to VIH.

Pulse Width Low The low pulse width is designated as

WzzL

, where zz represents the mnemonic of the input or output signal whose pulse width is being specified. Low pulse widths are measured from V

to VIL.

Setup Time Setup times are designated as t

Swwxx

, where ww represents the mnemonic of the input signal whose setup time is being specified relative to a clock or strobe input represented by mnemonic xx. Setup times are measured from the ww Valid to xx Invalid.

Hold Time Hold times are designated as t

Hxxww

, where ww represents the mnemonic of the input signal whose hold time is being specified relative to a clock or strobe input represented by mnemonic xx. Hold times are measured from xx Valid to ww Invalid.

Delay Time Delay times are designated as t

Dxxyy

Hi to Low, where xx represents the mnemonic of the input reference signal and yy represents the mnemonic of the output signal whose timing is being specified relative to xx. The mnemonic may optionally be terminated by an H or L to specify the high going or low going transition of the output signal. Maximum delay times are measured from xx Valid to yy Valid. Minimum delay times are measured from xx Valid to yy Invalid. This parameter is tested under the load conditions specified in the Conditions column of the Timing Specifications section of this data sheet.

Page 15

Page 16

Physical Dimensions inches (millimeters)

Cavity Dual-In-Line Package (J)

Order Number TP3064J or TP3067J

NS Package Number J20A

Molded Small Outline Package (WM)

Order Number TP3064WM or TP3067WM

NS Package Number M20B

Page 17

Physical Dimensions inches (millimeters) (Continued)

Molded Dual-In-Line Package (N)

Order Number TP3064N or TP3067N

NS Package Number N20A

Page 18

TP3064, TP3067 ‘‘Enhanced’’ Serial Interface CMOS CODEC/Filter COMBO

Physical Dimensions inches (millimeters) (Continued) Lit.

113975

Plastic Chip Carrier (V)

Order Number TP3064V or TP3067V

NS Package Number V20A

LIFE SUPPORT POLICY

NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or 2. A critical component is any component of a life systems which, (a) are intended for surgical implant support device or system whose failure to perform can into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life failure to perform, when properly used in accordance support device or system, or to affect its safety or with instructions for use provided in the labeling, can effectiveness. be reasonably expected to result in a significant injury to the user.

National Semiconductor National Semiconductor National Semiconductor National Semiconductor Corporation Europe Hong Kong Ltd. Japan Ltd.

1111 West Bardin Road Fax: (

49) 0-180-530 85 86 13th Floor, Straight Block, Tel: 81-043-299-2309 Arlington, TX 76017 Email: cnjwge@tevm2.nsc.com Ocean Centre, 5 Canton Rd. Fax: 81-043-299-2408 Tel: 1(800) 272-9959 Deutsch Tel: (

49) 0-180-530 85 85 Tsimshatsui, Kowloon Fax: 1(800) 737-7018 English Tel: (

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Fran3ais Tel: (

49) 0-180-532 93 58 Tel: (852) 2737-1600

Italiano Tel: (

49) 0-180-534 16 80 Fax: (852) 2736-9960

National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.

Datasheet TP3067V-X, TP3067WM, TP3067V, TP3067N Datasheet (NATIONAL SEMICONDUCTOR)

Specifications and Main Features

Frequently Asked Questions

User Manual