Datasheet TLE 6244X Datasheet (lnfineon)

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18 Channel Smart Lowside Switch

ASSP for Powertrain

Final Data Sheet

Features

• Short Circuit Protection

• Overtemperature Protection

• Overvoltage Protection

• 16 bit Serial Data Input and Diagnostic Output
(2 bit/chan. acc. SPI Protocol)

• Direct Parallel Control of 16 channels for PWM
Applications

• Low Quiescent Current

• Compatible with 3.3V Microcontrollers

• Electrostatic discharge (ESD) Protection

TLE 6244X

P-MQFM 64-10

Ordering Code: Q67007-A9613

General description

18-fold Low-Side Switch (0.35 Ω to 1 Ω) in Smart Power Technology (SPT) with a Serial Pe-

ripheral Interface (SPI) and 18 open drain DMOS output stages. The TLE6244X is protected
by embedded protection functions and designed for automotive and industrial applications.
The output stages are controlled via SPI Interface. Additionally 16 of the 18 channels can be
controlled direct in parallel for PWM applications. Therefore the TLE6244X is particularly
suitable for engine management and powertrain systems.

VS

V

IN1

IN2

IN15

IN16 as Ch. 1

SCLK

SI

as Ch. 1

as Ch. 1

as Ch. 1

as Ch. 1

as Ch. 1

as Ch. 1

Serial Interface

SPI

LOGIC

16

1

16

Output Control

Buffer

Protection
Functions

Output Stage

BB

OUT1

OUT18

SO

GND

Final Data Sheet 1 V4.2, 2003-08-29

1. Description

1.1 Short Description

This circuit is available in MQFP64 package or as chip.

1.1.1 Features of the Power Stages

TLE 6244X

Nominal Current

OUT1, 2, 5, 6

OUT3, OUT4

OUT7, OUT8

OUT9, OUT10

OUT11...OUT14

OUT15, OUT16

OUT17, OUT18 *)

*) only serial control possible (via SPI)

Parallel connection of power stages is possible (see 1.13)
Internal short-circuit protection
Phase relation: non-inverting (exception: IN8->OUT8 is inverting)

1.1.2 Diagnostic Features

The following types of error can be detected:

Short-circuit to U
Short-circuit to ground (SCG)
Open load (OL)

Overtemperature (OT)
Individual detection for each output.
Serial transmission of the error code via SPI.

R

2.2A 400mΩ - 70V

2.2A 380mΩ -70V

1.1A 780mΩ -45V

2.2A 380mΩ X 45V

2.2A 380mΩ -45V

3.0A 280mΩ X 45V

1.1A 780mΩ X45V

(SCB)

Batt

on,max

at TJ = 25°C

static current limita-

tion enabled by SPI

Clamping

1.1.3 VDD-Monitoring

Low signal at pin ABE
Exception: If OUT8 is controlled by IN8, OUT8 will only be switched off by the overvoltage
detection and not by undervoltage detection.
The state of VDD can be read out via SPI.

1.1.4 µsec-bus

Alternatively to the parallel and SPI control of the power stages, a high speed serial bus inter­face can be configured as control of the power stages OUT1...OUT7 and OUT9...OUT16.

1.1.5 Power Stage OUT8

OUT8 can be controlled by SPI or by the pin IN8 only. When controlled by IN8 this power stage
is functional if the voltage at the pin VDD is above 3,5V.
SPI mode the power stage is fully supervised by the VDD-monitor.

and shut-off of the power stages if VDD is out of the permitted range.

OUT8 will not be reset by RST. In

Final Data Sheet 2 V4.2, 2003-08-29

1.2 Block Diagram

IN1

IN2

IN3

IN4

fault

diagnostics

SPI

UBatt

2,2A / 70V

2,2A / 70V

2,2A / 70V

2,2A / 70V

TLE 6244X

OUT1

OUT2

OUT3

OUT4

IN5

IN6

IN7

IN8

IN9

IN10

IN11

IN12

IN13

IN14

IN15

IN16

control only via SPI possible

control only via SPI possible

IN6 IN7 IN16

µsec - Bus

2,2A / 70V

2,2A / 70V

1.1A / 45V

1.1A / 45V

2,2A / 45V

2,2A / 45V

2,2A / 45V

2,2A / 45V

2,2A / 45V

2,2A / 45V

3,0A / 45V

3,0A / 45V

1.1A / 45V

1.1A / 45V

VDD

OUT5

OUT6

OUT7

OUT8

OUT9

OUT10

OUT11

OUT12

OUT13

OUT14

OUT15

OUT16

OUT17

OUT18

SCK
SI

SS

SPI Interface

SO

RST

GND1...8

VDD-Moni-

toring

GND_ABE

VDD

ABE

Final Data Sheet 3 V4.2, 2003-08-29

TLE 6244X

1.3 Description of the Power Stages

OUT1... OUT6

6 non-inverting low side power switches for nominal currents up to 2.2A. Control is possible by
input pins, by the µsec-bus or via SPI. For T

below 400mΩ.

An integrated zener diode limits the output voltage to 70V typically.

A protection for inverse current is implemented for OUT1... OUT4 for use as stepper-motor con­trol.

= 25°C the on-resistance of the power switches is

J

OUT9... OUT14

6 non-inverting low side power switches for nominal currents up to 2.2A. Control is possible by
input pins, by the µsec-bus or via SPI. For T

below 380mΩ.

An integrated zener diode limits the output voltage to 45V typically.

= 25°C the on-resistance of the power switches is

J

OUT15, OUT16

2 non-inverting low side power switches for nominal currents up to 3.0A. Control is possible by
input pins, by the µsec-bus or via SPI. For T

below 280mΩ.

An integrated zener diode limits the output voltage to 45V typically.

= 25°C the on-resistance of the power switches is

J

OUT7, OUT8, OUT17, OUT18

4 low side power switches for nominal currents up to 1100mA. Stage 7 is non-inverting, Stage 8
is inverting (IN8 = ‘1’ => OUT8 is active). For the output OUT7 control is possible by the input pin,
by the µsec-bus or via SPI, OUT8 is controlled by the input pin IN8 or via SPI, for the outputs
OUT17 and OUT18 control is only possible via SPI. For T

switches is below 780mΩ.

An integrated zener diode limits the output voltage to 45V typically.

In order to increase the switching current or to reduce the power dissipation parallel connection
of power stages is possible (for additional information see 1.13).
The power stages are short-circuit proof:
Power stages OUT1...OUT8, OUT11.14: In case of overload (SCB) they will be turned off after a
given delay time. During this delay time the output current is limited by an internal current control
loop.
Power stages OUT9, OUT10, OUT15...OUT18:
In case of SCB these power stages can be configured for a shut-down mode or for static current
limitation. In the shut down mode while SCB they will behave like OUT1..8 or OUT11..14.
In case of static current limitation and SCB the current is limited and the corresponding bit com­bination is set (early warning) after a given delay time. They will not be turned off. If this condition
leads to an overtemperature condition, the output will be set into a low duty cycle PWM (selective
thermal shut- down with restart) to prevent critical chip temperature.

There are 3 possibilities to turn the power stages on again:

- turn the power stage off and on, either via serial control (SPI) or via parallel control (input pin,
except outputs OUT17 and OUT18) or by the µsec-bus (except OUT8, OUT17,OUT18)

- applying a reset signal.

- sending the instruction “del_dia” by the SPI-interface
The VDD-monitoring locks all power stages, except OUT8 for access by the IN8 input. OUT8 is
locked by an internal threshold of 3,5V maximum when controlled by IN8. Otherwise OUT8 is
locked by the VDD-monitor.

= 25°C the on-resistance of the power

J

Final Data Sheet 4 V4.2, 2003-08-29

All low side switches are equipped with fault diagnostic functions:

TLE 6244X

- short-circuit to U

: (SCB) can be detected if switches are turned on

Batt

- short-circuit to ground: (SCG) can be detected if switches are turned off

- open load: (OL) can be detected if switches are turned off

- overtemperature: (OT) will only be detected if switches are turned on

The fault conditions SCB, SCG, OL and OT will not be stored until an integrated filtering time is
expired (please note for PWM application). If, at one output, several errors occur in a sequence,
always the last detected error will be stored (with filtering time). All fault conditions are encoded
in two bits per switch and are stored in the corresponding SPI registers. Additionally there are
two central diagnostic bits: one specially for OT and one for fault occurrence at any output.

The registers can be read out via SPI. After each read out cycle the registers have to be cleared
by the DEL_DIA command.

1.3.1 Power Stage OUT8 (Condensed Description)

1.3.1.1 Control of OUT8 and VDD-Monitoring
OUT8 can be controlled by SPI or by the pin IN8 only, control by µs-bus is not possible. When
controlled by IN8 this power stage is functional if the voltage at the pin VDD is above 3,5V. In
SPI mode the power stage is fully supervised by the VDD-monitor.
If OUT8 is controlled by IN8, OUT8 will only be switched off by the overvoltage detection and
not by undervoltage detection.

1.3.1.2 Phase Relation IN8 - OUT8
The phase relation IN8 -> OUT8 is inverting.
OUT8 is active if IN8 is set to logic '1' (high level, see 3.4.2 ) in case of parallel access.
On executing the read instruction on RD_INP1/2 the inverted status of IN8 is read back.

1.3.1.3 Reset / Power Stage Diagnostics
If OUT8 is controlled by IN8, OUT8 will not be reseted by RST.
After reset parallel control (by IN8) is active for OUT8.
If UVDD < 4.5V errors are not stored because of the active RST of the external Regulator. Nev­ertheless
OUT8 is protected against overload.

1.3.1.4 Input Current
The control input IN8 has an internal pull-down current source. Thus the input currents I IN8
are positive (flow into the pin).

1.3.1.5 On Resistance
For OUT8 and 3.5V < UVDD < 4.5V R on increases (see 3.8.5).

1.3.1.6 Parallel Connection of Power Stages
Parallel connection of power stages with OUT8 and parallel control is prohibited (inverting
input IN8). Control via SPI is possible. See 1.13.

Final Data Sheet 5 V4.2, 2003-08-29

1.4 Pinout

Function Pin Pin Number
Input 1 IN1 7
Input 2 IN2 46
Input 3 IN3 10
Input 4 IN4 43
Input 5 IN5 6
Input 6 or FDA IN6 63
Input 7 or SSY IN7 61
Input 8 IN8 22
Input 9 IN9 20
Input 10 IN10 33
Input 11 IN11 5
Input 12 IN12 48
Input 13 IN13 13
Input 14 IN14 40
Input 15 IN15 1
Input 16 or FCL IN16 62

TLE 6244X

Output 1 OUT1 8
Output 2 OUT2 45
Output 3 OUT3 9
Output 4 OUT4 44
Output 5_1 OUT5_1 16
Output 5_2 OUT5_2 17
Output 6_1 OUT6_1 37
Output 6_2 OUT6_2 36
Output 7 OUT7 60
Output 8 OUT8 57
Output 9_1 OUT9_1 18
Output 9_2 OUT9_2 19
Output 10_1 OUT10_1 35
Output 10_2 OUT10_2 34
Output 11 OUT11 4
Output 12 OUT12 49
Output 13_1 OUT13_1 14
Output 13_2 OUT13_2 15
Output 14_1 OUT14_1 39
Output 14_2 OUT14_2 38
Output 15_1 OUT15_1 2
Output 15_2 OUT15_2 3
Output 16_1 OUT16_1 51
Output 16_2 OUT16_2 50
Output 17 OUT17 25
Output 18 OUT18 28

(Note: OUTxy_1 and OUTxy_2 have to be connected externally!)

Slave Select SS
Serial Output SO 53
Serial Input SI 55
SPI Clock SCK 54

56

Final Data Sheet 6 V4.2, 2003-08-29

Supply Voltage VDD VDD 47
Supply Voltage U

B

att

Ubatt 23

GND1 GND1 26
GND2 GND2 27
GND3 GND3 58
GND4 GND4 59
GND5 GND5 11
GND6 GND6 12
GND7 GND7 42
GND8 GND8 41

TLE 6244X

Sense Ground VDD-Monitoring GND_ABE
In-/Output VDD-Monitoring ABE
Reset (low active) RST

29
30
31

not connected nc 21, 24, 32, 52, 64

64

63

62

61

60

59

IN16 / FCL22IN7 / SSY23OUT7

IN6 / FDA

nc

IN15

1 52

OUT15_1

2

OUT15_2

3

OUT11

4

IN11

5

IN5

6

IN1

7

OUT1

8

OUT3

9

IN3

10

GND5

11

GND6

12

IN13

13

OUT13_1

14

OUT13_2

15

OUT5_1

16

OUT5_2

17

OUT9_1

18

OUT9_2

19

IN9

20

GND4

HiQUAD64

58

5756555453

GND3

OUT8

S
S GND_ABE

SO

SCK

SI

nc

OUT16_1

OUT16_2

OUT12

IN12

VDD

IN2

OUT2

OUT4

IN4

GND7

GND8

IN14

OUT14_1

OUT14_2

OUT6_1

OUT6_2

OUT10_1

OUT10_2

IN10

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

OUT17

Ubatt

IN8

nc

21

GND1

n.c.

24

25

26

OUT18

GND2

2728293031

ABE

RST

nc

32

Final Data Sheet 7 V4.2, 2003-08-29

1.5 Function of Pins

IN1 to IN16 Control inputs of the power stages

Internal pull-up current sources (exception: IN8 with pull-down current
source)

FCL Clock for the µsec-bus (pin shared with IN16)
FDA Data for the µsec-bus (pin shared with IN6)
SSY Strobe and Synchronisation for the µsec-bus (pin shared with IN7)

OUT1 to OUT18 Outputs of the power switches

Short-circuit proof

Low side switches
Limitation of the output voltage by zener diodes

VDD Supply voltage 5V

TLE 6244X

UBatt Supply voltage U

Batt

Pin must not be left open but has to be connected either to U
(e.g. in commercial vehicles)

GND1 to GND8 Ground pins

Ground pins for the power stages (see 2.4)

Ground reference of all logic signals is GND1/2

RST

Reset

Active low
Locks all power switches regardless of their input signals (except OUT8)
Clears the fault registers
Resets the µsec-bus interface registers

ABE

In-/Output VDD-Monitoring

Active low
Output pin for the VDD-Monitoring
Input pin for the shut-off signal coming from the supervisor

or to VDD

Batt

GND_ABE

SI, SO, SCK, SS

Sense ground VDD-Monitoring

SPI Interface

Final Data Sheet 8 V4.2, 2003-08-29

TLE 6244X

1.6 SPI Interface

The serial SPI interface establishes a communication link between TLE6244X and the systems mi­crocontroller. TLE6244X always operates in slave mode whereas the controller provides the mas­ter function. The maximum baud rate is 5 MBaud.
The TLE6244X is selected by the SPI master by an active slave select signal at SS
two bits of the SPI instruction.SI is the data input (Slave In), SO the data output (Slave Out). Via
SCK (Serial Clock Input) the SPI clock is provided by the master.
In case of inactive slave select signal (High) the data output SO goes into tristate.

Block Diagram:

and by the first

SS

SCK

SI

SO

Power Stages 1..18

SCON_REG1...3

Shift Register

Power Stages 1..16

MUX_REG1,2

SPI Control:

State Machine
Clock Counter
Control Bits
Parity Generator

STATCON_REG

VDD-Monitoring

Power Stages 1..18

Final Data Sheet 9 V4.2, 2003-08-29

DIA_REG1...5

TLE 6244X

A SPI communication always starts with a SPI instruction sent from the controller to TLE6244X.
During a write cycle the controller sends the data after the SPI instruction, beginning with the MSB.
During a reading cycle, after having received the SPI instruction, TLE6244X sends the correspond­ing data to the controller, also starting with the MSB.

SPI Command/Format:

MSB

76543210

0 0 INSTR4 INSTR3 INSTR2 INSTR1 INSTR0 INSW

Bit Name Description

7,6 CPAD1,0 Chip Address (has to be ‘0’, ‘0’)

5-1 INSTR (4-0) SPI instruction (encoding)

0 INSW Parity of the instruction

Characteristics of the SPI Interface:

1) If the slave select signal at SS

is High, the SPI-logic is set on default condition, i.e. it expects

an instruction.

2) If the 5V-reset (RST
The VDD monitoring (ABE

) is active, the SPI output SO is switched into tristate.

) has no influence on the SPI interface.

3) Verification byte:
Simultaneously to the receipt of an SPI instruction TLE6244X transmits a verification
byte via the output SO to the controller. This byte indicates regular or irregular operation of
the SPI. It contains an initial bit pattern and a flag indicating an invalid instruction of the previous

access.

4) On a read access the databits at the SPI input SI are rejected. On a writing access or after
the DEL_DIA instruction the TLE6244XTLE6244X sets the SPI output SO to low after sending

the verification byte. If more than 16 bits are received the rest of the frame is rejected.

5) Invalid instruction/access:
An instruction is invalid, if one of the following conditions is fulfilled:

- an unused instruction code is detected (see tables with SPI instructions)

- in case the previous transmission is not completed in terms of internal data processing

- number of SPI clock pulses counted during active SS

differs from exactly 16 clock pulses.
A write access and the instruction DEL_DIA is internally suppressed (i.e internal
registers will not be affected) in all cases where at the rising (inactive) edge of SS

the
number of falling edges applied to the SPI input SCK during the access is not equal to 16.
A write access is also internally suppressed (i.e internal registers will not be affected) if
at the rising (inactive) edge of SS

a 17th bit is submitted (SCK=‘1’).

After the bits CPAD1,0 and INSTR (4-0) have been sent from the microcontroller
TLE6244X is able to check if the instruction code is valid. If an invalid instruction is
detected, any modification on a register of TLE6244X is not allowed and the data
byte ‘FFh’ is transmitted after having sent the verification byte. If a valid read instruction is
detected the content of the corresponding register is transmitted to the controller after having
sent the verification byte (even if bit INSW afterwards is wrong). If a valid write instruction is

Final Data Sheet 10 V4.2, 2003-08-29

TLE 6244X

detected the data byte ’00h’ is transmitted to the controller after having sent the verification
byte (even if bit INSW afterwards is wrong) but modifications on any register of TLE6244 are

not allowed until bit INSW is valid, too.

If an invalid instruction is detected bit TRANS_F in the following verification byte is set to
’High’. This bit must not be cleared before it has been sent to the microcontroller.

6) If TLE6244X and additional IC’s are connected to one common slave select, they are
distinguished by the chip address (CPAD1, CPAD0). If an IC with 32bit-transmission-format is
selected, TLE6232 must not be activated, even if slave select is set to ’low’ and
the first two bits of the third byte of the 32bit-transmission are identical to the chip address
of TLE6244X.
During the transmission of CPAD1 and CPAD0 the data output SO remains in tristate (see
timing diagram of the SPI in chapter 3.9. ).

SPI access format:

SS

SO

WRITE-access (16bit)

8 bit command + 8bit data

SS

SI

SPI instruction

MSB

Check byte 00 00 00 00

ZZ + 6bit

MSB

Data 8bit

SI

MSB

SO

Z=tristate

READ-access (16bit)

8 bit command + 8bit data

SPI instruction

Check byte

ZZ + 6bit

XX XX XX XX

Data 8bit

MSB

Verification byte:

MSB

76543210

ZZ10101TRANS_F

Bit Name Description

0 TRANS_F Bit = 1: error detected during previous transfer

Bit = 0: previous transfer was recognised as valid
State after reset: 0

1 Fixed to High

2 Fixed to Low

3 Fixed to High

4 Fixed to Low

5 Fixed to High

6 send as high impedance

7 send as high impedance

Final Data Sheet 11 V4.2, 2003-08-29

SPI Instructions

SPI Instruction Encoding Description

TLE 6244X

bit 7,6
CPAD1,0

bit 5,4,3,2,1
INSTR(4...0)

Parity

RD_IDENT1 00 00000 0 read identifier 1

RD_IDENT2 00 00001 1 read identifier2

WR_STATCON 00 10001 0 write into STATCON_REG

WR_MUX1 00 10010 0 write into MUX_REG1

WR_MUX2 00 10011 1 write into MUX_REG2

WR_SCON1 00 10100 0 write into SCON_REG1

WR_SCON2 00 10101 1 write into SCON_REG2

WR_SCON3 00 10110 1 write into SCON_REG3

WR_CONFIG 00 10111 0 write into CONFIG

RD_MUX1 00 00010 1 read MUX_REG1

RD_MUX2 00 00011 0 read MUX_REG2

RD_SCON1 00 00100 1 read SCON_REG1

RD_SCON2 00 00101 0 read SCON_REG2

RD_SCON3 00 00110 0 read SCON_REG3

RD_STATCON 00 00111 1 read STATCON_REG

DEL_DIA 00 11000 0 resets the 5 diagnostic registers

DIA_REG

RD_DIA1 00 01000 1 read DIA_REG1

RD_DIA2 00 01001 0 read DIA_REG2

RD_DIA3 00 01010 0 read DIA_REG3

RD_DIA4 00 01011 1 read DIA_REG4

RD_DIA5 00 01100 0 read DIA_REG5

RD_CONFIG 00 01101 1 read CONFIG

RD_INP1 00 01110 1 read INP_REG1

RD_INP2 00 0 1111 0 read I N P_REG 2

all others no function

Final Data Sheet 12 V4.2, 2003-08-29

TLE 6244X

1.6.1 Serial/Parallel Control

Serial/Parallel Control of the Power Stages 1...16 and Serial Control (SPI) of the Power Stages 17 and
18:
The registers MUX_REG1/2 and the bmux-bit prescribe parallel control or serial control (SPI or µsec­bus) of the power stages.

(SPI-Instructions: WR_MUX1...2, RD_MUX1...2, WR_SCON1...3, RD_SCON1...3)

The following table shows the truth table for the control of the power stages 1...18. The registers
MUX_REG1, 2 prescribe parallel-control or serial control of the power stages. The registers
SCON_REG1...3 prescribe the state of the power stage in case of SPI-serial control. BMUX deter­mines parallel control or control by µsec-bus.
For the power stages 17 and 18 control is exclusively possible via SCON17/18. IN17/18 and
MUX17/18 do not exist. BMUX has no function for OUT17/18.

ABE

00XXXX X OUTx off

01XXXX X OUTx off

10XXXX X OUTx off

1 1 X X 0 0 X SPI Control: OUTx on

1 1 X X 0 1 X SPI Control: OUTx off

1 1 0 1 1 X X Parallel Control: OUTx on

1 1 1 1 1 X X Parallel Control: OUTx off

1 1 X 0 1 X 0 µsec-bus Control: OUTx on

1 1 X 0 1 X 1 µsec-bus Control: OUTx off

RST INx BMUX MUXx SCONx µsec-

REGx

Exception: OUT8 is on (active) if IN8 is set to logic ‘1’ (and off if IN8 is set to logic ‘0’) in case of
parallel access.

Note: OUT8 cannot be controlled by the µsec-Bus. Refer to section 1.7.

Output OUTx of Power Stage x,
x = 1..18

Final Data Sheet 13 V4.2, 2003-08-29

TLE 6244X

Description of the SPI Registers

Register: MUX_REG1

76543210

MUX7 MUX6 MUX5 MUX4 MUX3 MUX2 MUX1 MUX0

State of Reset: 80H

Access by Controller: Read/Write

Bit Name Description

0 MUX0 Serial or parallel control of power stage 1

1 MUX1 Serial or parallel control of power stage 2

2 MUX2 Serial or parallel control of power stage 3

3 MUX3 Serial or parallel control of power stage 4

4 MUX4 Serial or parallel control of power stage 5

5 MUX5 Serial or parallel control of power stage 6

6 MUX6 Serial or parallel control of power stage 7

7 MUX7 Serial or parallel control of power stage 8

Register: MUX_REG2

76543210

MUX15 MUX14 MUX13 MUX12 MUX11 MUX10 MUX9 MUX8

State of Reset: 00H

Access by Controller: Read/Write

Bit Name Description

0 MUX8 Serial or parallel control of power stage 9

1 MUX9 Serial or parallel control of power stage 10

2 MUX10 Serial or parallel control of power stage 11

3 MUX11 Serial or parallel control of power stage 12

4 MUX12 Serial or parallel control of power stage 13

5 MUX13 Serial or parallel control of power stage 14

6 MUX14 Serial or parallel control of power stage 15

7 MUX15 Serial or parallel control of power stage 16

Final Data Sheet 14 V4.2, 2003-08-29

TLE 6244X

Register: SCON_REG1

76543210

SCON7 SCON6 SCON5 SCON4 SCON3 SCON2 SCON1 SCON0

State of Reset: FFH

Access by Controller: Read/Write

Bit Name Description

0 SCON0 State of serial control of power stage 1

1 SCON1 State of serial control of power stage 2

2 SCON2 State of serial control of power stage 3

3 SCON3 State of serial control of power stage 4

4 SCON4 State of serial control of power stage 5

5 SCON5 State of serial control of power stage 6

6 SCON6 State of serial control of power stage 7

7 SCON7 State of serial control of power stage 8

Register: SCON_REG2

76543210

SCON15 SCON14 SCON13 SCON12 SCON11 SCON10 SCON9 SCON8

State of Reset: FFH

Access by Controller: Read/Write

Bit Name Description

0 SCON8 State of serial control of power stage 9

1 SCON9 State of serial control of power stage 10

2 SCON10 State of serial control of power stage 11

3 SCON11 State of serial control of power stage 12

4 SCON12 State of serial control of power stage 13

5 SCON13 State of serial control of power stage 14

6 SCON14 State of serial control of power stage 15

7 SCON15 State of serial control of power stage 16

Final Data Sheet 15 V4.2, 2003-08-29

TLE 6244X

Register: SCON_REG3

76543210

111111SCON17SCON16

State of Reset: FFH

Access by Controller: Read/Write

Bit Name Description

0 SCON16 State of serial control of power stage 17

1 SCON17 State of serial control of power stage 18

7-2 No function: HIGH on reading

Final Data Sheet 16 V4.2, 2003-08-29

TLE 6244X

1.6.2 Diagnostics/Encoding of Failures

Description of the SPI Registers

(SPI Instructions: RD_DIA1...5)

Register: DIA_REG1

76543210

DIA7 DIA6 DIA5 DIA4 DIA3 DIA2 DIA1 DIA0

State of Reset: FFH

Access by Controller: Read only

Bit Name Description

1-0 DIA (1-0) Diagnostic Bits of power stage 1

3-2 DIA (3-2) Diagnostic Bits of power stage 2

5-4 DIA (5-4) Diagnostic Bits of power stage 3

7-6 DIA (7-6) Diagnostic Bits of power stage 4

Register: DIA_REG2

76543210

DIA15 DIA14 DIA13 DIA12 DIA11 DIA10 DIA9 DIA8

State of Reset: FFH

Access by Controller: Read only

Bit Name Description

1-0 DIA (9-8) Diagnostic Bits of power stage 5

3-2 DIA (11-10) Diagnostic Bits of power stage 6

5-4 DIA (13-12) Diagnostic Bits of power stage 7

7-6 DIA (15-14) Diagnostic Bits of power stage 8

Final Data Sheet 17 V4.2, 2003-08-29

TLE 6244X

Register: DIA_REG3

76543210

DIA23 DIA22 DIA21 DIA20 DIA19 DIA18 DIA17 DIA16

State of Reset: FFH

Access by Controller: Read only

Bit Name Description

1-0 DIA (17-16) Diagnostic Bits of power stage 9

3-2 DIA (19-18) Diagnostic Bits of power stage 10

5-4 DIA (21-20) Diagnostic Bits of power stage 11

7-6 DIA (23-22) Diagnostic Bits of power stage 12

Register: DIA_REG4

76543210

DIA31 DIA30 DIA29 DIA28 DIA27 DIA26 DIA25 DIA24

State of Reset: FFH

Access by Controller: Read only

Bit Name Description

1-0 DIA (25-24) Diagnostic Bits of power stage 13

3-2 DIA (27-26) Diagnostic Bits of power stage 14

5-4 DIA (29-28) Diagnostic Bits of power stage 15

7-6 DIA (31-30) Diagnostic Bits of power stage 16

Final Data Sheet 18 V4.2, 2003-08-29

TLE 6244X

Register: DIA_REG5

76543210

1 1 1 UBatt DIA35 DIA34 DIA33 DIA32

State of Reset: FFH

Access by Controller: Read only

Bit Name Description

1-0 DIA (33-32) Diagnostic Bits of power stage 17

3-2 DIA (35-34) Diagnostic Bits of power stage 18

4 UBatt 0: Voltage Level at Pin UBatt is below 2V (typically)

1: Voltage Level at Pin UBatt is above 2V (typically)
Diagnosis of UBatt is only possible if U

VDD

> 4.5V

Status of UBatt is not latched.

7-5 No function: High on reading

Encoding of the Diagnostic Bits of the Power Stages

DIA(2*x-1) DIA(2*x-2) State of power stage x x = 1..18

1 1 Power stage o.k.

10 Short-circuit to U

(SCB) / OT

Batt

0 1 Open load (OL)

00 Short-circuit to ground (SCG)

Final Data Sheet 19 V4.2, 2003-08-29

TLE 6244X

1.6.3 Configuration

The µsec-bus is enabled by this register. In addition the shut off at SCB can be configured for the
power-stages OUT9, OUT10 and OUT15... OUT18.

CONF I G (Read and wri te )

76543210

O16-SCB O15-SCB O10-SCB O9-SCB O18-SCB O17-SCB BMUX 1

State of Reset: FFh

Bit Name Description

0 No function: HIGH on reading

1 BMUX 1: parallel inputs INx enabled

0: µsec-Bus Interface enabled

2 O17-SCB 1: The output OUT17 is switched off in case of SCB

0: The output is not switched off in case of SCB

3 O18-SCB 1: The output OUT18 is switched off in case of SCB

0: The output is not switched off in case of SCB

4 O9-SCB 1: The output OUT9 is switched off in case of SCB

0: The output is not switched off in case of SCB

5 O10-SCB 1: The output OUT10 is switched off in case of SCB

0: The output is not switched off in case of SCB

6 O15-SCB 1: The output OUT15 is switched off in case of SCB

0: The output is not switched off in case of SCB

7 O16-SCB 1: The output OUT16 s switched off in case of SCB

0: The output is not switched off in case of SCB

Description of the µsec-bus see chapter 1.7

Final Data Sheet 20 V4.2, 2003-08-29

TLE 6244X

1.6.4 Other

Reading the IC Identifier (SPI Instruction: RD_IDENT1):

IC Identifier1 ( D evice ID)

76543210

ID7ID6ID5ID4ID3ID2ID1ID0

Bit Name Description

7...0 ID(7...0) ID-No.: 10101000

Reading the IC revision number (SPI Instruction: RD_IDENT2):

IC revision number

76543210

SWR3 SWR2 SWR1 SWR0 MSR3 MSR2 MSR1 MSR0

Bit Name Description

7...4 SWR(3...0) Revision corresponding to Software release: 0

Hex

3...0 MSR(3...0) Revision corresponding to Maskset: 0Hex

Reset of the Diagnostic Information (SPI Instruction: DEL_DIA):

Resets the 5 diagnostic registers DIA_REG1...5 to FFH and the common overtemperature flag in regis­ter STATCON_REG (Bit4) to High. These bits are only cleared by the DEL_DIA instruction when there
is no failure entry at the input of the registers.
Access is performed like a writing access with any data byte.

In the case a power stage is shut off because of SCB, the output is activated again by the DEL_DIA
instruction and the filtering-time is enabled. Therefore in case of SCB the output is activated and shut
off after the shutoff delay.
For a power stage in the current limitation mode, the current limitation mode is left, if a DEL_DIA
instruction has been received. If there is still the condition for SCB the current limitation mode
is entered again.

On the following pages the conditions for set and reset of the SCB report in DIA_REGx is shown in
several schematics. The signal „power stage control“ is generated as follows:

INi=“ON“
SPI=“ON“
µsec=“ON“

OR AND

ABE not active

power stage control = „ON“

Final Data Sheet 21 V4.2, 2003-08-29

TLE 6244X

no SCB

OnOn

OnOnOnOnOn

SCB

SCB

DIAG

t

DIAG

t

DIAG

t

DIAG

t

On

On

SCB

On

SCB

On

Schematic of SCB report of power stages OUT1...7,9...18 (power stage programmed for

shut-off in case of SCB), SCB entry deleted by DEL_DIA after SCB condition disappeared

and power stage control was toggled

Final Data Sheet 22 V4.2, 2003-08-29

SCB condition

OUTx

Fault entry

in DIA_REGx

DEL_DIA command

Reset

power stage

control

TLE 6244X

On

SCB no SCB

DIAG

t

DIAG

t

DIAG

t

On On

On

On

On

On

On

On

SCB

SCB SCB

DIAG

t

Schematic of SCB report of power stages OUT1...7,9...18 (power stage programmed for

shut-off in case of SCB), SCB entry deleted by Reset after SCB condition disappeared

and power stage control was toggled

Final Data Sheet 23 V4.2, 2003-08-29

SCB condition

OUTx On

Fault entry

in DIA_REGx

DEL_DIA command

Reset

power stage

control On

TLE 6244X

t

DIAG

On

On

On

DIAG

t

toggled

SCB

On On On

DIAG

t

SCB SCB

DIAG

t

On On

Schematic of SCB report of power stages OUT1...7,9...18 (power stage programmed for

shut-off in case of SCB), SCB entry deleted by DEL_DIA after SCB condition disappeared

but power stage control was not

Final Data Sheet 24 V4.2, 2003-08-29

SCB condition SCB no SCB

OUTx On

Fault entry

in DIA_REGx

DEL_DIA command

Reset

power stage

control On

TLE 6244X

DIAG

t

DIAG

t

On

On

On On

toggled

SCB

On On On

DIAG

t

SCB SCB

DIAG

t

Schematic of SCB report of power stages OUT1...7,9...18 (power stage programmed for

shut-off in case of SCB), SCB entry deleted by Reset after SCB condition disappeared

but power stage control was not

Final Data Sheet 25 V4.2, 2003-08-29

SCB condition SCB no SCB

OUTx On

Fault entry

in DIA_REGx

DEL_DIA command

Reset

power stage

control On

TLE 6244X

On

SCB

no SCB

no OTno OT

DIA,OT

t

DIA,OT

t

OnOn

On

OnOn

DIAG

t

OT

SCB

OnOnOn

SCB

DIAG

t

SCB

DIAG

t

Schematic of SCB report of power stages OUT9,10,15...18 (power stage programmed for

current limitation in case of SCB), SCB resp. OT flag entry deleted exemplary by DEL_DIA

after SCB resp. OT condition disappeared and power stage control was toggled

Final Data Sheet 26 V4.2, 2003-08-29

SCB condition

OT condition OT

OUTx

Fault entry

in DIA_REGx

common OT flag

in STATCON_REG

DEL_DIA command

Reset

power stage

control

Reading Input1 (SPI Instruction: RD_INP1)
:

Register INP_REG1

76543210

IN8 Test 0 IN5 IN4 IN3 IN2 IN1

Bit Name Description

0..4 IN(1...5) Status of the input pins IN1... IN5

5 No function: LOW on reading

6 Test µsec-test-bit, the bit D8 of the µsec-bus is read

7 IN8 Inverted status of the input pin IN8:

Low level at pin IN8: Bit 7 = 1
High level at pin IN8: Bit 7 = 0

TLE 6244X

Reading Input2 (SPI Instruction: RD_INP2):

Register INP_REG2

76543210

0 IN15 IN14 IN13 IN12 IN11 IN10 IN9

Bit Name Description

0..6 IN9...IN15 Status of the input pins IN9...IN15

7 No function: LOW on reading

The input pins IN1..IN5 and IN8...IN15 can be used as input port expander by reading the status of
the input pins using the SPI-commands RD_INP1/2. If the µsec-bus-interface is enabled (BMUX=0) the
pull-up current sources at the input IN1..5 and IN9..15 are disabled. If BMUX=1 the pullup current
sources at these pins are enabled. The pull-up/pull-down current sources of the other input pins are
not effected by the bit BMUX.

On executing the read instruction on RD_INP1/2, the present status (not latched) of the input pins INx is
read back (exception: bit IN8 represents the inverted status of input pin IN8).

Final Data Sheet 27 V4.2, 2003-08-29

TLE 6244X

Reading the State resp. the Configuration:
(SPI Instructions: WR_STATCON, RD_STATCON)

Register: STATCON_REG

76543210

CONFIG2 CONFIG1 CONFIG0 STATUS4 STATUS3 STATUS2 STATUS1 STATUS0

Bit Name Description

0 STATUS0 Bit = 1: No overvoltage at VDD

Bit = 0: Overvoltage at VDD resp. state of overvoltage still
stored (reset by CONFIG0 = 0)
Access by Controller: Read only

Overvoltage information (bit STATUS0 = 0) will not be reset by an
external reset signal (pin RST=low). Overvoltage will be detected
and stored (CONFIG0 = 1) during RST=low. The information will be
deleted when an internal (undervoltage) reset occurs or when
CONFIG0 is set to 0.

1 STATUS1 Bit = 1: No undervoltage at VDD

Bit = 0: Undervoltage at VDD
Access by Controller: Read only

2 STATUS2 Reading the voltage level at ABE

Access by Controller: Read only

3 STATUS3 Common error flag

Bit =1: At present no error is entered in one of the 5 diag­ nostic registers DIA_REG1..5.
Bit = 0: For at least at one power stage an error has been
detected and entered in the corresponding diagnostic
register.
Access by Controller: Read only

4 STATUS4 Common overtemperature flag

Bit = 1: No overtemperature detected since the last reset
of diagnostic information (by del_dia instruction,
RST

= Low or undervoltage at VDD (see 3.2. ))
Bit = 0: Overtemperature for at least one power stage has
been detected since the last reset of the
diagnostic information (by del_dia instruction,
RST

= Low or undervoltage at VDD (see 3.2. ))
State of Reset: 1
Access by Controller: Read only

5 CONFIG0 Bit = 1: Latch function for overvoltage at VDD is switched on

Bit = 0: Latch function for overvoltage at VDD is switched off
State of Reset: 1
Access by Controller: Read/Write

Final Data Sheet 28 V4.2, 2003-08-29

TLE 6244X

6 CONFIG1 Bit = 1: Lower threshold of VDD-monitoring is lifted

if bit CONFIG2 = 0 (test of switch-off path)
Bit = 0: Upper threshold of VDD-monitoring is reduced
if bit CONFIG2 = 0 (test of switch-off path)
State of Reset: 1
Access by Controller: Read/Write

7 CONFIG2 Bit = 1: Test of VDD threshold is switched off

Bit = 0: Test of VDD threshold is switched on
State of Reset: 1
Access by Controller: Read/Write

Final Data Sheet 29 V4.2, 2003-08-29

TLE 6244X

1.7 µsec - Bus Interface

The µsec-bus-interface is one of three possibilities to control the power stages. OUT1...OUT7
and OUT9...OUT16 are influenced by the reset input RST. If RST is set to Low, these power
stages are switched off. After reset they are controlled by the SPI (default initialization of
TLE6244X). Power stage 8 however is not influenced by the reset input if it’s controlled by IN8
and U

> 3,5V. Alternatively these outputs can be controlled either by the pins IN1...IN16 or by

VDD

the µsec-bus interface. Exception: OUT8 can be controlled by IN8 or by the SPI-interface only.
The bit ’Bus-Multiplex’ (BMUX) in the SPI register CONFIG prescribes parallel access (IN1...IN7,
IN9...IN16) or µsec-bus control (see figure below). Exception: If BMUX is set to ‘0’ only the power­stages OUT1...OUT7 and OUT9...OUT16 are controlled by the µsec-bus.

Main features:

- 16 data bits for each data-frame (at the pin FDA)

- 16 clock-pulses for each data-frame (at the pin FCL)

- clock frequency TLE6244: 0...16 MHz

- one sync -input (pin SSY) to latch the input data stream

- input level interface same as for IN6, IN7, IN16

- no error correction

Data-Frame

SSY

FCL

FDA D0

FDA

FCL

SSY

SPI

Glitch
Filter

D0 D1 don’t careD15D14

INx

16 bit shift register

16 bit µsec-bus Reg.

SCON_REG

SPI-shift-reg

BMUX

OUTx

MUX_REG

Principle of the µsec-bus interface

Final Data Sheet 30 V4.2, 2003-08-29

TLE 6244X

When the bit BMUX in CONFIG is set to Low, the power stages 1...7 and 9...16 are controlled by
the µsec-bus-interface on condition that registers MUX_REG1/2 are configured for serial access.
The received µsec-bus bit stream (D0... D15) is latched into a 16-bit register by the rising edge at
SSY. Power stages 1...7 and 9...16 are switched according to bits D0...D7 and D9...D15:

µsec-bus control of

power stage

µsec-bus control of

power stage

D0 OUT14 D8 µsec-bus Test

Bit

D1 OUT1 D9 OUT11

D2 OUT2 D10 OUT10

D3 OUT3 D11 OUT9

D4 OUT4 D12 OUT12

D5 OUT5 D13 OUT13

D6 OUT6 D14 OUT16

D7 OUT7 D15 OUT15

Bit Dx = 0: Power stage OUTx is switched on
Bit Dx = 1: Power stage OUTx is switched off
State of reset: FFFF

H

Because the power stage 8 is not controlled by the µsec-bus-interface, the corresponding bit D8
can be used as test bit, that can be read back by the SPI-interface (see register RD_INP1).
If the µsec-bus-interface is used to control the power stages, the input pins IN1..IN5 and
IN8...IN15 can be used as input port expander by reading the status of the input pins by the SPI­commands RD_INP1/2.

Final Data Sheet 31 V4.2, 2003-08-29

TLE 6244X

1.8 Unused Power Stages

To avoid an „open load“ fault indication an unused power switch has to be connected to an exter­nal pull up resistor connected to U

or has to be switched on by the input pin or via SPI or the

UB

µsec-bus-interface.

U

UBatt

Voltage
regulator

U

UBR

drop

TLE6244X

U

Batt

R

Pull-up

I

diag

U

UB

OUTi

U

thresOL

R

UBR

is the required minimum battery voltage for diagnostic function of the ECU. The drop volt-

min

Pull-up,max

age is composed of the drop voltage of the regulator and the drop voltage of the reverse protec­tion circuit of the regulator resp. the forward voltage of a reverse protection diode.

Attention:

This equation also applies to power switches that are used as signal drivers (pull up resistor
inside ECU or outside ECU): the permissible pull up resistance without a wrong diagnostic infor­mation is calculated by the same equation. On dimensioning the pull up resistance in combination
with the diagnostic current, in applications as signal drivers attention must be paid especially to
the required high level (also for low battery voltage).

= (UBR

min

- U

drop,max

- U

thresOL,max

) / I

diag,max

Final Data Sheet 32 V4.2, 2003-08-29

1.9 Timing Diagram of the Power Outputs

1.9.1 Power Stages

U

INi

U

INiH

U

INiL

TLE 6244X

t

0.8U

U

0.8U

0.2U

0.2U

U

OUTi

U

CLi

BATT

BATT

BATT

CLi

CLi

*)

s

off

s

on

t

don

t

son

t

doff

t

soff

t

If the output is controlled via SPI the timing starts with the positive slope at SS
If the output is controlled by the µsec-bus, the timing starts with the pos. slope of SSY

*) With ohmic load, UCLi = UBatt

Final Data Sheet 33 V4.2, 2003-08-29

1.10 VDD-Monitoring

Overview:

TLE 6244X

The VDD-monitoring generates a „low“ signal at the bidirectional pin ABE
age at pin VDD is out of the permissible range of 4.5V...5.5V. On ABE
TLE6244X are switched off. Exception: OUT8 is not switched off in case of parallel control via
IN8 by the VDD monitoring undervoltage threshold, but by a threshold of 3.5V at VDD.
On shorting pin ABE
undervoltage or overvoltage at pin VDD in spite of ABE
The behavior of the ABE
rect range is not configurable. At the transition from undervoltage to normal voltage the signal
at pin ABE
return of VDD out of the overvoltage range into the correct range is configurable in
STATCON_REG, Bit5. At the transition from overvoltage to normal voltage the signal at pin ABE
goes high either after a filtering time (OV not latched) or after a SPI writing instruction (OV
latched, state after reset).
On undervoltage condition the signal at pin ABE
overvoltage condition pin ABE
tion. Before this SPI instruction is sent to TLE6244X appropriate tests can be carried out by the
controller.
If the voltage at pin VDD is below the lower limit or is resp. was above the upper limit, this can
be read out by the SPI instruction RD_STATCON.
VDD-monitoring has no influence on SCON_REGx, MUX_REGx, DIA_REGx, CONFIG and
INP_REGx.
If output stages are switched off by the internal over-/undervoltage detection or by externally
applying a low signal at the ABE

Description in Detail:

goes high after a filtering time is expired. The behavior of the ABE level on the

to V

or UBATT (≤ 36V), the power stages will be switched off in case of

DD

level on the return of VDD out of the undervoltage range into the cor-

goes high after a filtering time is expired. On

goes high either after a filtering time or after a SPI writing instruc-

pin, no failure storage (DIAREG1...5) may occur.

= high.

if the 5V supply volt-

= low the power stages of

Description of the Register:
STATCON_REG

Bit 7 1: Normal operation

0: Test of VDD threshold
Access by controller: read/write
State of reset: 1

Bit 6 1: Testing the lower threshold (if bit 7 = 0)

0: Testing the upper threshold (if bit 7 = 0)
Access by controller: read/write
State of reset: 1

Bit 5 1: ABE

0: ABE

Access by controller: read/write
State of reset: 1

Bit 2 Reading out the level at pin ABE

Access by controller: read only

Bit 1 1: no undervoltage at pin VDD

0: undervoltage at pin VDD
Access by controller: read only

latched after overvoltage
deactivated immediately after the disappearance of the overvoltage

Final Data Sheet 34 V4.2, 2003-08-29

TLE 6244X

Bit 0 1: no overvoltage at pin VDD

0: overvoltage at pin VDD resp. state of overvoltage still stored
Access by controller: read only

Testing the VDD-Monitoring:

Upper threshold:
By writing 000xxxxxb in the register STATCON_REG the overvoltage threshold is reduced by

0.8V. In STATCON_REG Bit 0 has to be LOW then.
After writing 110xxxxxb in the register STATCON_REG Bit 0 in STATCON_REG must be HIGH
again.

Lower threshold:
By writing 010xxxxxb in the register STATCON_REG the overvoltage threshold is increased by

0.8V. In STATCON_REG Bit 1 has to be LOW then.
After writing 110xxxxxb in the register STATCON_REG Bit 1 in STATCON_REG must be HIGH
again.

Example of configuration:

Requirement: After overvoltage ABE
After overvoltage a self-test is carried out by the ECU, afterwards ABE

Register STATCON_REG is set to 111xxxxxb during driving cycle.
When ABE
After the ECU’s self-test a reset condition is achieved by writing 110xxxxxb into the register
STATCON_REG. This reset is only possible after disappearance of the overvoltage condition
because the set input is dominant. The reset signal is withdrawn by writing 111xxxxxb.

becomes active, overvoltage can be detected by reading out STATCON_REG.

is to be LOW;

is deactivated.

Final Data Sheet 35 V4.2, 2003-08-29

TLE 6244X

ABE

100k

VDD

GND1,2

&

„L“ = Switch Off

Power Stages

1

&

Undervoltage

Reset

Q

STATCON_REG

S

Set dominant

Glitch filter

R

01

<=

<=

2

-

+

„L“ = Undervoltage at VDD

-

+

„L“ = Overvoltage at VDD

GND_ABE

0

1

0

1

Block Diagram: VDD-Monitoring

1

>

VDD

1

>

1

GND_ABE

34

5

Test: Overvoltage Threshold

0

6

0

7

default

Test: Undervoltage Threshold

1

X

1

0

Final Data Sheet 36 V4.2, 2003-08-29

TLE 6244X

1.11 Notes for the Application in Commercial Vehicles

>

For electric systems with 24V battery voltage, that can even increase to

_

37V in case of

load dump, some peculiarities have to be observed!

The static voltage at pin UBatt without destruction is limited to 37V, therefore this pin must either
be connected to the 5V supply voltage VDD or else the voltage at pin UBatt has to be limited by
adequate external circuitry. By connecting pin UBatt to VDD the values of R

of the power

ds, on

switches will increase up to 20%.

The power stages 7...18 are equipped with a 40V active clamping. Therefore this power stages
must only drive loads with an accordingly high resistance that can be switched on in case of over-

voltage (e.g. a maximum load dump voltage of 60V and a load resistor of 1kΩ result in a power

dissipation of 0.8W for each power stage. For all of the 12 power stages together there is a power
dissipation of 9.6W for the typical duration of a load dump of 500ms.).

The restrictions listed above are no longer relevant in case of a „overvoltage-protected
battery voltage“within the 24V electric system that limits the voltage to e.g. a maximum of
37V.

The thresholds of the currents, on which the power stages are switched off in case of overload,
are increased by approximately 25% if there is a voltage at pin UBatt higher than19V (reason:
jump start requirements in 12V electric systems). Exception: OUT9 and OUT10 and OUT15...
OUT18. See characteristics in chapters 3.5.3, 3.6.3, 3.7.3 and 3.8.3.
The restrictions concerning overload of power stages (see 3.5.2, 3.6.2, 3.7.2 and 3.8.2) and per­missible clamping energy (see 3.5.8, 3.6.8, 3.7.8 and 3.8.8) are relevant further on.

1.11.1 Notes for short circuit limitation

The power stages are short circuit protected for the following conditions:
The max. voltage at the output pins are limited to 36V and the TLE6244 is not operating in the
booster mode.
The power stages will be switched on/off with a max. frequency of 1 kHz.
Only a 40 msec burst with the 1 kHz on/off-frequency is allowed, with a minimum burst repetition
time of 1 sec. The maximum number of burst repetition cycles is 25. The number of driving cycles
under these conditions is limited to 100 in lifetime. The temperature of the slug of the MQFP64
package must not exceed 130°C.
These limitations are valid for UBatt > 24 V.
For Ubatt

≤ 24 V the number of driving cycles under these conditions is extended to 1000 in life-

time.

Final Data Sheet 37 V4.2, 2003-08-29

TLE 6244X

1.12 Notes for the Diagnostics

- SCB entry in DIA_REGx see diagrams in chapter 1.6.4.

- In case of overvoltage at pin VDD (VDD > 5,5V) the diagnostic information can be wrong. In
that case, the diagnostic information has to be cleared with the DEL_DIA instruction.

- The filtering time restarts when the output voltage passes the diagnostic threshold for
short to ground (SCG).

- Diagram of the typical diagnostic current:

I

OUTPUT

580 µA

A

A

0V

-130 µA

A

Short to GND

A: Diagnostic current (see 3.11.3)
B: Bias Voltage Open Load (see3.11.2)
C: Short to GND Threshold (see 3.11.1.2)
D: Open load Threshold (see 3.11.1.1)

2.7V

3.5V

A

Open load

C

B

5V

D

o. k.

14V

U

OUT

Final Data Sheet 38 V4.2, 2003-08-29

State Diagram of the Power Stages Diagnostics

No

Action

TLE 6244X

A

(VDD is out of range) output OUTx is switched off. After reset the

SCG

No

OL

Toggling INx HIGH -> LOW

10 OT

Fault Entry

Fault

Debouncing

OT

B

OUTx on

INx LOW

Toggling INx LOW -> HIGH

LOW -> HIGH

Toggling INx

SCG

SCB

SCB

Debouncing

No

Current Control

SCB

SCG

Fault Entry

SCG

Debouncing

No

for OUT9..10

OUT15...16

10 SCB

Fault Entry

for OUT1..8,

OUT11..14

00 CSG

No

Action

SCG

OL

10 SCB

Fault Entry

LOW -> HIGH

Toggling INx

no OT

D

3..5A

INx LOW

(if current limitation is configured)

OUTx on

max current

A

(no current limitation)

for OUT9..10

OUT15...16

C

INx LOW

LOW -> HIGH

Toggling INx

OUTx off

OT

No

Fault

SCB

SCG

OL

OT

INx LOW

OUTx off

OT

no OT

Debouncing

OT

10 OT

Fault Entry

10 SCB

Fault Entry

At DEL_DIA:

C -> B

D -> B

A no action

Exemplary for a power stage controlled by input pin INx. Diagram is accordingly valid for serial con-

trol via SPI or µsec-bus. The SPI instruction DEL_DIA deletes all fault registers in any state.

On active reset resp. active ABE

A

SCB

OT

No

Fault

No

Action

power stage is in state A (except OUT8).

OL

No

INx HIGH

OL

OUTx off

OL

Debouncing

01 OL

Fault Entry

Final Data Sheet 39 V4.2, 2003-08-29

TLE 6244X

1.13 Parallel Connection of Power Stages

The power stages (PS) which are connected in parallel have to be switched on and off simultaneously.
The corresponding SPI-Bits SCONx have to be in the same register (see page 15), when the PS are
serial controlled via SPI.
In case of overload the ground current and the power dissipation are increasing. The application has to
take into account that all maximum ratings are observed (e.g. operating temperature T
ground current I

Max. number of parallel connections: 3

, see page 36, 37).

GND

and total

J

The following statements apply to PS within the same TLE6244X

The max. short circuit shutdown threshold of the parallel connected PS is the summation of the corre­sponding max. values of the PS (I

Max. Nominal Current Max. Clamping Energy On Resistance

SC,OUTx

+ I

SC,OUTy

+....).

2 symmetrical PS
(see note 1)

2 PS of the same type
(see note 2)

3 PS of the same type
(see note 2)

2 PS with the same nominal
current, but different clamp­ing voltage (application with­out
free-wheeling-diode)
(see note 3)

2 PS with the same nominal
current, but different clamp­ing voltage (application with
free-wheeling-diode)
(see note 3)

2 PS with the same clamp­ing voltage, but different
nominal
current (see note 4)

0.9 x (I

max,OUTx

0.85 x (I

max,OUTx

0,8 x
(I

max,OUTx

I

max,OUTz

0.7 x (I

max,OUTx

0.7 x (I

max,OUTx

Max

0.75 x (I

I

max,OUTy

+ I

max,OUTy

)

I

max,OUTx

I

max,OUTy

max,OUTx

+ I

max,OUTy

+ I

max,OUTy

+ I

max,OUTy

+ I

max,OUTy

)

+

+

)0.75 x (E

)0.75 x (E

0,58 x
(E
E

Clamping energy

)

Cl,OUTx

Cl,OUTx

Cl,OUTx

Cl,OUTz

+ E

)

+ E

+ E

Cl,OUTy

of the PS with the lower
clamping voltage

)

no clamping required

E

Min

Cl,OUTx

E

Cl,OUTy

Cl,OUTy

Cl,OUTy

+

)

0.5 x R

) 0.5 x R

0.34 x
R

on,OUTx,y,z

R

on,OUTx

R

on,OUTx

R

on,OUTx

R

on,Ax

R

on,OUTx

R

on,OUTx

on,OUTx,y

on,OUTx,y

x R

on,OUTy

+ R

on,OUTy

x R

on,OUTy

+ R

on,OUTy

x R

+ R

on,OUTy

on,OUTy

2 PS with different nominal
current and different clamp­ing voltage (see note 5)

Max

I

max,OUTx

I

max,OUTy

Clamping energy
of the PS with the lower
clamping voltage

R

on,OUTx

R

on,OUTx

x R

+ R

on,OUTy

on,OUTy

Final Data Sheet 40 V4.2, 2003-08-29

TLE 6244X

note 1: For every PS there exists only one symmetrical PS
OUT1 and OUT2 are symmetrical PS.
OUT3 and OUT4 are symmetrical PS.
...
OUT17 and OUT18 are symmetrical PS.

note 2: PS of the same type have the same nominal current and the same clamping voltage

note 3: Parallel connection of PS-type 2,2A/45V with type 2,2A/70V

note 4: Parallel connection of PS-type 2,2A/45V with type 3.0A/45V or
Parallel connection of PS-type 1.1A/45V with type 2,2A/45V

note 5: Parallel connection of PS-type 2,2A/70V with type 1.1A/45V or
Parallel connection of PS-type 2,2A/70V with type 3.0A/45V

If the power stages are configured for static current limitation the max. current limitation of the parallel
connected PS is the summation of the corresponding max. values of the
PS (I

SC,OUTx

+ I

SC,OUTy

+....).

The following statements apply to Power Stages within different TLE6244X

The application has to take into account that all maximum ratings of each TLE6244X are observed.

Final Data Sheet 41 V4.2, 2003-08-29

TLE 6244X

2. Maximum Ratings

2.1 Definition of Test Conditions

The integrated circuit must not be destroyed if maximum ratings are reached. Every maximum
rating is allowed to reach, as far as no other maximum rating is exceeded.

Unless otherwise indicated all voltages are referred to GND (GND pins 1...8 connected to each
other)

Positive current flows into the pin.

2.2

Test Coverage (TC) in Series Production

In the standard production flow not all parameters can be covered due to technical or economic
reasons. Therefore the following test coverage was defined:

A) Parameter test
B) Go/NoGo test (in the course of release qualification/characterization: parameter test)
C) Guaranteed by design (covered by lab tests, not considered within the standard production

flow)

2.3

Thermal Limits

Operating temperature TLE6244

continuous -40°C ≤ TJ ≤ 150°C
additionally only for the power switches 150°C ≤ T

≤ 200°C

J

(for 100h accumulated)

Storage temperature -55°C ≤ T

Thermal resistance R

2.4

Electrical Limits

thJC

≤ 125°C

C

≤ 2,5 K/W

Limits must absolutely not be exceeded. By exceeding only one limit the integrated circuit might
be destroyed.

Power Supplies U

Static (without destruction) *) -0.3V ≤ U

-0.3V ≤ U
Dynamic <10µsec (without destruction) -0.5V ≤ U

-0.5V ≤ U
Dynamic (500 ms, 10 x in lifetime, without destruction) -0.5V ≤ U

VDD

and U

UBatt

VDD

UBatt

VDD

UBatt

≤ 36V

≤ 37V

≤ 36V

≤ 40V

UBatt

≤ 40V

*) U

> 5.5V is allowed only in case of error conditions! Not suitable for continuous

VDD

operation.

SPI Output

Output voltage -0.3V ≤ U

SO

≤ 36V

Final Data Sheet 42 V4.2, 2003-08-29

TLE 6244X

Output current I

≤ 5mA

SO

Outputs Low Side Switches

Static voltage (without destruction) OUT1...6 ≤ 64V

OUT7..18 ≤ 40V

Dynamic voltage without destruction after ISO/DIS7637-1, pulses 1 to 4

OUT1 to 6, OUT9 to16: via external load (e.g. 2W lamp) ≤ 2ms
OUT7, OUT8, OUT17 and OUT18: via external load ≤ 2ms

Ground Current

Total current GND1+2 (pins 26/27) I

GND1+2

≤ 18 A

(total ground current of OUT5,6,9,10,17,18)

Total current GND3+4 (pins 58/59) I

GND3+4

≤ 20 A

(total ground current of OUT1,2,7,8,11,12,15,16)

Total current GND5+6 (pins 11/12) I

GND5+6

≤ 6 A

(total ground current of OUT3,13)

Total current GND7+8 (pins 41/42) I

GND7+8

≤ 6 A

(total ground current of OUT4,14)

Attention:

ground currents I

Even if all ground pins are connected with each other on the PCB the total

GND1+2

and I

GND3+4

and I

GND5+6

and I

GND7+8

must not be exceeded.

The 4 ground pins GND1...4 are internally connected to the heat sink via an unspecified
rivet joint. Therefore it is advisable to short-circuit the 4 ground pins on the PCB and to
connect them with the heat sink. In addition the 4 ground pins GND5..8 must be connected
to the other ground pins on the PCB

Inputs of the Power Switches, SPI Inputs, Reset and Shut-off of the Power Stages

Input voltage -0.3V ≤ U

INi,RST,SS,SI,SCK,ABE

≤ 36V

Input currents see 3.4.4 , 3.9.1 , 3.9.2 , 3.9.3 , 3.13.2

Pin RST

Minimum reset duration (Power-On) 15 ms

Input currents see 3.4.4

Final Data Sheet 43 V4.2, 2003-08-29

3. Electrical Characteristics

TLE 6244X

3.1 Operating
Range

(see also 3.13
VDD-monitoring
ABE

)

alidity of

3.2 V
Parameters

Out of this range the power stages
can be shut off by the VDD-moni­toring except OUT8

Voltage referred to GND_ABE

Minimum reset duration
(Power-On)

Minimum reset duration
in operation mode

4.5V ≤ U

VDD

≤ 5.5V

Parameters are valid for

4.5V ≤ U

4.5V ≤ U
TLE6244: -40°C ≤ T

VDD

UBatt

≤ 5.5V,

≤ 37V

≤ 150°C and

J

2 power stages in
current limitation
unless otherwise noted.
If VDD-monitoring is active the
power stages are switched off
except OUT8 (see page 28).
Positive current flows into the pin,
negative current flows out of the
pin.
Unless otherwise noted all volt­ages are referred to GND
(GND1...8 connected with each
other).

U

VDD

t

RST,min

t

RST,min

4.7

15

1

5.3 V

ms

µs

If the U
trashed the power stages (except

falls below this

VDD

U

VDD

3.5 4.2 4.5

V
OUT8) are switched off.
If U

rises above this threshold

VDD

the power stages work regularly

after a delay time of 250 µsec.

Threshold for shut off of OUT8:
If U

rises above this threshold

VDD

U

VDD

3.5

V
the power stages work regularly
after a delay time of 250 µsec.

Supply voltage U

VDD

4.5 5.5 V

Final Data Sheet 44 V4.2, 2003-08-29

TLE 6244X

3.3 Power Con­sumption

U

VDD ≤

5.5V
5,5 V < UVDD < 36 V (IC is not
destroyed)
U
U
U

= 14V

UBatt

= 28V

UBatt

≤ U

UBatt

VDD

Power consumption in standby
mode in case of missing U

3.4 I

nputs of the

Power Stages

U

Outputs are switched off if inputs
are open (parallel control).

UBatt

≤ 14V

and Reset

IN1...IN16, RST

3.4.1 Low Level Reset not active,
Power stage on for
i = 1...5, 9...15
i = 6, 7, 16
Power stage off for
i = 8

3.4.2 High Level Power stage off for
i = 1...7, 9...16

Power stage on for
i = 8

VDD,

A
C

A
A
A

A

B

B
B

B

B
B

I
I

I

UBatt

I

UBatt

I

UBatt

I

UBatt

U

U
U

U

U

U

VDD

VDD

RSTL

INiL

INiL

INiL

RSTH

INiH

1.7

2.0

20
50

200

1.0

1.0

1.0

1.0

mA
mA

mA

3

mA

4

mA

1

µA

V

V
V

V

V

V
V

B

U

INiH

2.0

V

3.4.3 Hysteresis C ∆U

∆U

3.4.4 Input Cur-

rents

-0.3V ≤ U

INi,RST

(i = 1...7, 9...16)

≤ U

VDD

A/B

I

INi,RST

In, RST

U

VDD

≤ U

INi

≤ 36 V

C

|I

(i = 1...7, 9...16)

-0.3V ≤ U

0.8V ≤ U

≤ U

U

VDD

0V ≤ U
0V ≤ U

≤ U

IN8

RST

INi

IN8

≤ U

VDD

≤ U

VDD

≤ 36 V, pull down

IN8

≤ U

VDD

- 1.7V, pull up

VDD

, pull down

- 1.7V, pull up

A/B

A
C

A

A

-I

(i = 6,7,16)

Bit BMUX = 1 (CONFIG_REG):

0V ≤ U

INi

≤ U

- 1.7V, pull up

VDD

A

(i = 1..5, 9..15)

Bit BMUX = 0 (CONFIG_REG):

0V ≤ U

INi

≤ U

, high-impedance

VDD

A

|I

(i = 1..5, 9..15)

I

IN8

I

IN8

I

IN8

RST

-I

-I

INi

RST

INi

INi

INi

INi

,

0.1 0.6 V

-100

|

-100

20
20

20

5

20

40
40

40

10

40

|

5

5

100

100
100

100

20

100

1

µA

µA

µA

µA
µA

µA

µA

µA

µA

Final Data Sheet 45 V4.2, 2003-08-29

TLE 6244X

3.4.5 Input Protec-

tion INi

3.5 P

ower Outputs

2.2A/70V

OUT1...6

3.5.1 Nominal Cur-

rent

Input clamping at INi (i = 1...16):
No malfunction during clamping.

Max. clamping current (externally
limited)
static
dynamic (t < 2ms)

Max. clamping voltage
I

= -5mA

INi

I

= +2mA (t < 2ms)

INi

External current limitation at INi is
only provided if µsec-bus control is
used. In that case INi are used as
digital inputs. If µsec-bus is not
used, there is no external resistor
for current limitation. See 2.4
“Inputs of the Power Switches, SPI
Inputs...”

In case of open input (parallel con­trol) or missing power supply the
power stage is switched off. Paral­lel connection of power stages is
possible.

C
C

C
C

C

|I

INi

|I

INi

U

INi

U

INi

I

OUT1..6

2

|
|

-3

40

70

mA

5

mA

V
V

2.2 A

3.5.2 Extended Cur-

rent Range

3.5.3 Maximum

Current
(Short Circuit
Shut- down
Threshold)

I

OUT1...6

> 2.2A

Accumulated operating time C 100 h

4.5V ≤ U

T

= -40°C

J

T

= 150°C

J

U

> 21V

UBatt

T

= -40°C

J

T

= 150°C

J

UBatt

≤ 17V

I

B
A

B
A

OUT1..6

I

OUT1..6

I

OUT1..6

I

OUT1..6

2.4

2.2

3

2.7

4.0

3.7

5.0

4.6

Above this limit short circuit to
UBatt is detected. For the duration
of the shutoff delay time t

Voff

(see

3.5.4) the output current is limited
to approximately this value. If the
short circuit condition is still
present after t

, the output is

Voff

switched off. An error is stored
after t

(see 3.11.4).

Diag

A
A

A
A

Final Data Sheet 46 V4.2, 2003-08-29

Between -40°C and 150°C an
approximately linear characteristic
line can be assumed for the short
circuit shutdown threshold.

TLE 6244X

3.5.3.1 Maximum

Battery Volt­age at Short
Circuit to Bat­tery

Between 17V ≤ U

≤ 21V, the

UBatt

short circuit shutdown threshold is
switched.

A power stage that is switched off
in case of SCB can be switched on
again by an off/on cycle at the cor­responding input pin resp. by the
change of the state of the corre­sponding SPI bit SCONx (see
page 16), by the µsec-Bus, by a
DEL_DIA instruction or can be
released again by reset. If the fault
register is cleared before this
release (by a DEL_DIA instruc­tion), a new fault entry of SCB is
immediately carried out, even if
SCB condition is no longer
present.

See Note 1.11.1 C U

OUT

1..6

36 V

3.5.4 Shutoff Delay Shutoff delay of the power stages
after detection of SCB

3.5.5 On Resis-

tance

OUT1,2,5,6: T
OUT1,2,5,6: T
OUT1,2,5,6: T
OUT3,4: T
OUT3,4: T
OUT3,4: T
For U

UBatt

= 25°C

J

= 150°C

J

= -40°C

J

≤ 10V R

= 25°C

J

= 150°C

J

= -40°C

J

is increased

on

up to 20%.

3.5.6 On/off Delay

„On“

Times

„Off“
(Measurement with ohmic load)
|t

- t

doff

|

don

switch-on slew rate
switch-off slew rate

Bt

A
A
A
A
A
A

B
B
B
C
C

C
C

Vof f

R

on1,2,5,6

R

on1,2,5,6

R

on1,2,5,6

R

on3, 4

R

on3, 4

R

on3, 4

t

don1...6

t

son1...6

t

doff1...6

t

soff1...6

∆t

s

on1...6

s

off1...6

d

60 215 µs

220
420
180
210
410
170

320
600
250
300
580
240

400
750
310
380
720
300

10

5
10
10

5

1521V/µs

V/µs

mΩ
mΩ
mΩ
mΩ
mΩ
mΩ

µs
µs
µs
µs
µs

Final Data Sheet 47 V4.2, 2003-08-29

3.5.7 Leakage Cur­rent

3.5.8 Clamping

3.5.8.1 Clamping

Voltag e

U

VDD

= 0V, U

OUT1...6

= 14V (leak­age current of the DMOS, diag­nostic current = 0)

U

VDD

= 0V, U

OUT1...6

= 24V (leak­age current of the DMOS, diag­nostic current = 0)

I

OUT1...6

= 0.2A A

TLE 6244X

I

A

A

OUT1..6

I

OUT1..6

U

OUT1..6

64 76 V

50

200µAµA

3.5.8.2 Matching of
the Clamp­ing Voltage

3.5.8.3 Maximum
Clamping En­ergy

≤ 110°C

T

C

3.5.8.4 Maximum
Clamping En­ergy
T

≤ 60°C

C

3.5.8.5 Maximum
Clamping En­ergy with two
Outputs con­nected in par­allel

Between different outputs with
identical inductive loads

Linear decreasing current,
f

= 50Hz (see diagrams

max

E = f(I) on page 66)

I

OUT1...6

I

OUT1...6

I

OUT1...6

≤ 2.2A C E 8.5 mJ
≤ 1.0A C E 19 mJ
≤ 0.5A C E 30 mJ

Linear decreasing current,
f

= 50Hz

max

I

OUT1...6

I

OUT1...6

I

OUT1...6

≤ 2.2A C E 10.8 mJ
≤ 1.0A C E 22 mJ
≤ 0.5A C E 36 mJ

Each output 75% of the values of

3.5.8.3 resp. 3.5.8.4

A ∆U3V

C

3.5.8.6 Maximum
Clamping En­ergy at Load
Dump

3.5.8.7 Jump Start Each output 150% of the values of

For a maximum of 10 times during
ECU life (load dump with 400ms
and R

= 2Ω over the load, e.g. 2W

i

lamp)

CE 50mJ

C

3.5.8.4.
For a maximum of 10 jump starts
of 2 minutes each during ECU life.

3.5.8.8 Single pulse
T

≤ 60°C

C

I

OUT1...6

≤ 0.6A, max 10 000 pulse C E 50 mJ

Final Data Sheet 48 V4.2, 2003-08-29

TLE 6244X

3.6 Power outputs

2.2A/45V

OUT9...OUT14

3.6.1 Nominal Cur-

rent

3.6.2 Extended Cur-

rent Range

3.6.3 Maximum

Current
(Short Circuit
Shut down
Threshold)

In case of open input (parallel con­trol) or missing power supply the
power stage is switched off. Paral­lel connection of power stages is
possible.

I

I

OUTi

> 2.2A

C

OUT9..

.14

2.2 A

Accumulated operating time C 100 h

4.5V ≤ U

4.5V ≤ U

T

= -40°C

J

T

= 150°C

J

U

> 21V for OUT11...14

UBatt

T

= -40°C

J

T

= 150°C

J

≤ 17V for OUT11..14

UBatt

for OUT9/10

UBatt

B
A

B
A

I

OUTi

I

OUTi

I

OUTi

I

OUTi

2.4

2.2

3

2.7

3.8

3.7

5

4.6

For OUT11... OUT14

Above this limit short circuit to
UBatt is detected. For the duration
of the shutoff delay time t

Voff

(see

3.6.4) the output current is limited
to approximately this value. If the
short circuit condition is still
present after t

, the outputs

Voff

OUT11...OUT14 are switched off.
An error is stored after t

Diag

(see

3.11.4).
The same is true for OUT9,
OUT10 if the static current limita­tion is not enabled.

A
A

A
A

Between -40°C and 150°C an
approximately linear characteristic
line can be assumed.

Between 17V ≤ U

≤ 21V, the

UBatt

short circuit shutdown threshold is
switched for OUT11..14

Final Data Sheet 49 V4.2, 2003-08-29

A power stage that is switched off
in case of SCB can be switched on
again by an off/on cycle at the cor­responding input pin resp. by the
change of the state of the corre­sponding bit for SPI or µsec-bus
by a DEL_DIA instruction or can
be released again by reset. If the
fault register is cleared before this
release (by a DEL_DIA instruc­tion), a new fault entry of SCB is
immediately carried out, even if
SCB condition is no longer
present.

For OUT9, OUT10

Above this limit short circuit to
UBatt is detected. The output cur­rent is limited to approximately this
value if the static current limitation
is configured. An error is stored
after t

(see 3.11.4). If the oper-

Diag

ation leads to an overtemperature
condition, a second protection
level (about 170°C) will change the
output into a low duty cycle PWM
(selective thermal shutdown with
restart) to prevent critical chip tem­peratures

TLE 6244X

Between -40°C and 150°C an
approximately linear characteristic
line can be assumed.

3.6.3.1 Maximum

See Note 1.11.1 C U
Battery Volt­age at Short
Circuit to Bat­tery

3.6.4 Shutoff Delay Shutoff delay of the power stages
after detection of KSUB. For the
duration of t

current is limited to

Voff

maximum current.

3.6.5 On Resis-

tance

= 25°C

T

J

T

= 150°C

J

T

= -40°C

J

For U

UBatt

≤ 10V R

is increased

on

up to 20%.

OUT

9..14

Bt

A
A
A

R
R
R

Voff

on9-14

on9-14

on9-14

36 V

60 215 µs

200
380
150

300
550
220

380
680
280

mΩ
mΩ
mΩ

Final Data Sheet 50 V4.2, 2003-08-29

TLE 6244X

3.6.6 On /off Delay
Times

3.6.7 Leakage Cur­rent

3.6.8 Clamping

3.6.8.1 Clamping

Voltag e

3.6.8.2 Maximum

Clamping En­ergy
T

≤ 110°C

C

3.6.8.3 Maximum

Clamping En­ergy
T

≤ 60°C

C

3.6.8.4 Maximum

Clamping En­ergy with two
Outputs con­nected in par­allel

„On“

„Off“
( M e a s u r e m e n t w i t h o h m i c l o a d )
|t

- t

doff

|

don

switch-on slew rate
switch-off slew rate

U

VDD

= 0V, U

OUT9...14

= 14V
(leakage current of the DMOS,
diagnostic current = 0)

U

VDD

= 0V, U

OUT9...14

= 24V
(leakage current of the DMOS,
diagnostic current = 0)

I

= 0.2A A U

OUTi

Linear decreasing current,
f

= 30Hz (see diagrams

max

E = f(I) on page 66)

I

OUT9...14

I

OUT9...14

≤ 2.2A C E 14 mJ
≤ 1.0A C E 30 mJ

Linear decreasing current,
f

= 30Hz

max

I

OUT9...14

I

OUT9...14

≤ 2.2A C E 17 mJ
≤ 1.0A C E 36 mJ

Each output 75% of the values of

3.6.8.2 resp. 3.6.8.3.

B
B
B
C
C

C
C

A

t

don

t

son

t

doff

t

soff

∆t

s

on

s

off

I

OUTi

10

5
10
10

d

5

2025V/µs

50

µs
µs
µs
µs
µs

V/µs

A

I

OUTi

9...14

40 45 50 V

200µAµA

C

3.6.8.5 Maximum
Clamping En­ergy at Load
Dump

For a maximum of 10 times during
ECU life (load dump with 400ms
and R

= 2Ω over the load, e.g. 2W

i

lamp)

3.6.8.6 Jump Start Each output 150% of the values of

CE 50mJ

C

3.6.8.3.
For a maximum of 10 jump starts
of 2 minutes each during ECU life.

3.6.8.7 Single pulse
T

≤ 60°C

C

I

OUT9...14

pulse

≤ 0.6A, max 10 000

CE 50mJ

Final Data Sheet 51 V4.2, 2003-08-29

TLE 6244X

3.7 Power outputs

3.0A/45V

OUT15...OUT16

3.7.1 Nominal Cur-

rent

3.7.2 Extended Cur-

rent Range

3.7.3 Maximum

Current
(Short Circuit
Shut down
threshold)

In case of open input (parallel con­trol) or missing power supply the
power stage is switched off. Paral­lel connection of power stages is
possible.

I

OUT15,16

> 3.0A

CI

OUT15

I

OUT16

3.0 A

Accumulated operating time C 100 h

U

> 4.5V

UBatt

T

= -40°C

J

T

= 150°C

J

B
A

I

OUT15

I

OUT16

3.3
3

6

5.5

Above this limit short circuit to
UBatt is detected. For the duration
of the shutoff delay time t

Voff

(see

3.6.4) the output current is limited
to approximately this value. If the
short circuit condition is still
present after t

, the outputs

Voff

OUT15/16 are switched off if the
static current limitation is not
enabled. An error is stored after
t

(see 3.11.4).

Diag

Above this limit short circuit to
UBatt is detected. The output cur­rent is limited to approximately this
value if the static current limitation
is configured. An error is stored
after t

(see 3.11.4). If the oper-

Diag

ation leads to an overtemperature
condition, a second protection
level (about 170°C) will change the
output into a low duty cycle PWM
(selective thermal shutdown with
restart) to prevent critical chip tem­peratures.

A
A

Between -40°C and 150°C an
approximately linear characteristic
line can be assumed.

3.7.3.1 Maximum
Battery Volt-

See Note 1.11.1 C U

OUT

15,16

36 V

age at Short
Circuit to Bat­tery

3.7.4 Shuttoff Delay Shutoff delay of the power stages

Bt

Vof f

60 215 µs
after detection of SCB. For the
duration of t

current is limited to

Voff

maximum current.

Final Data Sheet 52 V4.2, 2003-08-29

TLE 6244X

3.7.5 On Resis­tance

3.7.6 On /off Delay
Times

3.7.7 Leakage Cur­rent

TJ = 25°C:

T

= 150°C:

J

T

= -40°C:

J

For U

UBatt

≤ 10V R

is increased

on

up to 20%.

„On“

„Off“
( M e a s u r e m e n t w i t h o h m i c l o a d )
|t

- t

doff

|

don

switch-on slew rate
switch-off slew rate

U

VDD

= 0V, U

OUT15,16

= 14V
(leakage current of the DMOS,
diagnostic current = 0)

U

VDD

= 0V, U

OUT15,16

= 24V
(leakage current of the DMOS,
diagnostic current = 0)

R

A

A

A

B
B
B
C
C

C
C

A

on15,

16

R

on15,

16

R

on15,

16

t

don

t

son

t

doff

t

soff

∆t

s

on

s

off

I

OUT15

,16

150

270

120

d

220

390

170

280

480

210

10

10
10

2025V/µs

50

mΩ
mΩ
mΩ

µs

5

µs
µs
µs

5

µs

V/µs

A

I

OUT15

,16

200µAµA

3.7.8 Clamping

3.7.8.1 Clamping
Voltag e

3.7.8.2 Maximum
Clamping En­ergy
T

≤ 110°C

C

3.7.8.3 Maximum
Clamping En­ergy
T

≤ 60°C

C

3.7.8.4 Maximum
Clamping En­ergy with two
Outputs con­nected in par­allel

I

OUT15,16

= 0.2A U

OUT15,

16

40 45 50 V

Linear decreasing current,
f

= 30Hz (see diagrams

max

E = f(I) on page 67)

I

OUT15,16 ≤ 3.0A C E 18 mJ

I

OUT15,16 ≤ 2.2A C E 20 mJ

I

OUT15,16 ≤ 1.5A C E 24 mJ

I

OUT15,16 ≤ 1.0A C E 40 mJ

Linear decreasing current,
f

max = 30Hz

OUT15,16 ≤ 3.0A C E 20 mJ

I

I

OUT15,16

Each output 75% of the values of

≤ 1.0A C E 46 mJ

C

3.7.8.2 resp. 3.7.8.3.

Final Data Sheet 53 V4.2, 2003-08-29

TLE 6244X

3.7.8.5 Maximum
Clamping En­ergy at Load
Dump

For a maximum of 10 times during
ECU life (load dump with 400ms
and R

= 2Ω over the load, e.g. 2W

i

lamp)

3.7.8.6 Jump Start Each output 150% of the values of

3.7.8.3.
For a maximum of 10 jump starts
of 2 minutes each during ECU life.

3.7.8.7 Single pulse
T

≤ 60°C

C

3.8 Power Outputs

1.1A/45V

OUT7,8,
OUT17,18

I

OUT15, 16

pulses

In case of open input (parallel con­trol) or missing power supply the
power stage is switched off. Paral­lel connection of power stages is

≤ 0.6A, max 10 000

possible.

3.8.1 Nominal Cur-

for OUT7, 8, 17, 18 C I

rent

3.8.2 Extended Cur-

I

OUT7,8,17,18

> 1.1A

rent Range

Accumulated operating time C 100 h

3.8.3 Maximum

Current

4.5V ≤ U

4.5V ≤ U

≤ 17V for OUT7, 8

UBatt

for OUT17,18

UBatt

(Short Circuit
Shut down
Threshold

T

= -40°C

J

T

= 150°C

J

and static
current limita­tion)

CE 50mJ

C

CE 50mJ

OUTi

B
A

I

OUTi

I

OUTi

1.2

1.1

1.1 A

2.2

2.0

A
A

U

> 21V only for OUT7,8

UBatt

T

= -40°C

J

T

= 150°C

J

B
A

I

OUTi

I

OUTi

1.5

1.3

2.5

2.3

A
A

For OUT7, OUT8

Above this limit short circuit to
UBatt is detected. For the duration
of the shutoff delay time t

Voff

(see

3.8.4) the output current is limited
to approximately this value. If the
short circuit condition is still
present after t

, the outputs

Voff

OUT7/8 are switched off. An error
is stored after t

(see 3.11.4).

Diag

The same is true for OUT17
OUT18 if the static current limita­tion is not enabled.

Final Data Sheet 54 V4.2, 2003-08-29

Between -40°C and 150°C an
approximately linear characteristic
line can be assumed.

TLE 6244X

Between 17V ≤ U

≤ 21V, the

UBatt

short circuit shutdown threshold is
switched for OUT7/8

A power stage that is switched off
in case of SCB can be switched on
again by an off/on cycle at the cor­responding input pin resp. by the
change of the state of the corre­sponding bit for SPI or µsec-bus
by a DEL_DIA instruction or can
be released again by reset. If the
fault register is cleared before this
release (by a DEL_DIA instruc­tion), a new fault entry of SCB is
immediately carried out, even if
SCB condition is no longer
present.

For OUT17, OUT18

Above this limit short circuit to
UBatt is detected. The output cur­rent is limited to approximately this
value if the static current limitation
is configured. An error is stored
after t

(see 3.11.4). If the oper-

Diag

ation leads to an overtemperature
condition, a second protection
level (about 170°C) will change the
output into a low duty cycle PWM
(selective thermal shutdown with
restart) to prevent critical chip tem­peratures

Between -40°C and 150°C an
approximately linear characteristic
line can be assumed.

3.8.3.1 Maximum
Battery Volt-

See Note 1.11.1 C U

OUT

17,18

36 V

age at Short
Circuit to Bat­tery

3.8.4 Shutoff Delay Shutoff delay of the power stages

Bt

Vof f

60 215 µs
after detection of SCB. For the
duration of t

current is limited to

Voff

maximum current.

Final Data Sheet 55 V4.2, 2003-08-29

TLE 6244X

3.8.5 On Resis­tance

3.8.6 On/off Delay
Times

3.8.7 Leakage Cur­rent

TJ = 25°C

T

= 150°C

J

T

= -40°C

J

For U
to 20%; condition: U

UBatt

≤ 10V R

is increased up

on

> 4.5 V

VDD

For OUT8 only:

3.5V<(U
T

= 25°C

J

T

= 150°C

J

T

= -40°C

J

VDD

, U

UBatt

)<4.5V

„On“

„Off“
( M e a s u r e m e n t w i t h o h m i c l o a d )
|t

- t

doff

|

don

Switch-on slew rate
Switch-off slew rate

For OUT7,8, OUT1718:

U

VDD

= 0V, U

= 14V (leakage

OUTi

current of the DMOS, diagnostic
current = 0)

R

A

A

A

A
A
A

B
B
B
C
C

C
C

A

17,18

R

17,18

R

17,18

R
R
R

t
t
t
t

I

on7,8,

on7,8,

on7,8,

on

on

on

don

son

doff

soff

∆t

s

on

s

off

OUTi

400

780

290

d

620

1200

450

780

1500

560

1300
2200
1050

10

10
10

2540V/µs

50

mΩ
mΩ
mΩ

mΩ
mΩ
mΩ

µs

5

µs
µs
µs

5

µs

V/µs

U

VDD

= 0V, U

= 24V (leakage

OUTi

current of the DMOS, diagnostic
current = 0)

3.8.8 Clamping For OUT7,8, OUT17,18:

3.8.8.1 Clamping

= 0.2A A U

I

OUTi

Voltag e

3.8.8.2 Maximum

Clamping En­ergy
T

≤ 110°C

C

3.8.8.3 Maximum

Clamping En-

Linear decreasing current,
f

= 10Hz (see diagrams

max

E = f(I) on page 67)

I

≤ 0.6A

OUTi

I

≤ 1.1A

OUTi

Linear decreasing current,
f

= 10Hz

max

ergy
T

≤ 60°C

C

I

OUTi

I

OUTi

≤ 0.6
≤ 1.1A

A

C
C

C
C

I

OUTi

OUTi

200µAµA

40 45 50 V

E
E

E
E

10

7

12

8.5

mJ
mJ

mJ
mJ

Final Data Sheet 56 V4.2, 2003-08-29

TLE 6244X

3.8.8.4 Maximum

Clamping En-

Each output 75% of the values of

3.8.8.2 resp. 3.8.8.3.
ergy with two
Outputs con­nected in par­allel

3.8.8.5 Maximum
Clamping En­ergy at Load

For a maximum of 10 times during
ECU life (load dump with 400ms
and R

= 2Ω over the load)

i

Dump

3.8.8.6 Jump Start Each output 150% of the values of

3.8.8.3.
For a maximum of 10 jump starts
of 2 minutes each during ECU life

C

CE 15mJ

C

Final Data Sheet 57 V4.2, 2003-08-29

TLE 6244X

3.9 SPI Interface

The timing of TLE6244X is defined as follows:

- The change at output (SO) is forced by the rising edge of the SCK signal.

- The input signal (SI) is sampled on the falling edge of the SCK signal.

- The data received during a writing access is taken over into the internal registers on the rising edge of the
SS
signal, if exactly 16 SPI clocks have been counted during SS
(Also: Only if exactly 16 SPI clocks have been counted the instruction DEL_DIA resets the diagnostic regis­ters.)

= active.

SS

SCK

SO

SI

13

10

2

1

11

3

8

9

14

12

5

MSB IN

tristate

6

4

Bit (n-3) Bit 0; LSB

Bit (n-3)Bit (n-2)

Bit (n-4)...1

Bit (n-4)...1

LSB IN

7

X see 3.9.5

n = 16

Final Data Sheet 58 V4.2, 2003-08-29

3.9.1 Input SCK SPI clock input

TLE 6244X

3.9.1.1 Low Level B U

3.9.1.2 High Level B U

3.9.1.3 Hysteresis C

3.9.1.4 Input Capacity

3.9.1.5 Input Current Pull up current source connected

CC

A-I

SCKL

SCKH

∆U

SCK

to VDD

3.9.2 Input SS

Slave select signal

3.9.2.1 Low Level TLE6244X is selected B U

3.9.2.2 High Level B U

3.9.2.3 Hysteresis C ∆U

3.9.2.4 Input Capaci-

CC

ty

3.9.2.5 Input Current Pull up current source connected

A-I

to VDD

3.9.3 Input SI SPI data input

3.9.3.1 Low Level B U

3.9.3.2 High Level B U

3.9.3.3 Hysteresis C ∆U

3.9.3.4 Input Capaci-

CC

ty

SCK

SCK

SSL

SSH

SS

SS

SS

SIL

SIH

SI

SI

1.0 V

2.0 V

0.1 0.6 V

10 pF

10 20 50 µA

1.0 V

2.0 V

0.1 0.6 V

10 pF

10 20 50 µA

1.0 V

2.0 V

0.1 0.6 V

10 pF

3.9.3.5 Input Current Pull up current source connected

A-I

SI

10 20 50 µA

to VDD

3.9.4 Output SO Tristate output of the TLE6244X

(SPI output);
On active reset (RST

) output SO is

in tristate.

3.9.4.1 Low Level I

3.9.4.2 High Level I

= 2mA A U

SO

= -2mA A U

SO

SOL

SOH

U

VDD

0.4 V

V

- 1.0

3.9.4.3 Capacity Capacity of the pin in tristate C C

3.9.4.4 Leakage Cur-

In tristate A I

SO

SO

-10 10 µA

10 pF

rent

Final Data Sheet 59 V4.2, 2003-08-29

TLE 6244X

3.9.5 Timing 1. Cycle-Time

(referred to master)

2. Enable Lead Time
(referred to master)

3. Enable Lag Time
(referred to master)

4. Data Valid CL = 50pF (5 MHz)
Data Valid CL = 200pF (2MHz)
(referred to TLE6244X)

5. Data Setup Time
(referred to master)

6. Data Hold Time
(referred to master)

7. Disable Time
(referred to TLE6244X)

8. Transfer Delay
(referred to master)

B

t

cyc

C

C

C
C

C

C

C

C

t

t

t
t

t

t

t

t

lead

lag

v

v

su

h

dis

dt

200

100

150

50

20

150

100
150

100

ns

ns

ns

ns
ns

ns

ns

ns

ns

9. Select time
(referred to master)

10. Access time
(referred to master)

11. Serial clock high time
(referred to master)

12. Serial clock low time

13. Disable Lead Time

14. Disable Lag Time

C

C

C

C

t

sel

t

acc

t

SCKH

t

SCKL

50

8.35

50

120

nsec

µsec

ns

ns

C

t

dld

250

ns

C

t

dlg

250

ns

Final Data Sheet 60 V4.2, 2003-08-29

3.10 µsec-bus

FCL/IN16

FDA/IN6

SSY/IN7

t

cyc

t

setup

t

hold

t

shold

t

SF

TLE 6244X

t

switch

Timing µsec-bus

Notes for the timing:

Timing definitions are starting or ending at a voltage level of 1V (Low Level) resp. 2V (High Level).

During SSY = high the clock at FCL may be interrupted, i.e. there is no need for a clock during SSY = high.
The clock signal may remain on high or low statically during SSY = high.
A rising edge at SSY and a falling edge at FCL must not occur simultaneously!
On the rising edge of SSY the 16 bits clocked in TLE6244X by the last 16 falling edges at FCL are latched.

3.10.1 Input FCL,

FDA, SSY

3.10.1.1 Low Level B U

3.10.1.2 High Level B U

3.10.1.3 Hysteresis

3.10.1.4 Input Ca­pacity

3.10.1.5 Input Cur­rent

3.10.2 Timing Cycle Time C t

µsec-bus interface pins

FCLl

U

FDAl

U

SSYl

FCLh

U

FDAh

U

SSYh

∆U

C

CC

Pull up current source connected

AI

to VDD

∆U
∆U

C
C

I
I

FCL
FDA
SSY

FCL

FDA

SSY

FCL

FDA

SSY

CYC

Data setup time C t

Data hold time C t

Switching time on FCL
f

< 10MHz

FCL

Ct

setup

hold

switch

1.0 V

2.0 V

0.1 0.6 V

10 pF

51020µA

62 nsec

10 nsec

10 nsec

30 nsec

Final Data Sheet 61 V4.2, 2003-08-29

TLE 6244X

3.11 Diagnostics

3.11.1 Diagnostic

Thresholds
Power Stages

3.11.1.1 Open Load
(OL)

3.11.1.2 Short to
Ground
(SCG)

Switching time on FCL
f

> 10MHz

FCL

Ct

Select hold time C t

FCL Low time
FCL High time

SSY Low time
SSY High time

Time between rising edge of SSY

C

tFCLL

C

tFCLH

C

tSSYL

C

tSSYH

C

and next falling edge of FCL

Output turned off B U

Output turned off B U

switch

shold

25 10 nsec

25

8nsec

nsec

25

25

nsec

25

tSF 8nsec

OUT1..

18

OUT1...

18

U

0.5V

0.54

U

0.5V

VDD

-

*

VDD

-

U

VDDUVDD

0.5V

0.54

0.54

*

U

VDD

U

0.5V

V

+

V

*

VDD

+

3.11.1.3 Short to Bat­tery (SCB)

3.11.1.4 Overtem­perature

3.11.2 Bias Voltage

Open Load
Power Stages

3.11.3 Diagnostic

Currents
Power Stages

See 3.5.3, 3.6.3, 3.7.3, 3.8.3

Output turned on
Individually for each stage

Output turned off, I

4.5V ≤ U

≤ 5.5V, output turned

VDD

OUT1...18

= 0 A U

off

U

OUT1...18

= 14V (diagnostic cur-

rent incl. leakage current)

U

OUT1...18

U

OUT1...18

U

OUT1...18

= 0V

= OL-Threshold

= SCG-Threshold

BT

A

A

C

C

OUT1...

18

I

OUT

-I

OUT

I

OUT

-I

OUT

J

150 °C

0.6 *

U

270

50

220

40

VDD

0.7 *

U

VDD

580

130

0.76*

U

VDD

980

250

980

250

V

µA

µA

µA

µA

Final Data Sheet 62 V4.2, 2003-08-29

TLE 6244X

3.11.4 Filtering

Time Power
Switches

3.11.5 Diagnostic

Threshold
UBatt

3.12 Reverse Cur-

rents

3.12.1 Reverse Cur-

rent at
OUT1...18
without Sup­ply Voltage

Time from occurrence of one of

B
the errors ’short to ground’, ’open
load’ or ’short to battery’ until the
fault is entered into the corre­sponding diagnostic register.

Time from occurrence of OT until

C
the information is entered into the
corresponding diagnostic register.

Bit Ubatt in DIA_REG5 U

U

≤ 1V

VDD

Static

C
C
C
C

Dynamic
(Test pulse 1 according to ISO:
100V, R

= 10W, 2ms)

i

C
C
C
C

t

Diag

t

DiatOT

th,UB

-I

O1...6

-I

O9...16

-I

O7,8

-I

O17,18

-I

O1...6

-I

O9...16

-I

O7,8

-I

O17,18

60

3

240

30

µs

µs

19V

3
3

0.8

0.8

10
10

1.5

1.5

A
A
A
A

A
A
A
A

3.12.2 Reverse Cur­rent at
OUT1...OUT18
in Operation
Mode

4.5V ≤ U

VDD

≤ 5.5V

Pulsed power stage.
Neighboring stages, reset, input
signals of the power stages, VDD­monitoring, SPI interface (incl. reg­isters) and µsec-bus must not be
disturbed. Diagnostics of fault con­ditions at neighboring stages is still
possible. Control bits in the SPI
registers (serial control of power
stages are not disturbed).

Open load failure at neighboring
stages may be detected as short
to ground

Open load failure at neighboring
stages are not detected as short
to ground

Destruction limit C

-I

C
C
C

C
C
C
C

C
C
C

O1...16

-I

-I

O17,18

-I

O1...4

-I

O5...16

-I

-I

O17,18

-I

O1...6

-I

O9...16

-I

-I

O17,18

O7,8

O7,8

O7,8

1

0.3

0.3

0.5

0.25

0.3

0.3

3
3

0.8

0.8

A
A
A

A
A
A
A

A
A
A
A

Final Data Sheet 63 V4.2, 2003-08-29

TLE 6244X

3.13 VDD-Monitor-

ing ABE

3.13.1 Output U

3.13.1.1 Low Level U

Bidirectional: open drain output /
input with pull up current source
An external current limitation
must guarantee I
any U

ABE

= Low (after t

ABE

2.7V < U

< 4.5V... 4.7V or

VDD

5.3V... 5.5V < U

ABE

glitch)

VDD

< 5 mA for

for:

< 36V or
Testmode (see 3.13.5 or 3.13.6) or
Pin GND_ABE is open

U

VDD
VDD

> 4.5V, I
= 2.7V, I

ABE
ABE

<5mA

<1mA,
in case of less current, ohmic
behavior can be assumed

A
A

U
U

ABE

ABE

1.2

1.0

V
V

3.13.1.2 Maximum
Voltag e

No current recovery on VDD,
UBatt and the logical pins
(SS

,SCK,SI,SO,INx,RST) in case

of short to battery at ABE

(up to

CU

36V)

3.13.2 Input

3.13.2.1 Low Level B U

3.13.2.2 High Level B U

3.13.2.3 Hysteresis C ∆U

3.13.2.4 Input Cur­rent

3.13.3 Overvoltage

Pull up current source connected
to VDD

-0.25V ≤ U

-0.25V ≤ U

-0.3V ≤ U

ABE

ABE

ABE

≤ U

VDD

≤ U

VDD

< -0,25V

-1.7 V

-1.5 V

Voltage referred to GND_ABE

A
C
C

-I

-I

-I

BV

Threshold

ABE

ABEL

ABEH

ABE

ABE

ABE

ABE

DDth_h

36 V

0.3 *
U

VDD

0.7 *

U

VDD

0.2 1.0 V

20
15

40
40

100
100
300

5.3 5.5 V

V

V

µA
µA
µA

Final Data Sheet 64 V4.2, 2003-08-29

TLE 6244X

3.13.4 Undervolt-

age Thresh­old

3.13.5 Test Mode:

Reducing the
Overvoltage
Threshold

3.13.6 Test Mode:

Lifting the
Undervoltage
Threshold

3.13.7 Suppres-

sion of
Glitches

3.13.8 GND_ABE

Voltage referred to GND_ABE BV

Voltage referred to GND_ABE

Voltage referred to GND_ABE

Periodical alternating between

BV

BV

At

DDth_l

DDth_h

DDth_l

glitch

overvoltage and normal operating
voltage with T< 50µs and overvolt­age duration > 5µs leads to over­voltage detection.
If the transition from undervoltage
to overvoltage is faster than the fil­tering time t
t

for overvoltage detection is

glitch

, the filtering time

glitch

not started again. The same is
valid for reverse order.

4.5 4.7 V

4.5 4.7 V

5.3 5.5 V

50 215 µs

3.13.8.1 Permissible
Offset be­tween
GND_ABE
and GND

3.13.8.2 Bond Lift /
Solder Crack
on
GND_ABE

Pin ABE

goes LOW
(see 3.13.1.1).
The power stages are switched off.
The over- and undervoltage
thresholds are increased by typi­cally 700mV for T

= 25°C.

A

C ∆U

GND

0.3 V

Final Data Sheet 65 V4.2, 2003-08-29

3.14 Clamping Energy

TLE 6244X

3.14.1 E = f(I

E / mJ

30

20

10

0

OUT1...6

), 2.2A Power Stages with 70V Clamping

Injector Drivers
Clamping Voltage 64... 76V

f

= 50 Hz

+

+

+

0 0.5 1.0 1.5 2.0

max

T

+

Cmax

= 110°C

+

+

I

/ A

MAX

3.14.2 E = f (I

E / mJ

30

20

10

0

OUT9...A14

), 2.2A Power Stages with 45V Clamping

2.2A Power Stage
Clamping Voltage 40... 50V
f

= 30 Hz

+

+

00.51.01.52.0

max

T

+

Cmax

= 110°C

+

+

I

MAX

/ A

Final Data Sheet 66 V4.2, 2003-08-29

TLE 6244X

3.14.3 E = f(I

E / mJ

15

10

OUT7,8,17,18

), 1100mA Power Stages with 45V Clamping

1.1A Power Stage
Clamping Voltage 40... 50V

f
T

+

+

5

0

0 0.25 0.5 0.75 1.0

max

Cmax

= 10 Hz

= 110°C

+

I

MAX

/ A

3.14.4 E = f(I

E / mJ

30

20

10

0

OUT15, OUT16

), 3.0A Power Stages with 45V Clamping

3.0A Power Stage
Clamping Voltage 40... 50V
f

= 30 Hz

+

+

0 0.5 1.0 1.5 2.0

max

T

Cmax

= 110°C

+

2.5

+

/ A

I

MAX

Final Data Sheet 67 V4.2, 2003-08-29

TLE 6244X

4. ESD

All pins of the IC have to be protected against electrostatic discharge (ESD) by appropriate pro­tection
components.

The integrated circuit has to meet the requirements of the „Human Body Model“ with U

C = 100pF and R2 = 1,5kΩ without any defect or destruction of the IC.

Appropriate measures to reach the required ESD capability have to be coordinated.

The ESD capability of the IC has to be verified by the following test circuit.

S2

(1)(2)

R1

R2

S1

U

S

V

DC-Volt­meter

C

U

C

DUT

= 2kV,

C

S3

U

= + 2kV

C

R

= 100kΩ

1

R

= 1,5kΩ

2

C = 100pF

Number of pulses each pin: 18 in all
Frequency: 1Hz

Arrangement and performance:
The requirements of MIL883D Method 3015 (latest revision) have to be fulfilled.

Final Data Sheet 68 V4.2, 2003-08-29

5. Package Outline

TLE 6244X

Final Data Sheet 69 V4.2, 2003-08-29

TLE 6244X

Edition 2003-08-29
Published by Infineon Technologies AG,

St.-Martin-Strasse 53,
D-81541 München, Germany

© Infineon Technologies AG 11/28/03.

All Rights Reserved.

Attention please!

The information herein is given to describe certain components and shall not be considered as warranted characteristics.
Terms of delivery and rights to technical change reserved.
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descr ipt ions and charts

stated her ein.
Infineon Technologies is an approved CECC manufacturer.

Information

For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon T echnologies Office in Germany
or our Infineon Technologies Representatives worldwide.

Warnings

Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your ne ares t
Infineon Technologies Office.

Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies,
if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or
effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain
and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.

Final Data Sheet 70 V4.2, 2003-08-29