Datasheet THAT4301S, THAT4301P Datasheet (THAT Corporation)

Page 1
THAT Corporation; 45 Sumner Street; Milford, Massachusetts 01757-1656; USA
Tel: +1 (508) 478-9200; Fax: +1 (508) 478-0990; Web: www.thatcorp.com
THAT Corporation
THAT Analog Engine
®
IC Dynamics Processor
THAT 4301, 4301A
FEATURES
High-Performance Voltage Controlled Amplifier
High-Performance RMS-Level Detector
Three General-Purpose Opamps
Wide Dynamic Range: >115 dB
Low THD: <0.03%
Low Cost: $4.39 (‘000s)
DIP & Surface-Mount Packages
APPLICATIONS
Compressors
Limiters
Gates
Expanders
De-Essers
Duckers
Noise Reduction Systems
Wide-Range Level Meters
Description
THAT 4301 Dynamics Processor, dubbed “THAT Analog Engine,” combines in a single IC all the active circuitry needed to construct a wide range of dynamics processors. The 4301 includes a high-performance, exponen­tially-controlled VCA, a log-responding RMS-level sensor and three general- purpose opamps.
The VCA provides two opposing-polarity, volt­age-sensitive control ports. Dynamic range ex­ceeds 115 dB, and THD is typically 0.003% at 0 dB gain. In the 4301A, the VCA is selected for low THD at extremely high levels. The RMS de
­tector provides accurate rms-to-dc conversion over an 80 dB dynamic range for signals with
crest factors up to 10. One opamp is dedicated as a current-to-voltage converter for the VCA, while the other two may be used for the signal path or control voltage processing.
The combination of exponential VCA gain con­trol and logarithmic detector response — “deci­bel-linear” response simplifies the mathematics of designing the control paths of dynamics processors. This makes it easy to de­sign audio compressors, limiters, gates, ex­panders, de-essers, duckers, noise reduction systems and the like. The high level of integra
-
tion ensures excellent temperature tracking be
­tween the VCA and the detector, while minimizing the external parts count.
OUT
CTIT
IN
-
+
-
1
18
11
17
14
13
12
15
16
19
20
2
5
4
9
10 8
6
7
-
OA1
+
VCC
THAT4301
EC-
EC+
IN
OUT
SYM
VCA
OA3
+
OA2
GND
VEE
RMS
Figure 1. Block Diagram (pin numbers are for DIP only)
Page 2
THAT Corporation; 45 Sumner Street; Milford, Massachusetts 01757-1656; USA
Tel: +1 (508) 478-9200; Fax: +1 (508) 478-0990; Web: www.thatcorp.com
Page 2 Rev. 04/10/02
SPECIFICATIONS
1,2
Absolute Maximum Ratings (TA= 25°C)
Positive Supply Voltage (VCC) +18 V
Negative Supply Voltage (V
EE
) -18 V
Supply Current (I
CC
)20mA
Power Dissipation (P
D
)(TA= 75°C) 700 mW
Operating Temperature Range (T
OP
) 0 to +70°C
Storage Temperature Range (T
ST
) -40 to +125°C
Overall Electrical Characteristics
Parameter Symbol Conditions Min Typ Max Units
Positive Supply Voltage V
CC
+7 +15 V
Negative Supply Voltage V
EE
-7 -15 V
Positive Supply Current I
CC
—1218 mA
Negative Supply Current I
EE
-12 -18 mA
Thermal Resistance q
J-C
SO-Package 140 °C/W
VCA Electrical Characteristics
3
4301 4301A
Parameter Symbol Conditions Min Typ Max Min Typ Max Units
Input Bias Current I
B(VCA)
No Signal 30 400 30 400 pA
Input Offset Voltage V
OFF(VCA In)
No Signal ±4 ±15 ±4 ±15 mV
Input Signal Current I
IN(VCA)
or I
OUT(VCA)
175 750 175 750 mArms
Gain at 0V Control G
0
EC+=EC–= 0.000V -0.4 0.0 +0.4 -0.4 0.0 +0.4 dB
Gain-Control Constant T
A
= 25°C (T
CHIP
@ 55°C)
-60 dB < gain < +40dB
E
C+
/Gain (dB) EC+& SYM 6.4 6.5 6.6 6.4 6.5 6.6 mV/dB
EC-/Gain (dB) E
C-
-6.4 -6.5 -6.6 -6.4 -6.5 -6.6 mV/dB
Gain-Control TempCo DEC/ DT
CHIP
Ref T
CHIP
= 27°C — +0.33 — +0.33 %/°C
Gain-Control Linearity -60 to +40 dB gain 0.5 2 0.5 2 %
Off Isolation EC+=SYM=-375mV, EC-=+375mV 110 115 110 115 dB
Output Offset Voltage Change DV
OFF(OUT)
R
out
= 20kW
0 dB gain 1 3 1 3 mV
+15 dB gain 2 10 2 10 mV
+30 dB gain 5 25 5 25 mV
Gain Cell Idling Current I
IDLE
—20— —20— mA
Output Noise e
n(OUT)
20 Hz-20 kHz
R
out
= 20kW
0 dB gain -96 -94 -96 -94 dBV
+15 dB gain -85 -83 -85 -83 dBV
Total Harmonic Distortion THD V
IN
= 0 dBV, 1 kHz
0 dB gain 0.003 0.007 0.003 0.007 %
1. All specifications subject to change without notice.
2. Unless otherwise noted, T
A
=25°C, VCC= +15V, VEE= -15V; VCA
SYM
adjusted for min THD@1V,1kHz, 0 dB gain.
3. Test circuit is the VCA section only from Figure 2.
Page 3
THAT Corporation; 45 Sumner Street; Milford, Massachusetts 01757-1656; USA
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THAT 4301 Dynamics Processor IC Page 3
SPECIFICATIONS
1,2
(Cont’d.)
VCA Electrical Characteristics3(Cont’d.)
4301 4301A
Parameter Symbol Conditions Min Typ Max Min Typ Max Units
Total Harmonic Distortion (cont’d.) THD V
IN
= +10 dBV, 1 kHz
0 dB gain 0.03 0.07 0.03 0.07 %
–15 dB gain 0.035 0.09 — 0.035 0.09 %
V
OUT
= +10 dBV, 1 kHz
+15 dB gain 0.035 0.09 0.035 0.09 %
V
IN
= +19.5 dBV, 1 kHz
0 dB gain 0.05 0.09 %
Symmetry Control Voltage V
SYM
minimum THD -2.5 0 +2.5 -2.5 0 +2.5 mV
RMS Detector Electrical Characteristics
4
Parameter Symbol Conditions Min Typ Max Units
Input Bias Current I
B (RMS)
No Signal 30 400 pA
Input Offset Voltage V
OFF(RMS In)
No Signal ±4 ±15 mV
Input Signal Current I
IN(RMS)
175 750 mA
Input Current for 0 V Output I
in0
IT= 7.5mA 6 8.5 12 mA
Output Scale Factor E
O
/ 20log(Iin/I
in0
) 31.6nA< IIN< 1mA
TA= 25°C (T
CHIP
»55°C) 6.4 6.5 6.6 mV/dB
Scale Factor Match (RMS to VCA) -20 dB < VCA Gain < +20 dB
1mA<I
in (DET)
<100mA .985 1 1.015
Output Linearity f
IN
= 1kHz
1mA<I
in
< 100mA 0.1 dB
100nA < I
in
< 316mA 0.5 dB
31.6nA < Iin< 1mA 1.5 dB
Rectifier Balance f
IN
= 100 Hz, t = .001 s
1mA< Iin< 100mA –20 20 %
Crest Factor 1ms pulse repetition rate
0.2 dB error 3.5
0.5 dB error 5
1.0 dB error 10
Maximum Frequency for 2 dB Additional Error I
in
³ 10mA 100 kHz
I
in
³ 3mA 45 kHz
Iin³ 300nA 7 kHz
Timing Current Set Range I
T
1.5 7.5 15 mA
Voltage at ITPin IT= 7.5mA -10 +20 +50 mV
Timing Current Accuracy ICT/I
T
IT= 7.5mA 0.90 1.1 1.30
Filtering Time Constant t T
CHIP
=55°C
()0 026.
C
I
T
T
s
Output Temp. Coefficient DEo/ DT
CHIP
Re: T
CHIP
=27°C 0.33 %/°C
Output Current I
OUT
–300mV < V
OUT
< +300mV ±90 ±100 mA
4. Except as noted, test circuit is the RMS-Detector section only from Figure 2.
Page 4
THAT Corporation; 45 Sumner Street; Milford, Massachusetts 01757-1656; USA
Tel: +1 (508) 478-9200; Fax: +1 (508) 478-0990; Web: www.thatcorp.com
Page 4 Rev. 04/10/02
Specifications
1,2
(Cont’d)
Opamp Electrical Characteristics
5
OA1 OA2 OA3
Parameter Symbol Conditions Min Typ Max Min Typ Max Min Typ Max Units
Input Offset Voltage V
OS
±0.5 ±6—±0.5 ±6—±0.5 ±6mV
Input Bias Current I
B
150 500 — 150 500 150 500 nA
Input Offset Current I
OS
15 50 15 50 N/A nA
Input Voltage Range I
VR
±13.5 — ±13.5 — N/A V
Common Mode Rej. Ratio CMRR RS<10k 100 — 100 — N/A
Power Supply Rej. Ratio PSRR VS=±7V to ±15V 100 — 100 — 100
Gain Bandwidth Product GBW (@50kHz) 5 5 5 MHz
Open Loop Gain A
VO
RL=10k 115 110 — 125
RL=2k N/A N/A 120 —
Output Voltage Swing V
O@RL
=5kW — ±13 ±13 ±14 V
VO@RL=2kW N/A N/A — ±13 — V
Short Circuit Output Current 4 4 12 mA
Slew Rate SR 2 2 2 V/ms
Total Harmonic Distortion THD 1kHz, A
V
=1, RL=10kW — 0.0007 0.003 — 0.0007 0.003 — 0.0007 0.003 %
1kHz, AV=–1, RL=2kW N/A N/A — 0.0007 0.003 %
Input Noise Voltage Density e
n
fO=1kHz 6.5 10 7.5 12 7.5 12
nV Hz
Input Noise Current Density i
n
fO=1kHz 0.3 0.3 0.3
pA Hz
50K
R5
47uF
C1
10uF
C4
22uF
C6
300K
R4
51
R3
1%
R1
1%
R2
47pF
C2
1%
10K0
R6
47uF
C3
1%
2M00
R7
100n
C7
100n
C8
Ct
OA2
OA1
VEE
VCC
GND
-
+
VCA
-
-
+
VCA SYM
IN
SIGNAL
Ec-
OUT
SIGNAL
OUT
RMS
+15V
+15V
-15V
-15V
-15V
20K0
20K0
THAT4301
IN
RMS
It
SYM
OUT
IN
EC-
EC+
OA3
OUT
+
Figure 2. VCA and RMS detector test circuit
5. Test circuit for opamps is a unity-gain follower configuration, with load resistor R
L
as specified.
Page 5
THAT Corporation; 45 Sumner Street; Milford, Massachusetts 01757-1656; USA
Tel: +1 (508) 478-9200; Fax: +1 (508) 478-0990; Web: www.thatcorp.com
THAT 4301 Dynamics Processor IC Page 5
Pin Name DIP P in SO Pin
RMS In 1 3
I
T(ITime
)24
No Connection 3 5
RMS Out 4 6
C
T(CTime
)57
OA2 -In 6 9
OA2 Out 7 10
OA2 +In 8 11
GND 9 12
VEE 10 13
VCC 11 18
OA3 Out 12 19
VCA Out 13 20
SYM 14 22
E
C+
15 23
Pin Name DIP P in SO Pin
E
C-
16 24
VCA In 17 25
OA1 Out 18 26
OA1 -In 19 27
OA1 +In 20 28
No Connection 1
No Connection 2
No Connection 8
No Connection 14
No Connection 15
No Connection 16
No Connection 17
No Connection 21
No Connection 29
No Connection 30
Table 1. Pin Connections
1
B
A
C D
P
J
I
K
N
L
M
O
H
F
G
E
ITEM
A B C D E F G H
I J K L M N O P
MILLIMETERS INCHES
24.8 Max.
0.98 Max
24.2 +/-0.2 0.95 +/-0.008
6.4 +/-0.2 0.25 +/-0.008
7.62 +/-0.25
0.30 +/-0.01
2.54 +/-0.15 0.10 +/-0.006
0.46 +0.15 -0.1 0.02 +0.006 -0.004
1.0 +/-0.15
0.04 +/-0.006
1.5 Typ.
0.06 Typ.
0.98 Typ.
0.04 Typ.
1.5 0.06
1.75
0.07
3.25 +/-0.15 0.13 +/-0.006
4.7 Max.
0.19 Max.
0.51 Min.
0.02 Min.
2.8 Min.
0.11 Min.
0.25 +0.15 -0.05 0.01 +0.006 -0.002
0-15
Figure 3. Plastic dual in-line package outline
B
C
J
G
I
H
ED
A
1
+ 0.1 - 0.05
Typ .
+/- 0.2
+ 0.1 - 0.05
+/- 0.4
+/- 0.3
J0.2
I
0.8
H0.15
G2.3
F 0.85 MAX.
E1.0
D
0.4
C10.3
B7.5
15.4A
MILLIMETERSITEM
F
+/- 0.1
+/- 0.15
INCHES
0.60 +/- 0.012
0.29 +/- 0.008
0.41 +/- 0.016
0.002 +0.004 -0.002
0.039 Typ.
0.033 Max.
0.09 +/- 0.006
0.006 +/- 0.004
0.031
0.008 +0.004 -0.002
0-10
Figure 4. Plastic surface-mount package outline
Ordering Information
Plastic DIP 4301P 4301PA
Plastic Surface Mount 4301S Inquire
Page 6
THAT Corporation; 45 Sumner Street; Milford, Massachusetts 01757-1656; USA
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Page 6 Rev. 04/10/02
Figure 5. VCA Gain vs. Control Voltage (Ec-) at 25°C Figure 6. VCA 1kHz THD+Noise vs. Input, -15 dB Gain
Representative Data
Figure 7. VCA 1kHz THD+Noise vs. Input, +15 dB Gain Figure 8. VCA 1kHz THD+Noise vs. Input, 0 dB Gain
Figure 9. VCA THD vs. Frequency, 0 dB Gain, 1Vrms Input Figure 10. RMS Output vs. Input Level, 1 kHz & 10 kHz
Figure 11. Departure from Ideal Detector Law vs. Level Figure 12. Detector Output vs. Frequency at Various Levels
Page 7
Theory of Operation
THAT 4301 Dynamics Processor combines THAT Corporation’s proven Voltage-Controlled Amplifier (VCA) and RMS-Level Detector designs with three general-purpose opamps to produce an Analog En
-
gine useful in a variety of dynamics processor appli
­cations. For details of the theory of operation of the VCA and RMS-Detector building blocks, the inter
­ested reader is referred to THAT Corporation’s data sheets on the 2150 Series VCAs and the 2252 RMS-Level Detector. Theory of the interconnection of exponentially-controlled VCAs and log-responding level detectors is covered in THAT Corporation’s ap
­plication note AN101, The Mathematics of Log-Based Dynamic Processors.
The VCA — in Brief
THAT 4301 VCA is based on THAT Corporation’s highly successful complementary log-antilog gain cell topology, as used in THAT 2150-Series IC VCAs, and the modular 202 Series VCAs. THAT 4301 is inte
­grated using a fully complementary, BiFET process. The combination of FETs with high-quality, comple
­mentary bipolar transistors (NPNs and PNPs) allows additional flexibility in the design of the VCA over previous efforts.
Input signals are currents to the VCA IN pin. This pin is a virtual ground, so in normal operation an in­put voltage is converted to input current via an ap­propriately sized resistor (R
1
in Figure 2, Page 4). Because dc offsets present at the input pin and any dc offset in preceeding stages will be modulated by gain changes (thereby becoming audible as thumps), the input pin is normally ac-coupled (C
1
in Figure 2).
The VCA output signal is also a current, inverted
with respect to the input current. In normal opera
­tion, the output current is converted to a voltage via inverter OA
3
, where the ratio of the conversion is de
­termined by the feedback resistor (R
2
, Figure 2) con
­nected between OA
3
‘s output and its inverting input.
The signal path through the VCA and OA
3
is
noninverting.
The gain of the VCA is controlled by the voltage
applied to E
C–,EC+
, and SYM. Gain (in decibels) is
proportional to E
C+–EC-
, provided EC+and SYM are
at essentially the same voltage (see below). The con
­stant of proportionality is –6.5 mV/dB for the voltage at E
C–
, and 6.5 mV/dB for the voltage at EC+and SYM.
As mentioned, for proper operation, the same
voltage must be applied to E
C+
and SYM, except for a small (±2.5 mV) dc bias applied between these pins. This bias voltage adjusts for internal mismatches in the VCA gain cell which would otherwise cause small differences between the gain of positive and negative half-cycles of the signal. The voltage is usually ap
-
plied via an external trim potentiometer (R
5
in Figure
2), which is adjusted for minimum signal distortion at unity (0 dB) gain.
The VCA may be controlled via E
C-
, as shown in
Figure 2, or via the combination of E
C+
and SYM. This connection is illustrated in Figure 13. Note that this figure shows only that portion of the circuitry needed to drive the positive VCA control port; cir
-
cuitry associated with OA
1
,OA2and the RMS detector
has been omitted.
While the 4301’s VCA circuitry is very similar to that of the THAT 2150 Series VCAs, there are several important differences, as follows:
1) Supply current for the VCA is fixed internally. Approximately 2mA is available for the sum of input and output signal currents. (This is also the case in a 2150 Series VCA when biased as recommended.)
2) The signal current output of the VCA is inter
­nally connected to the inverting input of an on-chip opamp. In order to provide external feedback around this opamp, this node is brought out to a pin.
3) The control-voltage constant is approximately
6.5 mV/dB, due primarily to the higher internal oper
­ating temperature of the 4301 compared to that of the 2150 Series.
4) The input stage of the 4301 VCA uses inte
­grated P-channel FETs rather than a bias-current corrected bipolar differential amplifier. Input bias currents have therefore been reduced.
The RMS Detector — in Brief
The 4301’s detector computes rms level by recti
­fying input current signals, converting the rectified current to a logarithmic voltage, and applying that voltage to a log-domain filter. The output signal is a dc voltage proportional to the decibel-level of the rms
THAT Corporation; 45 Sumner Street; Milford, Massachusetts 01757-1656; USA
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THAT 4301 Dynamics Processor IC Page 7
50K
R5
47uF
C1
300K
R4
51
R3
1%20K0
R1
1%20K0
R2
47pFC2
CtIt
THAT4301
OUT
SYM
OUT
OA3
OA2
OA1
VEE
VCC
GND
IN
RMS
-
+
EC+EC-
IN
VCA
-
-
++
VCA SYM
Signal In
Positive Control In
Signal
Out
Figure 13. Driving the VCA via the Positive Control Port
Page 8
value of the input signal current. Some ac component (at twice the input frequency) remains superimposed on the dc output. The ac signal is attenuated by a log-domain filter, which constitutes a single-pole rolloff with cutoff determined by an external capaci
-
tor and a programmable dc current.
As in the VCA, input signals are currents to the
RMS IN pin. This input is a virtual ground, so a re
-
sistor (R
6
in Figure 2) is normally used to convert in
­put voltages to the desired current. The level detector is capable of accurately resolving signals well below 10 mV (with a 10 kW input resistor). However, if the detector is to accurately track such low-level signals, ac coupling is normally required.
The log-domain filter cutoff frequency is usually placed well below the frequency range of interest. For an audio-band detector, a typical value would be 5 Hz, or a 32 ms time constant (t). The filter’s time constant is determined by an external capacitor at
-
tached to the C
T
pin, and an internal current source
(I
CT
) connected to CT. The current source is pro
-
grammed via the I
T
pin: current in ITis mirrored to
I
CT
with a gain of approximately 1.1. The resulting time constant t is approximately equal to 0.026 C
T/IT
. Note that, as a result of the mathematics of RMS de­tection, the attack and release time constants are fixed in their relationship to each other.
The dc output of the detector is scaled with the same constant of proportionality as the VCA gain control: 6.5 mV/dB. The detector’s 0 dB reference (I
in0
, the input current which causes 0 V output), is
determined by I
T
as follows: I
in0
=
9.6 mA I
t
The de­tector output stage is capable of sinking or sourcing 100 mA.
Differences between the 4301’s RMS-Level Detec
-
tor circuitry and that of the THAT 2252 RMS Detec
-
tor are as follows:
1) The rectifier in the 4301 RMS Detector is inter
­nally balanced by design, and cannot be balanced via an external control. The 4301 will typically bal
­ance positive and negative halves of the input signal within ±1.5%, but in extreme cases the mismatch may reach ±15%. However, a 15% mismatch will not significantly increase ripple-induced distortion in dynamics processors over that caused by signal
ripple alone.
2) The time constant of the 4301’s RMS detector is determined by the combination of an external ca
-
pacitor (connected to the C
T
pin) and an internal, programmable current source. The current source is equal to 1.1 I
T
. Normally, a resistor is not con
-
nected directly to the C
T
pin on the 4301.
3) The 0 dB reference point, or level match,isnot adjustable via an external current source. However, as in the 2252, the level match is affected by the timing current, which, in this case, is drawn from the I
T
pin and mirrored internally to CT.
4) The input stage of the 4301 RMS detector uses integrated P-channel FETs rather than a bias-current corrected bipolar differential amplifier. Input bias currents are therefore negligible, improv
-
ing performance at low signal levels.
The Opamps — in Brief
The three opamps in the 4301 are intended for
general purpose applications. All are 5 MHz opamps with slew rates of approximately 2V/ms. All use bipo
­lar PNP input stages. However, the design of each is optimized for its expected use. Therefore, to get the most out of the 4301, it is useful to know the major differences among these opamps.
OA
3
, being internally connected to the output of the VCA, is intended for current-to-voltage conver­sion. Its input noise performance, at
75.
nV
Hz
, com-
plements that of the VCA, adding negligible noise at unity gain. Its output section is capable of driving a 2kW load to within 2V of the power supply rails, making it possible to use this opamp directly as the output stage in single-ended designs.
OA
1
is the quietest opamp of the three. Its input
noise voltage, at
65.
nV
Hz
, makes it the opamp of
choice for input stages. Note that its output drive ca
­pability is limited (in order to reduce the chip’s power dissipation) to approximately ±3 mA. It is comfortable driving loads of 5 kW or more to within 1V of the power supply rails.
OA
2
is intended primarily as a control-voltage
processor. Its input noise parallels that of OA
3
, and
its output drive capability parallels that of OA
1
.
THAT Corporation; 45 Sumner Street; Milford, Massachusetts 01757-1656; USA
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Page 8 Rev. 04/10/02
Page 9
Applications
The circuit of Figure 14, Page 9, shows a typical
application for THAT 4301. This simple compres
­sor/limiter design features adjustable hard-knee threshold, compression ratio, and static gain
1
. The applications discussion in this data sheet will center on this circuit for the purpose of illustrating impor
-
tant design issues. However, it is posslble to config
­ure many other types of dynamics processors with THAT 4301. Hopefully, the following discussion will imply some of these possibilities.
Signal Path
As mentioned in the section on theory, the VCA input pin is a virtual ground with negative feedback provided internally. An input resistor (R
1
, 20kW)is required to convert the ac input voltage to a current within the linear range of the 4301. (Peak VCA input currents should be kept under 1 mA for best distor
-
tion performance.) The coupling capacitor (C
1
,47mf)
is strongly recom
-
mended to block dc cur
­rent from preceeding stages (and from offset voltage at the input of the VCA). Any dc current into the VCA will be modulated by varying gain in the VCA, showing up in the output as “thumps”. Note that C
1
,
in conjunction with R
1
, will set the low fre­quency limit of the cir
-
cuit.
The VCA output is
connected to OA
3
, config
-
ured as an inverting cur
­rent-to-voltage converter. OA
3
‘s feedback compo
­nents (R
2
,20kW, and
C
2
, 47 pf) determine the
constant of cur
­rent-to-voltage conver
­sion. The simplest way to deal with this is to recognize that when the VCA is set for unity (0 dB) gain, the input to output voltage gain is simply R
2/R1
, just as in
the case of a single in
-
verting stage. If, for some reason, more than 0 dB gain is required when the VCA is set to unity, then the resistors may be skewed to provide it. Note that the feedback capacitor (C
2
)isrequired for stability.
The VCA output has approximately 45 pf of capaci
­tance to ground, which must be neutralized via the 47 pf feedback capacitor across R
2
.
The VCA gain is controlled via the E
C–
terminal, whereby gain will be proportional to the negative of the voltage at E
C–
. The EC+terminal is grounded, and the SYM terminal is returned nearly to ground via a small resistor (R
3
,51W). The VCA SYM trim (R5, 50 kW) allows a small voltage to be applied to the SYM terminal via R
4
(300 kW). This voltage adjusts for small mismatches within the VCA gain cell, thereby reducing even-order distortion products. To adjust the trim, apply to the input a middle-level, middle-frequency signal (1 kHz at1Visagood
THAT Corporation; 45 Sumner Street; Milford, Massachusetts 01757-1656; USA
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THAT 4301 Dynamics Processor IC Page 9
EC+
EC-
IN
OUT
SYM
VCA
+
OA3
-
OUT
1%20K0
R2
51
R3
R16
1%4k99
+
OA2
-
GND
C5
100N
1%
590K
R17
1%
10K0
R15
+15
R18
CCW
CW
GAIN
10K
-15
1%
1K43
R14
COMPRESSION
CW
CCW
R13 10K
C3
47uF
R6
-15
10K0 1%
22uF
C6
IN
IT
OUT
CT
RMS
R7
2M00
1%
-15
10uF
C4
VEE
VCC
THAT4301
+15
100n
C7
C8
100n
1%4k99
R8
+
OA1
-
-15
2M00 1%
R10
1%383K
R11
CR1
CR2
10K0 1%
R9
R12
CW
10K
CCW
THRESHOLD
+15
20K0 1%
R1
47uF
C1
300K
R4
-15
+15
R5
50K
VCA SYM
C2
47pF
IN
Figure 14. Typical Compressor/Limiter Application Circuit
1. More information on this compressor design, along with suggestions for converting it to soft-knee operation, is given in AN100, Basic Compressor Limiter Design. The designs in AN100 are based on THAT Corporation’s 2150-Series VCAs and 2252 RMS Detector, but are readily adaptable to the 4301 with only minor modifications. In fact, the circuit presented here is functionally identical to the hard-knee circuit published in AN100.
Page 10
choice with this circuit) and observe THD at the sig
-
nal output. Set the trim for minimum THD.
RMS-Level Detector
The RMS detector’s input is similar to that of the
VCA. An input resistor (R
6
,10kW) converts the ac in
-
put voltage to a current within the linear range of the
4301. (Peak detector input currents should be kept under 1 mA for best linearity.) The coupling capacitor (C
3
,47mf) is recommended to block dc current from
preceeding stages (and from offset voltage at the in
­put of the detector). Any dc current into the detector will limit the low-level resolution of the detector, and will upset the rectifier balance at low levels. Note that, as with the VCA input circuitry, C
3
in conjunc
­tion with R
6
will set the lower frequency limit of the
detector.
The time response of the RMS detector is deter
­mined by the capacitor attached to C
T(C4
,10mf) and
the size of the current in pin I
T
(determined by R7, 2MW and the negative power supply, –15V). Since the voltage at I
T
is approximately 0 V, the circuit of Figure
14 produces 7.5 mAinI
T
. The current in ITis mir
-
rored with a gain of 1.1 to the C
T
pin, where it is
available to discharge the timing capacitor (C
4
). The combination produces a log filter with time constant equal to approximately 0.026 C
T/IT
(~35 ms in the
circuit shown).
The waveform at C
T
will follow the logged (deci­bel) value of the input signal envelope, plus a dc off­set of about 1.3 V (2 V
BE
). This allows a polarized capacitor to be used for the timing capacitor, usually an electrolytic. The capacitor used should be a low-leakage type in order not to add significantly to the timing current.
The output stage of the RMS detector serves to
buffer the voltage at C
T
and remove the 1.3 V dc off
-
set, resulting in an output centered around 0 V for in
­put signals of about 85 mV. The output voltage increases 6.5 mV for every 1 dB increase in input sig
­nal level. This relationship holds over more than a 60 dB range in input currents.
Control Path
A compressor/limiter is intended to reduce its gain as signals rise above a threshold. The output of the RMS detector represents the input signal level over a wide range of levels, but compression only oc
-
curs when the level is above the threshold. OA
1
is configured as a variable threshold detector to block envelope information for low-level signals, passing only information for signals above threshold.
OA
1
is an inverting stage with gain of 2 above
threshold and 0 below threshold. Neglecting the ac
-
tion of the THRESHOLD control (R
12
) and its associ
-
ated resistors (R
11
and R10), positive signals from the
RMS detector output drive the output of OA
1
nega
-
tive. This forward biases CR
2
, closing the feedback
loop such that the junction of R
9
and CR2(the output
of the threshold detector) sits at -(R
9/R8
) RMS
OUT
. For
the circuit of Figure 14, this is –2 RMS
OUT
. Negative signals from the RMS detector drive the output of OA
1
positive, reverse biasing CR2and forward biasing
CR
1
. In this case, the junction of R9and CR2rests at 0 V, and no signal level informaion is passed to the threshold detector’s output.
In order to vary the threshold, R
12
, the THRESH
-
OLD control, is provided. Via R
11
(383 kW), R12adds
up to ±39.2 mA of current to OA
1
‘s summing junction,
requiring the same amount of opposite-polarity cur
­rent from the RMS detector output to counterbalance it. At 4.99 kW, the voltage across R
8
required to pro
­duce a counterbalancing current is ± 195 mV, which represents a ±30 dB change in RMS detector input level.
Since the RMS detector’s 0 dB reference level is 85 mV, the center of the THRESHOLD pot’s range would be 85 mV, were it not for R
10
(2 MW), which
provides an offset. R
10
adds an extra –7.5 matoOA1‘s summing junction, which would be counterbalanced by 37.4 mV at the detector output. This corresponds to 5.8 dB, offsetting the THRESHOLD center by this much to 165 mV, or approximately -16 dBV.
The output of the threshold detector represents the signal level above the determined threshold, at a constant of about 13 mV/dB (from [R
9/R8
] 6.5 mV/dB). This signal is passed on to the
COMPRESSION control (R
13
), which variably attenu-
ates the signal passed on to OA
2
. Note that the gain of
OA
2
, from the wiper of the COMPRESSION control to
OA
2
‘s output, is R16/R15(0.5), precisely the inverse of
the gain of OA
1
. Therefore, the COMPRESSION con
-
trol lets the user vary the above-threshold gain be
-
tween the RMS detector output and the output of OA
1
from zero to a maximum of unity.
The gain control constant of the VCA, 6.5 mV/dB, is exactly equal to the output scaling constant of the RMS detector. Therefore, at maximum COMPRES
­SION, above threshold, every dB increase in input signal level causes a 6.5 mV increase in the output of OA
2
, which in turn causesa1dBdecrease in the VCA gain. With this setting, the output will not increase despite large increases in input level above threshold. This is infinite compression. For intermediate set
-
tings of COMPRESSION,a1dBincrease in input sig
­nal level will cause less thana1dBdecrease in gain, thereby varying the compression ratio.
The resistor R
14
is included to alter the taper of the COMPRESSION pot to better suit common use. If a linear taper pot is used for R
13
, the compression ra
­tio will be 1:2 at the middle of the rotation. However, 1:2 compression in an above-threshold compressor is not very strong processing, so 1:4 is often pre
­ferred at the midpoint. R
14
warps the taper of R13so that 1:4 compression occurs at approximately the midpoint of R
13
‘s rotation.
THAT Corporation; 45 Sumner Street; Milford, Massachusetts 01757-1656; USA
Tel: +1 (508) 478-9200; Fax: +1 (508) 478-0990; Web: www.thatcorp.com
Page 10 Rev. 04/10/02
Page 11
The GAIN control (R18) is used to provide static gain or attenuation in the signal path. This control adds up to ±130 mV offset to the output of OA
2
(from
-V
+
R
R
16
17
to -V
-
R
R
16
17
), which is approximately
±20 dB change in gain of the VCA. C
5
is used to atten
-
uate the noise of OA
2
,OA1and the resistors R
8
through R16used in the control path. All these active and passive components produce noise which is passed on to the control port of the VCA, causing modulation of the signal. By itself, the 4301 VCA pro
-
duces very little noise modulation, and its perfor
­mance can be significantly degraded by the use of noisy components in the control voltage path.
Overall Result
The resulting compressor circuit provides hard-knee compression above threshold with three essential user-adjustable controls. The threshold of compression may be varied over a ±30 dB range from about –46 dBV to +14 dBV. The compression ratio
may be varied from 1:1 (no compression) to ¥:1. And, static gain may be added up to ±20 dB. Audio performance is excellent, with THD running below
0.05% at middle frequencies even with 10 dB of com
­pression, and an input dynamic range of over 115 dB.
Perhaps most important, this example design
only scratches the surface of the large body of appli
­cations circuits which may be constructed with THAT
4301. The combination of an accurate, wide-dynamic-range, log-responding level detector with a high-quality, exponentially-responding VCA produces a versatile and powerful analog engine. The opamps provided in the 4301 enable the designer to configure these building blocks with few external components to construct gates, expanders, de-essers, noise reduction systems and the like.
For further information, samples and pricing,
please contact us at the address below.
THAT Corporation; 45 Sumner Street; Milford, Massachusetts 01757-1656; USA
Tel: +1 (508) 478-9200; Fax: +1 (508) 478-0990; Web: www.thatcorp.com
THAT 4301 Dynamics Processor IC Page 11
Page 12
Notes
THAT Corporation; 45 Sumner Street; Milford, Massachusetts 01757-1656; USA
Tel: +1 (508) 478-9200; Fax: +1 (508) 478-0990; Web: www.thatcorp.com
Page 12 Rev. 04/10/02
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