Page 1
TH7120
300 to 930MHz
FSK/FM/ASK Transceiver
3901007120 Page 1 of 28 Data Sheet
Rev. 005 Jan. 2002
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Features
! Single chip solution with only a few external components
! Stand-alone fixed-frequency transceiver operation modes
! Programmable multi-channel transceiver operation modes
! Low current consumption in active mode and very low standby current
! PLL-stabilized RF VCO (LO) with internal varactor diode
! Lock detection in programmable channel applications
! 3wire bus serial control interface
! FSK/ASK modulation selection
! FSK for digital data and FM for analog signal reception
! RSSI allows signal strength indication and ASK detection
! Switchable LNA gain for improved dynamic range
! Automatic PA turn-on after PLL lock
! FM possible with external varactor
! ASK modulation achieved by on/off keying
! AFC option for extended input frequency acceptance range
! Surface mount package LQFP32
Ordering Information
Part No. (Engineering Samples) Temperature Code Package Code
TH7120 (TH7120-03) E (-40 °C to 85 °C) NE (LQFP32)
Application Examples
! General bi-directional half duplex digital data transmission or analog signal transmission
! Low-power telemetry
! Alarm and security systems
! Keyless car and central locking
! Domotics
! Model control
Technical Data Overview
! Frequency range: 300 MHz to 930 MHz for programmable channel applications
! 315 MHz, 433 MHz, 868 MHz or 915 MHz fixed-frequency single-channel variants
! Power supply range: 2.5 V to 5.5 V
! Temperature range: -40 °C to +85 °C
! Standby current: 50 nA
! Operating current: 6.0 mA in receive mode at low gain
! Operating current 9.0 mA in transmit mode at 0 dBm output power
! Adjustable output power range from –15 dBm to +6 dBm
! Sensitivity: -103 dBm at FSK with 150 kHz IF filter BW
! Sensitivity: -105 dBm at ASK with 150 kHz IF filter BW
! Maximum data rate for FSK and ASK: 60 kbit/s NRZ
! Maximum input level: –10 dBm at FSK and -20 dBm at ASK
! Input frequency acceptance: ± 50 kHz (with AFC option)
! Frequency deviation range: ±5 kHz to ±100 kHz
! Maximum analog modulation frequency: 20 kHz
! 3 MHz to 12 MHz crystal reference
Page 2
TH7120
300 to 930MHz
FSK/FM/ASK Transceiver
3901007120 Page 2 of 28 Data Sheet
Rev. 005 Jan. 2002
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General Description
The TH7120 is a single chip FSK/FM/ASK transceiver IC. It is designed to operate in low-power multi-channel
programmable or single-channel s tand-alone, half -duplex data tr ansm ission s ystems. It c an be used for ISM,
SRD or any other application operating in the frequency ranging of 300 MHz to 930 MHz.
The TH7120 transceiver IC consists of the following building blocks:
" Low-noise amplifier (LNA) for high-sensitivity RF signal reception with switchable gain
" Mixer (MIX) for RF-to-IF down-conversion
" IF amplifier (IFA) to amplify and limit the IF signal and for RSSI generation
" Phase-coincidence demodulator with external ceramic discriminator (FSK Demodulator)
" Operational amplifier, connected to demodulator output (OA1)
" Operational amplifier, integrator circuit at FSK-AFC mode (OA2)
" Control logic with 3wire bus serial control interface (SCI)
" Reference oscillator (RO) with external crystal
" Reference divider (R counter)
" Programmable divider (N/A counter)
" Phase-frequency detector (PFD)
" Charge pump (CP)
" Voltage control oscillator (VCO) with internal varactor
" Power amplifier (PA) with adjustable output power
The transceiver can be used either as a 3wire-bus-controlled programmable or as a stand-alone fixedfrequency device. After power up, the transceiver is set to fixed-frequency mode. In this mode, pins
FS0/SDEN and FS1/LD must be connected to V
EE
or VCC in order to set the desired frequency of operation.
The logic levels at pins FS0/SDEN and FS1/LD m ust not be changed after power up in order to remain in
fixed-frequency mode.
Channel frequency 433.92 MHz 868.3 MHz 315.0 MHz 915.0 MHz
FS0/SDEN
1010
FS1/LD
0011
After the first logic level change at pin FS0/SDEN, the transceiver enters into program mable m ode while pin
FS1/LD is now a PLL lock detector output. In this mode, the user can set any PLL frequency or mode of operation by the SCI.
In the fixed-frequency mode, the user c an set the transceiver to Standby, Receive, Tr ansmit or Idle (only PLL
synthesizer active) mode via control pins RE/SCLK and TE/SDTA.
Operation mode Standby Receive Transmit Idle
RE/SCLK
0101
TE/SDTA
0011
Page 3
TH7120
300 to 930MHz
FSK/FM/ASK Transceiver
3901007120 Page 3 of 28 Data Sheet
Rev. 005 Jan. 2002
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Block Diagram
Figure 1: TH7120 block diagram
IN_LNA
LNA
GAIN_LNA
OUT_LNA
IN_MIX
OUT_DTA
OA2
bias
IF
MIX
OUT_MIX1
IN_IFA
VEE_IF
IFA
IN_DEM
26
29
28
30 32 31 1
VCC_IF
2
3
OUT_DEM
6
OA1
8
INT1
5
INT2
4
RSSI
7
1.5pF
200k
VEE_LNA
27
MIX
DemodulatorFSK
VEE_PLL
OUT_PA
FSK
ASK
LO
IN_DTA
ASK/FSK
RE/SCLK
TE/SDTA
FS0/SDEN
25
VCC_PLL
20
PS_PA
24
FSK_SW
FS1/LD
VEE_RO
11 19 9 1716151312
RO
RO
R
counter
N
counter
RO
10
LF
21
SCLK
SDTA
SDEN
Control Logic
SCI
TNK_LO
23
VCO
22
PA
18
VEE_DIG
14
VCC_DIG
Page 4
TH7120
300 to 930MHz
FSK/FM/ASK Transceiver
3901007120 Page 4 of 28 Data Sheet
Rev. 005 Jan. 2002
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Pin Definition and Descripti on
Pin No. Name I/O Type Functional Schematic Description
1 IN_IFA input
3.1k3.1k
IN_IFA
1
VCC
140µA
VEE
2.2k
IF amplifier input, approx.
2
kΩ single-ended
2 VCC_IF supply positive supply of LNA, MIX,
IFA, FSK Demodulator, PA,
OA1 and OA2
3 IN_DEM analog I/O
VCC
100µA
10µA
VEE
IN_DEM
3
77k
1.5p
IF amplifier output and demodulator input, connection
to external ceramic discriminator
4 INT2 output integrator output OA2
8 OUT_DTA output
VCC
VEE
INT2
4
8
OUT_DTA
output OA1
5 INT1 input inverting inputs OA1 and
OA2
6 OUT_DEM analog I/O
OA2
bias
VEE
VCC
INT1
5
VEE
OUT_DEM
6
VCC
120
120
VEE
VCC
120
10.5p
10.5p
520k 520k
1k
OA1
+
200k
demodulator output and noninverting input OA1
7 RSSI output
VCC
VEE
RSSI
7
120
VEE
VCC
5µA
5µA
RSSI output
Page 5
TH7120
300 to 930MHz
FSK/FM/ASK Transceiver
3901007120 Page 5 of 28 Data Sheet
Rev. 005 Jan. 2002
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Pin No. Name I/O Type Functional Schematic Description
9 VEE_RO ground ground of RO
10 RO analog I/O
40p
VEE
VCC
RO
10
2.6µA
39k
40p
RO input, base of bipolar
transistor
11 FSK_SW analog I/O
VCC
VEE
FSK_SW
11
FSK pulling pin, switch to
ground or OPEN
12 IN_DTA input ASK/FSK modulation data
input, pull down resistor
120kΩ
15 RE/SCLK input receiver enable input / clock
input for the shift register,
pull down resistor 120kΩ
16 TE/SDTA input
VEE
VCC
IN_DTA
12
RE/SCLK
15
16
TE/SDTA
120k
120
transmitter enable input /
serial data input, pull down
resistor 120kΩ
13 ASK/FSK input ASK/FSK mode select input
17 FS0/SDEN input
VEE
VCC
ASK/FSK
13
17
FS0/SDEN
120
frequency select input / serial data enable input
14 VCC_DIG supply positive supply of serial port
and control logic
18 VEE_DIG ground ground of serial port and
control logic
19 FS1/LD input
VEE
VCC
FS1/LD
19
120
frequency select input / lock
detector output
20 VCC_PLL supply positive supply of PLL fre-
quency synthesizer
22 VEE_PLL ground ground of PLL frequency
synthesizer
Page 6
TH7120
300 to 930MHz
FSK/FM/ASK Transceiver
3901007120 Page 6 of 28 Data Sheet
Rev. 005 Jan. 2002
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Pin No. Name I/O Type Functional Schematic Description
21 LF analog I/O charge pump output, con-
nection to external loop filter
23 TNK_LO analog I/O
120
10k
6.3p
VCC
VCC
VCC
VEE
33 33
VEE
LF
21
TNK_LO
23
VCO open-collector output,
connection to external LC
tank
24 PS_PA analog I/O
VEE VEE
VCC VCC
120
PS_PA
24
power-setting input
25 OUT_PA output
VEE VEE
VCC
OUT_PA
25
power amplifier opencollector output
27 VEE_LNA ground ground of LNA and PA
28 OUT_LNA output LNA open-collector output,
connection to external LC
tank at RF
26 IN_LNA input
40p
VEE
VEE
3.8k
OUT_LNA
28
bias
37
IN_LNA
26
LNA input,
approx. 50Ω single-ended
29 GAIN_LNA input
VCC
VEE
GAIN_LNA
29
120
LNA gain control input
Page 7
TH7120
300 to 930MHz
FSK/FM/ASK Transceiver
3901007120 Page 7 of 28 Data Sheet
Rev. 005 Jan. 2002
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Pin No. Name I/O Type Functional Schematic Description
30 IN_MIX input
VCC
210
bias
LO
IN_MIX
30
VEE VEE
mixer input, approx. 200Ω
single-ended
31 VEE_IF ground ground of IFA, Demodulator,
OA1 and OA2
32 OUT_MIX output
VCC
VEE
OUT_MIX
32
100
mixer output, approx. 330Ω
single-ended
Page 8
TH7120
300 to 930MHz
FSK/FM/ASK Transceiver
3901007120 Page 8 of 28 Data Sheet
Rev. 005 Jan. 2002
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Stand-Alone Fixed-Frequency Operation
After power up the transceiver is set to fixed-frequency mode. In this mode, pins FS0/SDEN and FS1/LD
must be connected to V
EE
or VCC to set the desired frequency of operation. The logic levels at pins FS0/SDEN
and FS1/LD must not be changed after power up in or der to remain in fixed-f requency mode. The default
settings of the control word bits in stand-alone mode are described in the frequency selection table.
Frequency Selection
Channel frequency 433.92 MHz 868.3 MHz 315 MHz 915 MHz
FS0/SDEN
1010
FS1/LD
0011
Reference oscillator frequency
7.1505 MHz
R counter ratio in RX mode
16 16 18 30
PFD frequency in RX mode
446.91 kHz 446.91 kHz 397.25 kHz 238.35 kHz
N/A counter ratio in RX mode
947 1919 766 3794
VCO frequency in RX mode
423.22 MHz 857.60 MHz 304.30 MHz 904.30 MHz
RX frequency
433.92 MHz 868.30 MHz 315.00 MHz 915.00 MHz
R counter ratio in TX mode
16 16 18 30
PFD frequency in TX mode
446.91 kHz 446.91 kHz 397.25 kHz 238.35 kHz
N/A counter ratio in TX mode
971 1943 793 3839
VCO frequency in TX mode
433.92 MHz 868.30 MHz 315.00 MHz 915.00 MHz
TX frequency
433.92 MHz 868.30 MHz 315.00 MHz 915.00 MHz
IF frequency in RX mode
10.7 MHz 10.7 MHz 10.7 MHz 10.7 MHz
Page 9
TH7120
300 to 930MHz
FSK/FM/ASK Transceiver
3901007120 Page 9 of 28 Data Sheet
Rev. 005 Jan. 2002
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Default Register Settings After Power-up
Bits
A-word
symbols
Channel
‘00’
868.3
MHz
Channel
‘01’
433.92
MHz
Channel
‘10’
915.0
MHz
Channel
‘11’
315.0
MHz
B-word
symbols
Channel
‘00’
868.3
MHz
Channel
‘01’
433.92
MHz
Channel
‘10’
915.0
MHz
Channel
‘11’
315.0
MHz
21 not used 0 not used 0
20 DI_MODE 0 not used 0
19 MODUL 0 EnDelPLL 1
18 HighCur 0 LNAHYST 1
17
LOCK_MODE
0 EnAdj 0
16 PA_AUTO 0 EnFM 0
15 Pow1 1 Max2 1
14 Pow0 1 Max1 1
13 MIXG 1 Max0 1
12 LNAG 1 Min2 0
11 TE 0 Min1 1
10 RE 0 Min0 1
9 RR9 0 0 0 0 RT9 0 0 0 0
8 RR8 0 0 0 0 RT8 0 0 0 0
7 RR7 0 0 0 0 RT7 0 0 0 0
6 RR6 0 0 0 0 RT6 0 0 0 0
5 RR5 0 0 0 0 RT5 0 0 0 0
4 RR4 1 1 1 1 RT4 1 1 1 1
3 RR3 0 0 1 0 RT3 0 0 1 0
2 RR2 0 0 1 0 RT2 0 0 1 0
1 RR1 0 0 1 1 RT1 0 0 1 1
0 RR0 0 0 0 0 RT0 0 0 0 0
Bits
C-word
symbols
Channel
‘00’
868.3
MHz
Channel
‘01’
433.92
MHz
Channel
‘10’
915.0
MHz
Channel
‘11’
315.0
MHz
B-word
symbols
Channel
‘00’
868.3
MHz
Channel
‘01’
433.92
MHz
Channel
‘10’
915.0
MHz
Channel
‘11’
315.0
MHz
21 LNAGI_E 0
MODUL_CTR
0
20 POLAR 0 LD_TM1 1
19 High2 0 0 0 0 LD_TM0 0
18 High1 1 1 1 1 ER_TM1 0
17 UP 1 0 1 0 ER_TM0 0
16 NR16 0 0 0 0 NT16 0 0 0 0
15 NR15 0 0 0 0 NT15 0 0 0 0
14 NR14 0 0 0 0 NT14 0 0 0 0
13 NR13 0 0 0 0 NT13 0 0 0 0
12 NR12 0 0 0 0 NT12 0 0 0 0
11 NR11 0 0 1 0 NT11 0 0 1 0
10 NR10 1 0 1 0 NT10 1 0 1 0
9 NR9 1 1 1 1 NT9 1 1 1 1
8 NR8 1 1 0 0 NT8 1 1 0 1
7 NR7 0 1 1 1 NT7 1 1 1 0
6 NR6 1 0 1 1 NT6 0 1 1 0
5 NR5 1 1 0 1 NT5 0 0 1 0
4 NR4 1 1 1 1 NT4 1 0 1 1
3 NR3 1 0 0 1 NT3 0 1 1 1
2 NR2 1 0 0 1 NT2 1 0 1 0
1 NR1 1 1 1 1 NT1 1 1 1 0
0 NR0 1 1 0 0 NT0 1 1 1 1
Page 10
TH7120
300 to 930MHz
FSK/FM/ASK Transceiver
3901007120 Page 10 of 28 Data Sheet
Rev. 005 Jan. 2002
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Programmable Channel Operation
Serial Control Interface Description
A 3-wire (SCLK, SDTA, SDEN) Serial Control Interface (SCI) is used to program the transceiver in multichannel mode (see Fig. 2). At each rising edge of the SCLK signal, the logic value on the SDTA pin is written
into a 24-bit shift register. T he data st ored in the s hif t r egist er ar e loaded into one of the 4 appropr iate latc hes
on the rising edge of SDEN. The control words are 24 bits lengths: 2 addr ess bits and 22 data bits. T he first
two bits (bit 23 and 22) are latch address bits. As additional leading bits are ignored, only the least signific ant
24 bits are serial-clock ed into the shift register. The first incom ing bit is the most significant bit (MSB). To
program the transceiver in multi-c hannel application, four 24- bit words may be sent: A-word, B-word, C-word
and D-word. If individual bits within a word have to be changed, then it is sufficient to program only the appropriate 24-bit word. The serial data input timing and the structure of the control words are illustrated in Fig. 2
and 3. Table REGISTER SETTINGS describes the function of each bit.
Figure 2: SCI block diagram
Due to the static CMOS design, the SCI consumes virtually no current and it can be programmed in active as
well as in standby mode.
Figure 3: Serial data input timing
t
EH
t
EW
t
ES
t
CWH
t
CWL
t
CH
t
CS
bit 22 bit 1 bit 0bit 23
data
Invalid
LSBMSB
SDTA
SCLK
SDEN
data
Invalid
A - LATCH
ADDR DECODER
B - LATCH
C - LATCH
D - LATCH
22
A-word
2222
‘’
00
‘’
10
‘’
11
‘’
01
2
22
22
22
22
B-word
22
D-word
22
C-word
24-BIT
SHIFT REGISTER
SDEN
SDTA
SCLK
Page 11
TH7120
300 to 930MHz
FSK/FM/ASK Transceiver
3901007120 Page 11 of 28 Data Sheet
Rev. 005 Jan. 2002
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SCI Words
A-word
MSB
LS
B
23222120191817161514131211109876543210
00
XXXXXXXXXXXXXXXXXXXXXX
ADDR
not used
DI_MODE
MODUL
HighCur
LOCK_MODE
PA_AUTO
Pow1
Pow0
MIXG
LNAG
TE
RE
RR9
RR8
RR7
RR6
RR5
RR4
RR3
RR2
RR1
RR0
B-word
MSB
LS
B
23222120191817161514131211109876543210
01
XXXXXXXXXXXXXXXXXXXXXX
ADDR
not used
not used
EnDelPLL
LNAHYST
EnAdj
EnFm
Max2
Max1
Max0
Min2
Min1
Min0
RT9
RT8
RT7
RT6
RT5
RT4
RT3
RT2
RT1
RT0
C-word
MSB
LS
B
23222120191817161514131211109876543210
10
XXXXXXXXXXXXXXXXXXXXXX
ADDR
LNAGI_E
POLAR
High2
High1
UP
NR16
NR15
NR14
NR13
NR12
NR11
NR10
NR9
NR8
NR7
NR6
NR5
NR4
NR3
NR2
NR1
NR0
D-word
MSB
LS
B
23222120191817161514131211109876543210
11
XXXXXXXXXXXXXXXXXXXXXX
ADDR
MODUL_CTR
LD_TM1
LD_TM0
ER_TM1
ER_TM0
NT16
NT15
NT14
NT13
NT12
NT11
NT10
NT9
NT8
NT7
NT6
NT5
NT4
NT3
NT2
NT1
NT0
Page 12
TH7120
300 to 930MHz
FSK/FM/ASK Transceiver
3901007120 Page 12 of 28 Data Sheet
Rev. 005 Jan. 2002
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Register Settings
A-word
Symbol Bits No.
Description
Software button
RR9:RR0
RR9:RR0
[9:0] 10
Reference divider ratio in RX mode
TE:RE [11:10] 2 Select active mode at programmable-channel application:
OPMODE
‘00’
‘11’
‘10’
‘01’
Standby mode
Idle mode
Transmit mode
Receive mode
LNAG [12] 1 Select LNA gain at internal gain control:
LNAGAIN
‘0’
‘1’
low LNA gain
high LNA gain
MIXG [13] 1 Select mixer conversion gain at programmable-channel application:
MIXGAIN
‘0’
‘1’
low gain
high gain
Pow1:Pow0 [15:14] 2 Select output power at programmable-channel application:
TXPOWER
‘00’
‘01’
‘10’
‘11’
P
max
- 20 dBm
P
max
- 12 dBm
P
max
- 6 dBm
P
max
PA_AUTO [16] 1 Disable automatic PA turn-on after PLL lock:
PA_A UTO
‘0’
‘1’
enabled
disabled
LOCK_MODE [17] 1 Select PFD output analyse mode of lock detecting:
LOCK_MODE
‘0’
‘1’
before lock only
before and after lock.
HighCur [18] 1 Select Charge Pump output current:
CPCUR
‘0’
‘1’
±±±± 260 µA
±±±±1300 µA
MODUL [19] 1 Select modulation mode at internal modulation control:
ASK/FSK
‘0’
‘1’
ASK
FSK
DI_MODE [20] 1 Select mode for input data:
‘0’ normal
DI_MODE
‘0’ for space at ASK or f
min
at FSK, ‘1’ for mark at ASK or f
max
at FSK
‘1’ inverse
‘1’ for space at ASK or f
min
at FSK, ‘0’ for mark at ASK or f
max
at FSK
not used [21] 1 ‘X’
Page 13
TH7120
300 to 930MHz
FSK/FM/ASK Transceiver
3901007120 Page 13 of 28 Data Sheet
Rev. 005 Jan. 2002
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B-word
Symbol Bits No. Description
Software button
RT9:RT0
RT9:RT0
[9:0] 10
Reference divider ratio in TX mode
Min2:Min0 [12:10] 3 Select minimum value of RO active current:
ROMIN
‘000’
‘001’
‘010’
‘011’
‘100’
‘101’
‘110’
‘111’
0 µA
50 µA
100 µA
150 µA
200 µA
250 µA
300 µA
350 µA
Max2:Max0 [15:13] 3 Select maximum value of RO active current:
ROMAX
‘000’
‘001’
‘010’
‘011’
‘100’
‘101’
‘110’
‘111’
0 µA (RO is off)
50 µA
100 µA
150 µA
200 µA
250 µA
300 µA
350 µA
EnFm [16] 1 Test bit. Forced '0' for correct functioning.
EnAdj [17] 1 Test bit. Forced '0' for correct functioning.
LNAHYST [18] 1 Enable LNA hysteresis:
LNAHYST
‘1’
‘0’
disabled
enabled
EnDelPLL [19] 1 Enable delayed start of the PLL:
EnDelPLL
‘1’
‘0’
disabled
enabled.
not used [20] 1 ‘X’
not used [21] 1 ‘X’
Page 14
TH7120
300 to 930MHz
FSK/FM/ASK Transceiver
3901007120 Page 14 of 28 Data Sheet
Rev. 005 Jan. 2002
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C-word
Symbol Bits No. Description
Software button
NR16:NR0
NR16:NR0
[16:0] 17
Feedback divider ratio in RX mode
UP [17] 1 Select frequency band:
BAND
‘1’
‘0’
up to 500 MHz
500 to 1000MHz
High2:High1 [19:18] 2 Select VCO active current:
VCOCUR
‘00’
‘01’
‘10’
‘11’
low current (250 µA)
standard current (350 µA)
high1 current (450 µA)
high2 current (550 µA)
POLAR [20] 1 Select Phase Detector polarity:
PFDPOL
‘1’
‘0’
positive (1)
negative (2)
(2)
(1)
FREQUENCY
OUTPUT
VCO
VCO INPUT VOLTAGE
LNAGI_E [21] 1 Select LNA gain control mode:
LNACTRL
‘0’
‘1’
external LNA gain control
internal LNA gain control
Page 15
TH7120
300 to 930MHz
FSK/FM/ASK Transceiver
3901007120 Page 15 of 28 Data Sheet
Rev. 005 Jan. 2002
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D-word
Symbol Bits No. Description
Software button
NT16:NT0
NT16:NT0
[16:0] 17
Feedback divider ratio in TX mode
ER_TM1:ER_TM0 [18:17] 2
Select maximum enabled PFD output error for lock detecting
(in reference frequency clocks):
ER_TM1:ER_TM0
‘00’
‘01’
‘10’
‘11’
2 clocks
4 clocks
8 clocks
16 clocks
LD_TM1:LD_TM0 [20:19] 2
Select minimum number of PFD reference frequency clocks
before lock detecting:
LD_TM1:LD_TM0
‘00’
‘01’
‘10’
‘11’
4 clocks
16 clocks
64 clocks
256 clocks
MODUL_CTR [21] 1
Select mode of modulation control:
MODCTRL
‘0’
‘1’
external modulation control
internal modulation control
Page 16
TH7120
300 to 930MHz
FSK/FM/ASK Transceiver
3901007120 Page 16 of 28 Data Sheet
Rev. 005 Jan. 2002
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Technical Data
Absolute Maximum Ratings
Parameter Symbol Condition / Note Min Max Unit
Supply voltage V
cc
0 7.0 V
Input voltage V
IN
- 0.3 Vcc+0.3 V
Input current I
IN
-1 1 mA
Input RF level P
imax
no damage 10 dBm
Storage temperature T
STG
-40 +125 °C
Electrostatic discharge V
ESD1
human body model, 1) -1.0 +1.0 kV
Electrostatic discharge V
ESD2
human body model, 2) TBD TBD kV
1) pins IN_DTA, ASK/FSK, RE/SCLK; TE/SDTA, FS0/SDEN, FS1/LD
2) all pins, exept IN_DTA, ASK/FSK, RE/SCLK; TE/SDTA, FS0/SDEN, FS1/LD
Normal Operating Conditions
Parameter Symbol Condition Min Max Unit
Supply voltage V
cc
2.5 5.5 V
Operating temperature T
a
-40 +85 ºC
Carrier frequency f
c
300 930 MHz
VCO frequency f
VCO
300 930 MHz
RO frequency f
RO
312MHz
Frequency deviation
∆f
at FM or FSK
±5 ±120
kHz
FSK data rate R
FSK
NRZ 60 kbit/s
FM bandwidth f
m
20 kHz
ASK data rate R
ASK
NRZ 60 kbit/s
DC Characteristics
all parameters under normal operating conditions, unless otherwise stated;
typical values at T
a
= 23 °C and Vcc = 3 V
Parameter Symbol Condition Min Typ Max Unit
Standby current I
SBY
TE/SDTA=0,
RE/SCLK=0
50 100 nA
Idle current I
IDLE
TE/SDTA=1,
RE/SCLK=1
@ f
i
= 433.92 MHz
2.5 3.2 mA
Total supply current in
receive mode at low gain
I
RX_low
TE/SDTA=0,
RE/SCLK=1
V
GAIN_LNA
> 1.4 V
@ f
i
= 433.92 MHz
6.0 8.0 mA
Total supply current in
receive mode at high gain
I
RX_high
TE/SDTA=0,
RE/SCLK=1
V
GAIN_LNA
< 0.8 V
@ f
i
= 433.92 MHz
7.0 9.0 mA
Total supply current in
transmit mode at 0 dBm power
I
TX_0
TE/SDTA=1,
RE/SCLK=0
ASK/FSK=1
@ f
i
= 433.92 MHz,
@ P
o
= 0 dBm
9.0 11.5 mA
Page 17
TH7120
300 to 930MHz
FSK/FM/ASK Transceiver
3901007120 Page 17 of 28 Data Sheet
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AC System Characteristics of the Receiver Part
all parameters under normal operating conditions, unless otherwise stated; all parameters based on test
circuits for FSK (Fig. 4 to 5), FM and ASK (Fig. 6 to 7), respectively; RF at 433.92 MHz
Parameter Symbol Condition Min Typ Max Unit
Input sensitivity – FSK P
min_FSK
BIF = 150kHz
∆f = ± 50 kHz (FSK/FM)
BER ≤ 3⋅10
-3
-103 dBm
Input sensitivity – ASK P
min_ASK
BIF = 150kHz
BER ≤ 3⋅10
-3
-105 dBm
Maximum input signal – FSK/FM
at low gain
P
max_FSK_1
BER ≤ 3⋅10
-3
V
GAIN_LNA
> 1.4 V
10 dBm
Maximum input signal – FSK/FM
at high gain
P
max_FSK_0
BER ≤ 3⋅10
-3
V
GAIN_LNA
< 0.8 V
-10 dBm
Maximum input signal – ASK
at low gain
P
max_ASK_1
BER ≤ 3⋅10
-3
V
GAIN_LNA
> 1.4 V
-20 dBm
Maximum input signal – ASK
at high gain
P
max_ASK_0
BER ≤ 3⋅10
-3
V
GAIN_LNA
< 0.8 V
0dBm
Image rejection
∆P
imag
TBD dB
Blocking immunity
∆P
block
∆f
block
> ±2MHz, note 1
TBD dB
Start-up time – FSK/FM T
FSK
TE/SDTA=0,
RE/SCLK=1
valid data at output
1ms
Start-up time – ASK T
ASK
depends on ASK detector time constant and
start-up mode, valid
data at output
T
FSK
+
200K * C6
ms
Spurious emission P
spur
-70 dBm
Notes: 1. desired signal with FSK/FM or ASK modulation, CW blocking signal
AC System Characteristics of the Transmitter Part
all parameters under normal operating conditions, unless otherwise stated;
typical values at T
a
= 23 °C and Vcc = 3 V;
TE/SDTA=1, RE/SCLK=0, ASK/FSK=1, RPS≥15 kΩ, f
c
= 433.92 MHz, test circuit shown in Fig. 4 to 7
Parameter Symbol Condition Min Typ Max Unit
Output power P
o
CW mode 4 6 8 dBm
FSK deviation
∆f
FSK
depends on Cx1, Cx2 and
crystal parameter
±5 ±50 ±100
kHz
Data rate FSK R
FSK
60 kbit/s
FM deviation
∆f
FM
adjustable with varactor
and V
FM
±6
kHz
Modulation frequency FM f
mod
5kHz
Data rate ASK R
ASK
60 kbit/s
PLL spurs emission P
spur
at all fc and nominal P
o
-36 dBm
Harmonic emission P
harm
at all fc and power steps - -36 dBm
VCO gain K
VCO
35 MHz/V
Charge pump current I
CP
260 µA
Start-up time T
TX
from ”standby” to
“transmit” mode
1ms
Page 18
TH7120
300 to 930MHz
FSK/FM/ASK Transceiver
3901007120 Page 18 of 28 Data Sheet
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Output Power Selection
typical values at T
a
= 23 °C and Vcc = 3 V:
TE/SDTA = 1, RE/SCLK = 0, ASK/FSK = 1, f
c
= 433.92 MHz, CW mode
RPS / kΩΩΩΩ
≥≥≥≥ 15 k
6.8 k 3.3 k 1.0 k
ICC / mA TBD 9.0 TBD TBD
PO / dBm 6 0 -6 -15
P
harm
/ dBm
≤-36 ≤-36 ≤-36 ≤-36
Serial Control Interface
Parameter Symbol Condition Min Max Unit
Data to clock set up time f
CS
150 ns
Data to clock hold time t
CH
50 ns
Clock pulse width high t
CWH
100 ns
Clock pulse width low t
CWL
100 ns
Clock to load enable set
up time
t
ES
100
Crystal Parameters
Parameter Symbol Condition Min Max Unit
Crystal frequency f
crystal
fundamental mode, AT 3 12 MHz
Load capacitance C
load
10 15 pF
Static capacitance C
0
7pF
Motional resistance R
m
70
Ω
Page 19
TH7120
300 to 930MHz
FSK/FM/ASK Transceiver
3901007120 Page 19 of 28 Data Sheet
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Application Circuit Examples
Programmable Channel FSK Application Circuit
Figure 4: Test circuit for programmable channel FSK operation
SCLK
SDTA
SDEN
Lock
detect
FSK
output
FSK
input
CX1
CX2
CERFIL
XTAL
RPS
RB
CTX0
C1
C2
L1
LTX0
CRX0
L0
RSSI
OUT_MIX
VEE
CERRES
C3
CB5
C5
C4
C0
CB0
CB1
CB2
CB3
CB6
CB7
RE/SCLK
IN_DTA
ASK/FSK
FSK_SW
RO
VCC
VEE
VCC
FS1/LD
VEE
LF
TNK_LO
OUT_PA
IN_LNA
OUT_LNA
VEE
GAIN_LNA
IN_MIX
VEE
IN_IFA
IN_DEM
INT2
INT1
RSSI
OUT_DEM
OUT_DTA
VCC
VCC
VCC
VCC
VCC
FS0/SDEN
CB4
RF input
RF output
Antenna
matching
network
CP0
RP
CF1
CF2
RF
Page 20
TH7120
300 to 930MHz
FSK/FM/ASK Transceiver
3901007120 Page 20 of 28 Data Sheet
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Fixed-Frequency FSK Application Circuit
Figure 5: Test circuit for fixed-frequency FSK operation at 433 MHz
FSK
output
FSK
input
TX
enable
RX
enable
CX1
CX2
XTAL
RPS
RB
CTX0
C1
C2
L1
LTX0
CRX0
L0
CERFIL
RSSI
OUT_MIX
VEE
CB5
C5
C4
C0
CF1
CF2
RF
CB4
CB0
CB1
CB2
CB3
CB6
CB7
C3
RF input
RF output
Antenna
matching
network
CERRES
CP0
RP
RE/SCLK
IN_DTA
ASK/FSK
FSK_SW
RO
VCC
VEE
VCC
FS1/LD
VEE
LF
TNK_LO
OUT_PA
IN_LNA
OUT_LNA
VEE
GAIN_LNA
IN_MIX
VEE
IN_IFA
IN_DEM
INT2
INT1
RSSI
OUT_DEM
OUT_DTA
VCC
VCC
VCC
VCC
VCC
FS0/SDEN
Page 21
TH7120
300 to 930MHz
FSK/FM/ASK Transceiver
3901007120 Page 21 of 28 Data Sheet
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FSK test circuit component list to Fig. 4 and Fig. 5
Part Size Value
@ 433.92 MHz
Tolerance Description
C0 0805 0.68 pF
±5%
VCO tank capacitor
C1 0603 6.8 pF
±5%
LNA output tank capacit or
C2 0603 1 pF
±5%
MIX input matching capacitor
C3 0805 10 nF
±10%
data slicer capacitor
C4 0805 100 pF
±10%
demodulator output low-pass capacitor,
depending on data rate
C5 0805 330 pF
±10%
RSSI output low pass capaci tor
CB0 0805 100 nF
±10%
blocking capacitor
CB1 to CB4 0805
0603
330 pF
±10%
blocking capacitor
CB5 0603 330 pF
±10%
blocking capacitor
CB6 0603 10 nF
±10%
blocking capacitor
CB7 0603 330 pF
±10%
blocking capacitor
CF1 0805 390 pF
±5%
loop filter capacitor
CF2 0805 150 pF
±5%
loop filter capacitor
CX1 0805 18 pF
±5%
RO capacitor
CX2 0805 68 pF
±5% RO capacitor for FSK (∆f = ±20 kHz)
CP0 0805 10 - 12 pF
±5%
CERRES parallel capacit or
CRX0 0603 100 pF
±5%
RX coupling capacitor
CTX0 0603 100 pF
±5%
TX coupling capacitor
RB 0805
10 Ω±10%
blocking resistor f or V CC
RP 0805
3.9 KΩ±5%
CERFIL parallel resistor
RF 0805
47 kΩ
±5%
loop filter resistor
RPS 0805
82 kΩ
±5%
power-select resistor, only requi red
at fixed-frequency operation
L0 0805
18 nH
±5%
VCO tank inductor
L1 0603
15 nH
±5%
LNA output tank inductor
LTX0 0805
150 nH
±5%
TX impedance matching induct or
XTAL HC49-SMD 7.1505 MHz
±30ppm calibr.
±30ppm temp.
fundamental-mode crystal, C
load
= 10 pF to 15pF,
C
0, max
= 7 pF, R
m, max
= 70 Ω
CERFIL Leaded
type
SFE10.7MFP @
B
IF2
= 40 kHz
TBD ceramic filter f rom Murata
SMD
type
SFECV10.7MJS-A
@ B
IF2
= 150 kHz
±40 kHz
ceramic filter from Murata
CERRES SMD type
CDACV10.7MG18-A
ceramic demodulat or tank from Murata
Notes:
• NIP – not in place, may be used optionally
• Antenna matching network according to Evaluation Board Description EVB7120
Page 22
TH7120
300 to 930MHz
FSK/FM/ASK Transceiver
3901007120 Page 22 of 28 Data Sheet
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Programmable Channel ASK Application Circuit
Figure 6: Test circuit for programmable channel ASK operation
ASK
output
ASK
input
CX1
CERFIL
XTAL
RPS
RB
CTX0
C1
C2
L1
LTX0
CRX0
L0
RSSI
OUT_MIX
VEE
C3
CB5
C5
C0
CB0
CB1
CB2
CB3
CB6
CB7
RE/SCLK
IN_DTA
ASK/FSK
FSK_SW
RO
VCC
VEE
VCC
FS1/LD
VEE
LF
TNK_LO
OUT_PA
IN_LNA
OUT_LNA
VEE
GAIN_LNA
IN_MIX
VEE
IN_IFA
IN_DEM
INT2
INT1
RSSI
OUT_DEM
OUT_DTA
VCC
VCC
VCC
VCC
VCC
SCLK
SDTA
SDEN
Lock
detect
FS0/SDEN
RF input
RF output
Antenna
matching
network
CF1
CF2
RF
Page 23
TH7120
300 to 930MHz
FSK/FM/ASK Transceiver
3901007120 Page 23 of 28 Data Sheet
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Fixed-Frequency ASK Application Circuit
Figure 7: Test circuit for fixed-frequency ASK operation at 433 MHz
ASK
output
ASK
input
TX
enable
RX
enable
CX1
CERFIL
XTAL
RPS
RB
CTX0
C1
C2
L1
LTX0
CRX0
L0
RSSI
OUT_MIX
VEE
C3
CB5
C5
C0
CB0
CB1
CB2
CB3
CB6
CB7
RE/SCLK
IN_DTA
ASK/FSK
FSK_SW
RO
VCC
VEE
VCC
FS1/LD
VEE
LF
TNK_LO
OUT_PA
IN_LNA
OUT_LNA
VEE
GAIN_LNA
IN_MIX
VEE
IN_IFA
IN_DEM
INT2
INT1
RSSI
OUT_DEM
OUT_DTA
VCC
VCC
VCC
VCC
VCC
FS0/SDEN
RF input
RF output
Antenna
matching
network
CF1
CF2
RF
Page 24
TH7120
300 to 930MHz
FSK/FM/ASK Transceiver
3901007120 Page 24 of 28 Data Sheet
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ASK test circuit component list to Fig. 6 and Fig. 7
Part Size Value
@ 433.92 MHz
Tolerance Description
C0 0805 NIP
±5%
VCO tank capacitor
C1 0603 6.8 pF
±5%
LNA output tank capacit or
C2 0603 1 pF
±5%
MIX input matching capacitor
C3 0805 10 nF
±10%
data slicer capacitor
C5 0805 330 pF
±10%
RSSI output low pass capacitor
CB0 0805 100 nF
±10%
blocking capacitor
CB1 to CB3 0805
0603
330 pF
±10%
blocking capacitor
CB5 0603 330 pF
±10%
blocking capacitor
CB6 0603 10 nF
±10%
blocking capacitor
CB7 0603 330 pF
±10%
blocking capacitor
CF1 0805 1.5 nF
±5%
loop filter capacitor
CF2 0805 150 pF
±5%
loop filter capacitor
CX1 0805 27 pF
±5%
RO capacitor
CRX0 0603 100 pF
±5%
RX coupling capacitor
CTX0 0603 100 pF
±5%
TX coupling capacitor
RB 0805
10 Ω±10%
blocking resistor f or V CC
RF 0805
47 kΩ
±5%
loop filter resistor
RPS 0805
15 kΩ±5%
power-select resistor, only requi red
at fixed-frequency operation
L0 0805
18 nH
±5%
VCO tank inductor
L1 0603
15 nH
±5%
LNA output tank inductor
LTX0 0805
150 nH
±5%
TX impedance matching induct or
XTAL HC49-SMD 7.1505 MHz
±30ppm calibr.
±30ppm temp.
fundamental-mode crystal, C
load
= 10 pF to 15pF,
C
0, max
= 7 pF, R
m, max
= 70 Ω
CERFIL Leaded
type
SFE10.7MFP @
B
IF2
= 40 kHz
TBD ceramic fil t er from Murata
SMD
type
SFECV10.7MJS-A
@ B
IF2
= 150 kHz
±40 kHz
ceramic filter from Murata
Notes:
• NIP – not in place, may be used optionally
• Antenna matching network according to Evaluation Board Description EVB7120
Page 25
TH7120
300 to 930MHz
FSK/FM/ASK Transceiver
3901007120 Page 25 of 28 Data Sheet
Rev. 005 Jan. 2002
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Programmable Channel FSK Application Circuit with AFC
Figure 8: Test circuit for programmable channel FSK operation with AFC
Circuit Features
! Automatic Frequency Control (AFC)
! Increases input frequency acceptance range up to RF
nom
±50 kHz
! Compensation of calibration tolerances of ceramic resonator
! Compensation of temperature tolerances of ceramic resonator
VD
FSK
output
FSK
input
CX1
CX2
CERFIL
XTAL
RPS
RB
CTX0
C1
C2
L1
LTX0
CRX0
L0
RSSI
OUT_MIX
VEE
CERRES
C3
CB5
R2
C5
C4
C0
CB0
CB1
CB2
CB3
CB6
CP1
RE/SCLK
IN_DTA
ASK/FSK
FSK_SW
RO
VCC
VEE
VCC
FS1/LD
VEE
LF
TNK_LO
OUT_PA
IN_LNA
OUT_LNA
VEE
GAIN_LNA
IN_MIX
VEE
IN_IFA
IN_DEM
INT2
INT1
RSSI
OUT_DEM
OUT_DTA
VCC
VCC
VCC
VCC
SCLK
SDTA
SDEN
Lock
detect
FS0/SDEN
CB4
RF input
RF output
Antenna
matching
network
CB7
VCC
CF1
CF2
RF
Page 26
TH7120
300 to 930MHz
FSK/FM/ASK Transceiver
3901007120 Page 26 of 28 Data Sheet
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Fixed-Frequency FSK Application Circuit with AFC
Figure 9: Test circuit for fixed-frequency FSK operation at 433 MHz with AFC
Circuit Features
! Automatic Frequency Control (AFC)
! Increases input frequency acceptance range up to RF
nom
±50 kHz
! Compensation of calibration tolerances of ceramic resonator
! Compensation of temperature tolerances of ceramic resonator
VD
FSK
output
FSK
input
TX
enable
RX
enable
CX1
CX2
CERFIL
XTAL
RPS
RB
CTX0
C1
C2
L1
LTX0
CRX0
L0
RSSI
FS0/SDEN
OUT_MIX
VEE
CERRES
C3
CB5
R2
C5
C4
C0
CB0
CB1
CB2
CB3
CB6
CB7
CP1
RE/SCLK
IN_DTA
ASK/FSK
FSK_SW
RO
VCC
VEE
VCC
FS1/LD
VEE
LF
TNK_LO
OUT_PA
IN_LNA
OUT_LNA
VEE
GAIN_LNA
IN_MIX
VEE
IN_IFA
IN_DEM
INT2
INT1
RSSI
OUT_DEM
OUT_DTA
VCC
VCC
VCC
VCC
VCC
CB4
RF input
RF output
Antenna
matching
network
CF1
CF2
RF
Page 27
TH7120
300 to 930MHz
FSK/FM/ASK Transceiver
3901007120 Page 27 of 28 Data Sheet
Rev. 005 Jan. 2002
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Package Dimensions
Fig. 7: LQFP32 (Low Quad Flat Package)
All Dimension in mm, coplanaríty < 0.1mm
E1, D1 A A1 A2 e b L E, D
αααα
min 0.05 1.35 0.30 0.45 0°
7.00 0.8 9.00
max 1.60 0.15 1.45 0.45 0.75 7°
All Dimension in inch, coplanaríty < 0.004”
min 0.002 0.053 0.012 0.018 0°
0
.27
6
0.0310.35
4
max 0.630 0.006 0.057 0.018 0.030 7°
A1A2A
b
e
1
32
25
1724
8
9
16
D
D1
E1
E
L
Page 28
TH7120
300 to 930MHz
FSK/FM/ASK Transceiver
3901007120 Page 28 of 28 Data Sheet
Rev. 005 Jan. 2002
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Your Notes
Important Notice
Devices sold by Melexis are covered by the warranty and patent indemnification provisions appearing in its Term of Sale. Melexis makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devi ces from patent infringement. Melexis reserves the right to change specifications and prices at any time and without notice. Therefore, prior to designing this product into a system, it
is necessary to check with Melexis for current information. This product is intended for use in normal com mercial applications. Applications requi ring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life- support or life-sustaining equi pment are specifically not recommended without additional processing by Melexis for each application.
The information furnished by Melexis is believed to be correct and accurate. However, Melexis shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interrupt of business or indirect, special incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. No obligation or liability to
recipient or any third party shall arise or flow out of Melexis’ rendering of technical or other services.
© 2000 Melexis GmbH. All rights reserved.
For the latest version of thi s document. Go to our website at
www.melexis.com
Or for additional informat i on contact Melexis Direct:
Europe and Japan: All other locations:
Phone: +32 1361 1631 Phone: +1 603 223 2362
QS9000, VDA6.1 and ISO14001 Certified
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