TC520A
EVALUATION
KIT
AVAILABLE
SERIAL INTERFACE ADAPTER FOR TC500 A/D CONVERTER FAMILY
1
FEATURES
■ Converts TC500/500A/510/514 to Serial Operation
■ Programmable Conversion Rate and Resolution
for Maximum Flexibility
■ Supports up to 17 Bits of Accuracy Plus
Polarity Bit
■ Low Power Operation: Typically 7.5mW
■ 14-Pin DIP or 16-Pin SOIC Packages
■ Polled or Interrupt Mode Operation
ORDERING INFORMATION
Operating
Part No. Package Temp. Range
TC520ACOE 16-Pin SOIC (Wide) 0°C to +70°C
TC520ACPD 14-Pin Plastic DIP 0°C to +70°C
TC500EV Evaluation Kit for TC500 Family
PIN CONFIGURATION
V
V
1
DD
213
DGND
312
CMPTR
411
B
TC520ACPD
510
A
69
OSC
OUT
78
OSC
IN
14
CE
DV
LOAD
D
IN
DCLK
D
OUT
READ
DGND
CMPTR
OSC
OSC
OUT
N/C
1
DD
2
3
4
B
A
IN
5
6
7
8
TC520ACOE
CE
16
DV
15
LOAD
14
D
13
IN
D
12
CLK
D
11
OUT
10
READ
9
N/C
GENERAL DESCRIPTION
The TC520A Serial Interface Adapter provides logic
control for TelCom's TC500/500A/510/514 family of dual
slope, integrating A/D converters. It directly manages TC500
converter phase control signals A, B, and CMPTR thereby
reducing host processor task loading and software complexity. Communication with the TC520A is accomplished over
a 3 wire serial port. Key converter operating parameters are
programmable for complete user flexibility.
Data conversion initiated when the CE input is brought
low. The converted data (plus overrange and polarity bits)
are held in an 18 bit shift register until read by the processor,
or until the next conversion is completed. Data may be
clocked out of the TC520A at any time, and at any rate the
user prefers. A Data Valid (DV) output is driven active at the
start of each conversion cycle indicating the 18 bit shift
register update has just been completed. This signal may be
polled by the processor, or can be used as data ready
interrupt.
The TC520A timebase can be derived from an external
frequency source of up to 6MHz; or can operate from its own
external crystal. It requires a single 5V logic supply and
dissipates less than 7.5mW.
2
3
4
5
FUNCTIONAL BLOCK DIAGRAM
1
V
DD
2
GND
5
A
4
B
CE
DV
OUT
3
14
13
7
IN
÷4
6
CMPTR
OSC
OSC
TELCOM SEMICONDUCTOR, INC.
GATE
LOGIC
CONTROL
SYSCLK
8-BIT SHIFT REG.
8
8-BIT COUNTER
TIME OUT
FORCE AUTO-ZERO
POLARITY BIT
CLEAR COUNT
GATE
÷256
GATE
18-BIT SHIFT REGISTER
16
16-BIT COUNTER
OVERRANGE
BIT
GATE
Pin Out of
14-Pin Package
11
D
IN
12
LOAD
9
D
OUT
10
D
CLK
8
READ
TC520A-1 9/16/96
6
7
8
3-39
TC520A
SERIAL INTERFACE ADAPTER FOR
TC500 A/D CONVERTER FAMILY
ABSOLUTE MAXIMUM RATINGS*
DC Supply Voltage (VDD) ........................................ +6.0V
Input Voltage, All Inputs (VIN)............– 0.3V to VDD +0.3V
Operating Temperature Range (TA).............0°C to +70°C
Storage Temperature Range (T
Lead Temperature (Soldering, 10 sec) (T
ELECTRICAL CHARACTERISTICS: V
) ..... – 65°C to +150°C
STG
) ......+300°C
SDR
DD
= 5V, f
* Static-sensitive device. Unused devices must be stored in conductive
material. Protect devices from static discharge and static fields. Stresses
above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional
operation of the device at these or any other conditions above those
indicated in the Operational Specifications is not implied. Any exposure to
Absolute Maximum Rating Conditions may affect device reliability.
= 1 MHz, TA = +25°C, unless otherwise specified.
osc
Symbol Parameter Min Typ Max Unit
Supply
V
DD
I
DD
Input Characteristics
V
IL
V
IH
I
IL
I
PD
I
PU
Output Characteristics (I
V
OL
V
OH
tR, t
F
Oscillator (OSCIN, OSC
f
XTL
f
OSC
Timing Characteristics
t
RD
t
RS
t
DRS
t
LS
t
DLS
t
PWL
t
PWH
t
LDL
t
LDS
Parameter
t
IZ
t
AZI
= 250 µA, VDD = 5V)
OUT
)
OUT
Operating Voltage Range 4.5 5 5.5 V
Supply Current — 0.8 1.5 mA
Low Input Voltage — — 0.8 V
High Input Voltage 2.0 — — V
Input Leakage Current — — 10 µA
Pull-down Current (CE) — 5 — µA
Pull-up Current (READ, LOAD) — 5 — µA
Low Output Voltage — 0.2 0.3 V
High Output Voltage 3.5 4.3 — V
CL = 10pF, Rise/Fall Times — — 250 nsec
Crystal Frequency — 1.0 4.0 MHz
External Frequency (OSCIN) — — 6.0 MHz
READ Delay Time 250 — — nsec
Data Read Setup Time 1 — — µsec
D
CLK
to D
Delay 450 — — nsec
OUT
LOAD Setup Time 1 — — µsec
Data Load Setup Time 50 — — nsec
D
Pulse Width Low Time 150 — — nsec
CLK
D
Pulse Width High Time 150 — — nsec
CLK
Load Default Low Time 250 — — nsec
Load Default Setup Time 250 — — nsec
Integrator ZERO Time — 0.5 — msec
Autozero (RESET) Time at Power-Up — 100 — msec
3-40
TELCOM SEMICONDUCTOR, INC.
SERIAL INTERFACE ADAPTER FOR
TC500 A/D CONVERTER FAMILY
DETAILED DESCRIPTION
1
TC520A
The TC520A input and output signals are outlined in the
table below.
PIN DESCRIPTIONS
Pin No. Pin No.
14-Pin PDIP 16-Pin SOIC
Package Package Symbol Description
11VDDInput. +5V ±10% power supply input with respect to DGND.
2 2 DGND Input. Digital Ground.
3 3 CMPTR Input, active high or low (depending on polarity of the voltage input to A/D
converter). This pin connects directly to the zero-crossing comparator output
(CMPTR) of the TC5xx A/D converter. A High-to-Low state change on this pin
causes the TC520A to terminate the de-integrate phase of conversion.
4 4 B Output, active high. The A and B outputs of the TC520A connect directly to the
A and B inputs of the TC5xx A/D converter connected to the TC520A. The
binary code on A, B determines the conversion phase of the TC5xx A/D
converter: (A, B) = 01 places the TC5xx A/D converter into the Auto Zero
phase; (A, B) =10 for Integrate phase (INT); (A, B) =11 for De-integrate phase
(D
) and (A, B) = 00 for Integrator Zero phase (IZ). Please see the TC500
INT
family data sheets for a complete description of these phases of operation.
5 5 A Output, active high. See pin 4 description above.
6 6 OSC
7 7 OSC
8 N/C No connection on 16 pin package version.
9 N/C No connection on 16 pin package version.
8 10 READ Input, active low, level and negative edge triggered. A high-to low transition on
911D
10 12 D
OUT
IN
OUT
CLK
Input. This pin connects to one side of an AT-cut crystal having a effective
series resistance of 100Ω (typ) and a parallel capacitance of 20pF (typ). If an
external frequency source is used to clock the TC520A, this pin must be left
floating.
Input. This pin connects to the other side of the crystal described in pin 6
above. The TC520A may also be clocked from an external frequency source
connected to this pin. The external frequency source must be a pulse train
having a duty cycle of 30% (minimum); rise and fall times of 15nsec and a min/
max amplitude of 0 to V
be left floating. A maximum operating frequency of 4MHz (crystal) or 6MHz
(external clock source) is permitted.
READ loads serial port output shift register with the most recent converted
data. Data is loaded such that the first bit transmitted from the TC520A to the
processor is the overrange bit (OVR), followed by the polarity bit (POL) (high =
input positive; low = input negative). This is followed by a 16 bit data word
(MSB first). (OVR is available at the D
This bit may be used as the 17th data bit if so desired.) The D
serial port is enabled only when READ is held low. Otherwise, D
a high impedance state. A serial port read access cycle is terminated at any
time by bringing READ high.
Output, logic level. Serial port output pin. This pin is enabled only when READ
is low (see READ pin description).
Input, positive and negative edge triggered. Serial port clock. With READ low,
serial data is clocked into the TC520A at each low-to-high transition of D
and clocked out of the TC520A on each high-to-low transition of D
maximum serial port D
. If an external frequency source is used, pin 6 must
IH
as soon as READ is brought low.
OUT
OUT
frequency of 3MHz is permitted.
CLK
pin of the
remains in
OUT
. A
CLK
CLK
2
3
4
5
6
7
,
8
TELCOM SEMICONDUCTOR, INC.
3-41
TC520A
PIN DESCRIPTIONS (Cont.)
Pin No. Pin No.
14-Pin PDIP 16-Pin SOIC
Package Package Symbol Description
SERIAL INTERFACE ADAPTER FOR
TC500 A/D CONVERTER FAMILY
11 13 D
12 14 LOAD Input, active low; level and edge triggered. The LOAD VALUE is clocked into
13 15 DV Output, active low. DV is brought any time the TC520A is in the AZ phase of
14 16 CE Input, active low, level triggered. Conversion will be continuously performed as
IN
Input, logic level. Serial port input pin. The TC5xx A/D converter integration
time (TINT) and Autozero time (TAZ) values are determined by the LOAD
VALUE byte clocked into this pin. This initialization must take place at power
up, and can be rewritten (or modified and rewritten) at any time. The LOAD
VALUE is clocked into DIN MSB first.
the 8 bit shift register on board the TC520A while LOAD is held low. The LOAD
VALUE is then transferred into the TC520A internal timebase counter (and
becomes effective) when LOAD is returned high. If so desired, LOAD can be
momentarily pulsed low (eliminating the need to clock a LOAD VALUE into
). In this case, the current state of DIN is clocked into the TC520A timebase
D
IN
counter selecting either a count of 65536 (DIN = High), or count of 32768 (DIN = Low).
conversion. This occurs when either the TC520A initiates a normal AZ phase
by setting A, B, equal to 01; or when CE is pulled high (which overrides the
normal A, B sequencing and forces an AZ state). DV is returned high when the
TC520A exits AZ.
long as CE remains low. Pulling CE high causes the conversion process to be
halted, and forces the TC520 into the AZ mode for as long as CE remains
high. CE should be taken high whenever it is necessary to momentarily
suspend conversion (for example: to change the address lines of an input
multiplexer). CE should be pulled high only when the TC520A enters an AZ
phase (i.e. when DV is low). This is necessary to avoid excessively long
integrator discharge times which could result in erroneous conversion. This pin
should be grounded if unused. It should be left floating if a 0.01µF RESET
capacitor is connected to it (see
Applications
section).
DETAILED DESCRIPTION (CONT.)
TC520A Timing
The TC520A consists of a serial port and state machine.
The state machine provides control timing to both the TC5xx
A/D converter connected to the TC520A, as well as sequential timing for TC520A internal operation. All timing is derived from the frequency source at OSCIN and OSCout. This
frequency source can be either an externally-provided clock
signal, or external crystal. If an external clock is used, it must
be connected to the OSC
floating.
If a crystal is used, it must be connected between the
OSCIN and OSC
OSC
and OSC
IN
and physically located as close to the
OUT
pins as possible. The incoming fre-
OUT
quency is internally divided by 4 and the resulting clock
(SYSCLK) controls all timing functions.
TC5xx A/D Converter Control Signals
The TC520A control outputs (A, B) and control input
(CMPTR) connect directly to the corresponding pins of the
TC5xx A/D converter. A conversion is consummated when
3-42
pin and OSC
IN
must remain
OUT
A, B have been sequenced through the required 4 phases of
conversion: Auto Zero (AZ), Integrate (INT), De-integrate
(D
) and Integrator Zero (IZ) (See Figure 1). The Auto Zero
INT
phase compensates for offset errors in the TC5xx A/D
converter. The integrate phase connects the voltage to be
converted to the TC5xx A/D converter input (resulting in an
integrator output dv/dt directly proportional to the magnitude
of the applied input voltage). Actual A/D conversion (counting) is initiated at the start of the D
phase and terminates
INT
when the integrator output crosses 0V. The integrator output
is then forced to 0V during the IZ phase and the converter is
ready for another cycle. Please see the TC500/500A/510/
514 data sheet for a complete description of these phases.
The number of SYSCLK periods (counts) for the AZ and
INT phases is determined by the LOAD VALUE. The LOAD
VALUE is a single byte that must be loaded into the most
significant byte of 16 bit counter on-board the TC520A during
initialization. The lower byte of this counter is pre-loaded to
a value of 0FFH (25610) and cannot be changed.
The LOAD VALUE (upper 8 bits of the counter) can be
programmed over a range of 0FFH to 00H (corresponding to
TELCOM SEMICONDUCTOR, INC.
SERIAL INTERFACE ADAPTER FOR
TC500 A/D CONVERTER FAMILY
1
TC520A
a range of AZ = INT = 256 counts to 65536 counts). (See
Figure 2). The LOAD VALUE sets the number of counts for
both
the AZ and INT phases and directly affects resolution
and speed of conversion. The
allowed for AZ and INT; the
the
slower
the conversion speed.
The time period required for the D
of the amount of voltage stored on the integrator during the
INT phase, and the value of V
by the TC520A immediately after the INT phase, and terminated when the TC5xx A/D converter changes the state of
the CMPTR input of the TC520A (indicating a zero crossing).
In general, the maximum number of counts chosen for D
is twice that of INT (with V
Choosing these values guarantees a full count (maximum
resolution) during D
The IZ phase is initiated immediately following the D
phase maintained until the CMPTR input transitions high.
This indicates the integrator is initialized and ready for
another conversion cycle. This phase typically takes 2msec.
Serial Port Control Signals
Communication to and from the TC520A is accomplished over a 3 wire serial port. Data is clocked into DIN on
the rising edge of D
edge of D
and can be taken high at any time, which terminates the read
cycle, and releases D
version data is shifted to the processor from D
following order: Overrange bit (which can also be used as
the 17th data bit), Polarity bit, conversion data (MSB first).
. READ must be low to read from the serial port
CLK
when V
INT
and clocked out of D
CLK
OUT
greater
greater
REF
REF
to a high impedance state. Con-
the number of counts
the A/D resolution, but
phase is a function
INT
. The D
chosen at VIN (max)/2).
= VIN(max).
IN
phase is initiated
INT
on the falling
OUT
OUT
in the
INT
INT
APPLICATIONS
TC500 Series A/D Converter Component Selection
The TC500/500A/510/514 data sheet details the equations necessary to calculate values for integration resistor
(R
) and capacitor (C
INT
tors C
apply when using the TC520A, except integration time (T
and Autozero time (TAZ) are functions of the SYSCLK period
(timebase frequency and LOAD VALUE). TelCom offers a
ready-to-use TC5xx A/D converter design tool on a 3 1/2
inch diskette (Windows format). The TC500 Design Spreadsheet is an Excel-based spreadsheet that calculates values
for all components as well as the TC520A LOAD VALUE. It
also calculates overall converter performance such as noise
rejection, converter speed, etc. This software is included in
the TC500EV hardware evaluation kit and is also available
free of charge from your local TelCom representative.
and CAZ and voltage reference V
REF
TELCOM SEMICONDUCTOR, INC.
); auto zero and reference capaci-
INT
. All equations
REF
INT
TC520A Initialization
Initialization of the TC520A consists of:
(1) Power-On RESET of the TC500/520A (forcing the
TC520A into an AZ phase).
(2) Initializing the TC520A LOAD VALUE.
Power-On RESET
The TC520A powers-up with A, B = 00 (IZ Phase),
awaiting a high logic state on CMPTR, which must be
initiated by forcing the TC520A into the AZ phase. This can
be accomplished in one of two ways:
(1) External hardware (processor or logic) can momen-
tarily taking LOAD or CE low for a minimum of 100
msec (tAZI); or
(2) A .01µF RESET capacitor can be connected from
CE to VCC to generate a power-on pulse on CE.
Load Value Initialization
The LOAD VALUE is the preset value (high byte of the
SYSCLK timing counter) which determines the number of
counts allocated to the AZ and INT phases of conversion.
This value can be calculated using the TC520A spreadsheet
within the TC500 Design Spreadsheet software, or can be
setup as shown in the following example:
(1) Select V
Choose the TC5xx A/D converter reference voltage
(V
REF
input voltage. For example, if V
choose V
integration time (TD
maximum integration time (T
count (maximum resolution) during D
(2) Calculate T
)
The TC520A counter length is 16 bits (65536).
Allowing the full 65536 counts for TD
maximum T
(3) Select SYSCLK Frequency
SYSCLK frequency directly affects conversion time.
The faster the SYSCLK, the faster the conversion
time. The upper limit SYSCLK frequency is determined by the worst case delay of the TC500 comparator (which for the TC500 and TC500A is
3.2µsec). While a faster value for SYSCLK can be
used, operation is optimized (error minimized) by
choosing a SYSCLK period (1/SYSCLK frequency)
that is greater than 3.2µsec. Choosing T
, TD
REF
) to be half of the maximum A/D converter
REF
INT
max = 2.5V;
IN
= 1.75V. This forces the maximum de-
) to be equal to twice the
INT
) ensuring a full
INT
INT
INT
INT
= 65536/2 or 32768.
INT
.
results in a
=
SYSCLK
3-43
2
3
4
5
6
7
8
TC520A
SERIAL INTERFACE ADAPTER FOR
TC500 A/D CONVERTER FAMILY
4µsec makes the SYSCLK frequency equal to
250kHz. This makes the external crystal (or frequency source) equal to 1.0MHz (since SYSCLK =
crystal frequency/4). Calculating integration time (in
msec) using T
SYSCLK
= 4µsec, T
= µsec x 32768
INT
= 131msec.
(4) Calculate Load Value
Plug the T
INT
and T
SYSCLK
values into the equation and convert the resulting value to hexadecimal:
LOAD VALUE = [(65536 - (T
INT/TSYSCLK
)]
256
In this example, LOAD VALUE = 128
= 10H. There-
(10)
fore, a LOAD VALUE of 10H is loaded to the TC520A. If the
desired T
was 100msec instead of 131msec, the LOAD
INT
VALUE would be 9EH, and so on. The TC520A LOAD
VALUE must be initialized on power-up, and can be reinitialized as often as desired thereafter. This is accomplished by bringing the LOAD input low while transmitting the
appropriate LOAD VALUE to the TC520A as shown in
Figure 1 and Figure 2.
Polled vs. Interrupt Operation
The TC520A can be accessed at any time by the host
microprocessor. This makes operation in a polled environment especially easy since the most recently converted data
is available to the processor as needed. The TC520A can
also be used in an interrupt environment by connecting DV
to the IRQ line of the processor. Since AZ is the first phase
of a new conversion cycle, the most recently converted data
will be available as soon as DV goes low. If so desired, the
interrupt service routine can also modify the LOAD VALUE
during the DV = low interval.
Opto-Isolated Applications
The 3 wire serial port of the TC520A can be optoisolated for applications requiring isolated data acquisition.
The additional control lines (LOAD, DV, READ) are normally
not needed in such applications, but can also be brought
across the isolation barrier with the addition of a second
isolator.
LOAD
DIN, D
CE
CLK
DV
LOAD VALUE updated
and conversion started
LOAD VALUE
shifted into
D
IN
Figure 1. TC520A Initialization and Start/Stop Conversion Timing Relationships
AZ INTIZDINT
TC520A CONVERSION STATE
AZ INT INTDINT IZ
CE is pulled
high only when
during AZ (DV = LOW)
TC520A held in
AZ phase
as long as CE = HIGH
AZ AZ
New LOAD VALUE
can be loaded
(if so desired)
LOAD
VALUE
3-44
TELCOM SEMICONDUCTOR, INC.
SERIAL INTERFACE ADAPTER FOR
TC500 A/D CONVERTER FAMILY
1
TC520A
DV
DIN, D
CLK
LOAD
CE
AZ INT
TC520A CONVERSION STATE
IZDINT AZ
LOAD VALUE
shift into
D
IN
Figure 2. Load Value Modify Cycle
INT
LOAD VALUE updated
and conversion started
+5V
DINT IZ
AZ
INT
2
3
4
C
INT
10k
100k
V
IN+
V
IN-
100k
TC05
ANALOG GROUND
.01µ
C
R
AZ
INT
.01µ
1
INT
3
CAZ
4
BUF
11
+
IN
10
–
IN
9
+
REF
8
–
REF
5
COM
Figure 3. Typical System Application
CMPTR
TC500
V
CR
CR
GND
+
B
A
–
+
V
–5V
16
14
13
12
6
7
15
2
CRYSTAL
C
REF
DGND
6
7
3
4
5
13
14
2
OSC
OUT
OSC
IN
CMPTR
B
A
DV
CE
GND
TC520A
V
LOAD
READ
D
CLK
D
D
OUT
1
+
12
8
10
11
IN
9
LD
RD
SK
SO
SI
6
CE
DV
7
5
TELCOM SEMICONDUCTOR, INC.
8
3-45
TC520A
SERIAL INTERFACE ADAPTER FOR
TC500 A/D CONVERTER FAMILY
READ FORMAT
LOAD FORMAT
READ
D
OUT
D
CLK
READ
READ
D
D
OUT
OUT
D
D
CLK
CLK
LOAD
D
IN
D
CLK
READ TIMING
t
RD
t
DRS
OVR
MSB
t
POL
RS
t
PWL
MSB
LOAD TIMING
LOAD
D
IN
D
CLK
t
DLS
LSB
t
LS
Figure 4. TC520A Timing Diagram
t
PWH
LOAD DEFAULT TIMING
LOAD
D
IN
t
LDL
t
LDS
LSB
3-46
TELCOM SEMICONDUCTOR, INC.
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