Datasheet T5743P6-TGQ, T5743P6-TG, T5743P3-TG, T5743P3-TGQ Datasheet (ATMEL)

Features

• Tw o Different IF Receiving Bandwidth V ersions Are Available (B

• 5 V to 20 V Automotive Compatible Data Interface

• IC Condition Indicator, Sleep or Active Mode

• Low Power Consumption Due to Configurable Self Polling with a Programmable

Timeframe Check

• High Sensitivity, Especially at Low Data Rates

• Data Clock Available for Manchester- and Bi-phase-coded Signals

• Minimal External Circuitry Requirements, no RF Components on the PC Board Except

Matching to the Receiver Antenna

• Sensitivity Reduction Possible Even While Receiving

• Fully Integrated VCO

• SO20 Package

• Supply Voltage 4.5 V to 5.5 V, Operating Temperature Range -40°C to +105°C

• Single-ended RF Input for Easy Adaptation to λ/4 Antenna or Prin ted Antenna on PCB

• Low-cost Solution Due to High Integration Level

• ESD Protection According to MIL-STD. 883 (4KV HBM)

• High Image Frequency Suppression Due to 1 MHz IF in Conjunction with a SAW Front-

end Filter. Up to 40 dB is Thereby Achievable With State-of-the-art SAWs.

• Communication to Microcontroller Possible Via a Single, Bi-directional Data Line

• Power Management (Polling) Is Also Possible by Means of a Separate Pin Via the

Microcontroller

• Programmable Digital Noise Suppression

= 300 kHz or 600 kHz)

IF

UHF ASK/FSK
Receiver

T5743

Preliminary

Description

The T5743 is a multi-chip PLL receiver device supplied in an SO20 package. It has
been especially developed for the demands of RF low-cost data transmission systems
with data rates from 1 kBaud to 10 k Baud in Manchester or Bi -phase code. The
receiver is well suit ed to op erate with A tmel's P LL RF transmitter U2741B. Its main
applications are in the areas of telemeteri ng, security tec hnology and keyless-entry
systems. It can be used in the frequency receiving range of f

= 300 MH z to 450 MHz

0

for ASK or F SK da ta tr ansm issi on. All t he s tate men ts m ade bel o w refer to 43 3.9 2 MHz
and 315 MHz applications.

System Block Diagram

Figure 1. System Block Diagram

UHF ASK/FSK

Remote control transmitter

U2741B

XTO

PLL

VCO

Power

amp.

Antenna

T5743

Antenna

LNA VCO

UHF ASK/FSK

Remote control receiver

Demod.

IF Amp

PLL XTO

Control

1...5

µC

Rev. 4569A–RKE–12/02

1

Pin Configuration

Figure 2. Pinning SO20

SENS

IC_ACTIVE

CDEM

AVCC

TEST

AGND

MIXVCC

LNAGND

LNA_IN

n.c.

1

2

3

4

5

20

DATA

19

POLLING/_ON

18

DGND

17

DATA_CLK

16

MODE

T5743

6

7

8

9

10

15

14

13

12

11

DVCC

XTO

LFGND

LF

LFVCC

Pin Description

Pin Symbol Function

1 SENS Sensitivity-control resistor
2 IC_ACTIVE IC condition indicator

Low = sleep mode

High = active mode
3 CDEM Lower cut-off frequency data filter
4 AVCC Analog power supply
5 TEST Test pin, during operation at GND
6 AGND Analog ground
7 MIXVCC Power supply mixer
8 LNAGND High-frequency ground LNA and mixer
9 LNA_IN RF input

10 n.c. Not connected
11 LFVCC Power supply VCO
12 LF Loop filter
13 LFGND Ground VCO
14 XTO Crystal oscillator

2

T5743

4569A–RKE–12/02

Pin Description (Continued)

Pin Symbol Function

15 DVCC Digital power supply
16 MODE Selecting 433.92 MHz/315 MHz

Low: f

High: f

17 DATA_CLK Bit clock of data stream
18 DGND Digital ground
19 POLLING/_ON Selects polling or receiving mode

Low: receiving mode

High: polling mode

20 DATA Data output/configuration input

Figure 3. Block Diagram

= 4.90625 MHz (USA)

XT0

= 6.76438 MHz (Europe)

XT0

T5743

CDEM

AVCC

SENS

AGND

DGND

MIXVCC

LNAGND

FSK/ASK-

Demodulator

and data filter

Limiter outRSSI

IF Amp

4. Order

LPF

3 MHz

IF Amp

LPF

3 MHz

Dem_out

Sensitivity
reduction

Data
interface

Polling circuit

and

control logic

FE CLK

Standby logic

VCO XTO

DATA

POLLING/_ON

TEST

DATA_CLK

MODE

DVCC

IC_ACTIVE

LFGND

LFVCC

XTO

4569A–RKE–12/02

LNA_IN

LNA

f

LF

64

3

RF Front-end The RF front-end of the receiv er is a heter odyne conf iguration that c onverts the inp ut

signal into a 1 MHz IF signal. According to F igure 3, the fr ont-end consists of an LNA
(low-noise amplifier), LO (local oscillator), a mixer and an RF amplifier.

The LO generates the carrier frequency for the mixer via a PLL synthesizer. The XTO
(crystal oscillator) generate s the refe rence fr equency f
oscillator) generates the drive voltage frequency f
the voltage at Pin LF. f
f

by the phase frequency detector. The current out put of the phas e frequency detec-

XTO

is divided by fac tor 6 4. T he divid ed f req uency is c ompa red to

LO

LO

tor is connected to a passive loop filter and thereby generates the control voltage V
the VCO. By mean s of th at co n fi g ur at i on V
f

. If f

XTO

is determined, f

LO

can be calculated using the following formula: f

XTO

is controlled in a way th at fLO/64 is equal to

LF

The XTO is a one-pin oscillator that operates at the series resonance of the quartz crys­tal. According to Figure 4, the crystal should be connected to GND via a capacitor CL.
The value of that capacitor is recommended by the crystal supplier. The value of CL
should be optimized for the individual board layout to achieve the exact value of f
hereby of f

. When designing the system in terms of receiving bandwidth, the accuracy

LO

of the crystal and the XTO must be considered.
Figure 4. PLL Peripherals

V

S

DVCC

C

XTO

. The VCO (voltage-contr olled

XTO

for the mixe r. fLO is dependent on

LF

= fLO/64.

XTO

and

XTO

L

for

LFGND

R1 = 820 W

C9 = 4.7 nF

LF

LFVCC

R1

V

S

C9

C10 = 1 nF

C10

The passive loop filter connected to Pin LF is designed for a loop bandwidth of
BLoop = 100 kHz. This va lue for BL oop exhibi ts the best possib le noise perfor manc e of
the LO. Figure 4 shows the appropriate lo op filter compo nents to achiev e the desired
loop bandwidth. If the filter components are changed for any reason please notify that
the maximum capacitive load at Pin LF is limited. If the capacitive load is exceeded, a bit
check may no longer be possible since f

cannot settle in time before the bit check

LO

starts to evaluate the inc omi ng data s tream. Self polling do es th erefor e al so not work i n
that case.

f

is determined by the RF input frequency fRF and the IF frequency fIF using the fol lo w -

LO

ing formula: f

= fRF - f

LO

IF

To determine fLO, the construction of the IF filter must be considered at this point. The
nominal IF frequency is f
quencies, the filter is tuned by the crystal frequency f
fixed relation between f

= 1 MHz. To achieve a good accuracy of the filter’s corner fre-

IF

and fLO. This relation is dependent on the logic level at Pin

IF

. This means that there is a

XTO

MODE.

4

T5743

4569A–RKE–12/02

T5743

This is described by the following formulas:

f

LO

MODE 0 (USA) : f

MODE 1 (Europe) : f

The relation is designed to achieve the nominal IF frequency of f
applications. For applications where f
case of f

= 433.92 MHz, MODE must be set to ‘1’. For other RF frequencies, fIF is

RF

not equal to 1 MHz. f

----------==

IF

314

f

LO

------------------==

IF

432.92
= 1 MHz for most

= 315 MHz, MODE must be set to ‘0’. In the

RF

is then dependent on the logical level at Pin MODE and on fRF.

IF

IF

Table 1 summarizes the different conditions.
The RF input either from an antenna or from a generator must be transformed to the RF

input Pin LNA_ IN. T he in put i mpedan ce o f that pin is p rovide d in the e lectri cal parame­ters. The parasitic board inductances and capacitances also influence the input
matching. The RF receiv er T5743 exhib its its highest sens itivity at the best signal-to­noise ratio in the LNA. Hence, noise matching is the best choice for designing the trans­formation network.

A good practice when designin g the netwo rk is to star t with power m atching. Fr om that
starting point, the values of the components can be varied to some extent to achieve the
best sensitivity.

If a SAW is implemented into the input network a mirror frequency suppression of
DP

= 40 dB can be achiev ed. There are SAWs availab le that exh ibit a notch a t

Ref

Df = 2 MHz. These SAWs work best for an intermediate frequency of f

= 1 MHz. T he

IF

selectivity of the receiver is also imp roved by us ing a SAW. In ty pical auto motive ap pli­cations, a SAW is used.

Figure 5 shows a typical input matching network, for f

= 315 MHz and fRF=

RF

433.92 M Hz using a SAW. Figur e 6 illustrate s an accor ding input matching to 50 W
without a SAW. The input matching networks shown in Figure 6 are the reference net­works for the parameters given in the electrical characteristics.

Table 1. Calculation of LO and IF Frequency

Conditions Local Oscillator Frequency Intermediate Frequency

fRF = 315 MHz, MO DE = 0 fLO = 314 MHz fIF = 1 MHz

= 433.92 MHz, MODE = 1 fLO = 432.92 MHz fIF = 1 MHz

f

RF

300 MHz < f
MODE = 0

365 MHz < f
MODE = 1

< 365 MHz,

RF

< 450 MHz,

RF

f

f

LO

f

LO

RF

-------------------= f
1

1

----------+

314

f

RF

----------------------------= f

1

------------------+

1

432.92

f

LO

----------=

IF

314

f

LO

------------------=

IF

432.92

4569A–RKE–12/02

5

Figure 5. Input Matching Network with SAW Filter

8

LNAGND

T5743

IN
IN_GND

9

LNA_IN

C16

100p

27n

B3555

CASE_GND

3,4 7,8

L3

C17

8.2p

TOKO LL2012

F27NJ

OUT

OUT_GND

5
6

C3

22p

fRF = 433.92 MHz

RF

IN

TOKO LL2012

C2

8.2p

L2

F33NJ

33n

L

25n

1

2

Figure 6. Input Matching Network without SAW Filter

fRF = 433.92 MHz

15p

25n

8

9

LNAGND

T5743

LNA_IN

C3
47p

fRF = 315 MHz

RF

IN

TOKO LL2012

C2

10p

fRF = 315 MHz

33p

L2

F82NJ

82n

25n

L
25n

1
2

IN
IN_GND

8

LNAGND

9

LNA_IN

C16

100p

CASE_GND

8

LNAGND

9

LNA_IN

T5743

L3

47n

B3551

3,4 7,8

T5743

C17

22p

TOKO LL2012

F47NJ

OUT

OUT_GND

5
6

RFIN

3.3p
22n

100p

TOKO LL2012

F22NJ

RF

IN

3.3p
39n

100p

TOKO LL2012

F39NJ

Please notify that fo r all coup ling c onditions (see Fi gure 5 and F igure 6), th e bond w ire
inductivity of the LNA ground is compensated. C3 forms a series resonance circuit
together with the bond wire. L = 25 nH is a feed inductor to establish a DC path. Its
value is not critical but mu st be lar ge en oug h not to detun e the s er ies r esonan ce circuit.
For cost reduction this inductor can be easily printed on the PCB. This configuration
improves the sensitivity of the receiver by about 1 dB to 2 dB.

6

T5743

4569A–RKE–12/02

Analog Signal Processing

T5743

IF Amplifier

The signals coming from the RF front-end are filtered by the fully integrated 4th-order IF
filter. The IF center frequency is f
f

= 433 .92 MHz is used. For other RF inpu t frequenc ies refer to Table 1 to d etermine

RF

= 1 MHz for applications where fRF= 315 MHz or

IF

the center frequency.
The T5743 is available with two different IF bandwidths. T5743P3, the vers ion with

B

= 30 0 kHz, is well su ited for ASK sy stem s where Atme l’s PLL tr ansm itter U2 741B is

IF

used. The receiver T5743P6 employs an IF bandwidth of B

= 600 kHz. Both versions

IF

can be used together with the U2741B in ASK and FSK mode. If used in ASK applica­tions, it allows higher tolerances for the receiv er and PLL transmitter crystals. SAW
transmitters ex hibit muc h higher tran smit freq euncy toleranc es compare d to PLL tr ans­mitters. Generally, it is necessary to use B

= 600 kHz together with such transmitters.

IF

RSSI Amplifier The subsequent RSSI amplifier enhances the output signal of the IF amplifier before it is

fed into the demodulator. The dynamic range of this amplifier is DR
RSSI amplifier is operated within its linear range, the best S/N ratio is maintained in ASK
mode. If the dynamic range is exceeded by the transmitter signal, the S/N ratio is
defined by the ratio of the maximum RSSI output voltage and the RSSI output voltage
due to a disturber. The dynamic ran ge of the RSSI am plifier is exceede d if the RF input
signal is about 60 dB higher compared to the RF input signal at full sensitivity.

In FSK mode the S/N ratio is not affected by the dynamic range of the RSSI amplifier.
The output voltage of the RSSI amplifier is internally compared to a threshold voltage

V

. V

Th_red

nected between Pin S ENS a nd G ND or V

is determined by the value of th e external res istor R

Th_red

. The output of the c om par at or is f ed into the

S

digital control logic. By this means it is possible to operate the receiver at a lower
sensitivity.

= 60 dB. If the

RSSI

. R

Sens

Sens

is con-

If R
If R

sitivity is defined by the value of R

is connected to GND, the receiver operates at full sensitivity.

Sens

is connected to VS, the receiver operates at a lower sensitivity. The reduced sen-

Sens

, the maximum sensitivity by the signal-to-noise

Sens

ratio of the LNA input. The reduced sensitivity depends on the signal strength at the out­put of the RSSI amplifier.

Since different RF in put netw orks may ex hibit sli ghtly di fferent val ues for the LN A gain,
the sensitivit y values giv en in the elect rical chara cteristics r efer to a specif ic input
matching. This matching is illustrated in Figure 6 and exhibits the best possible
sensitivity.

R

can be connected to VS or GND via a mic rocontrolle r. The receiver can be

Sens

switched from full sensitivity to reduced sensitivity or vice versa at any time. In polling
mode, the receiver will not wake up if the R F input signal doe s not exceed the se lected
sensitivity. If the receiver is already active, the data stream at Pin DATA will disappear
when the input signal is lower than defined by the reduced sensitivity. Instead of the
data stream, the pattern according to Figure 7 is issued at Pin DATA to indicate that the
receiver is still active (see also figure 34).

Figure 7. Steady L State Limited DATA Output Pattern

DATA

t

DATA_min

t

DATA_L_max

4569A–RKE–12/02

7

FSK/ASK Demodulator
and Data Filter

The signal coming from the RSSI amplifier is converted into the raw data signal by the
ASK/FSK demodulator. The operating mode of the demodulator is set via the bit
ASK/_FSK in the OPMODE register. Logic ‘L’ sets the demodulator to FSK, applying ‘H’
to ASK mode.

In ASK mode, an automatic threshold control circuit (ATC) is used to set the detection
reference volt age t o a v alue wh ere a go od s ignal- to-no ise r atio is a chiev ed. T his c ircui t
effectively suppre ss es any ki nd o f inband noise signals o r comp eti ng tr an sm itte r s. If the
S/N (ratio to suppress inban d noise signals) exceeds 10 dB, the data signal c an be
detected properly.

The FSK demodulator is intended to be used for an FSK dev iation of 10 kHz £ Df £
100 kHz. In FSK mode the data signal can be detected i f the S/N (ratio to suppress
inband noise signals) exceeds 2 dB. This value is guaranteed for all modulation
schemes of a disturber signal.

The output signal of the demo dulator is filtered by the data filter befo re it is fed in to the
digital signal processing circuit. The data filter improves the S/N r atio as its passband
can be adopted to the characteristics of the data signal. The data filter consists of a

st

1

-order highpass and a 2nd-order lowpass filter.

The highpass filter cut-off frequency is defined by an external capacitor connected to Pin
CDEM. The cut-off frequency of the highpass filter is defined by the following formula:

fcu_DF

In self-polling mode , the data fil ter mu st settle very rapidly to ac hie ve a lo w cu r rent c on­sumption. Therefore, CDEM cannot be increased to very high values if self-polling is
used. On the other hand, CDEM must be large enough to meet the data filter require­ments according to the d ata signal. Reco mmended val ues for CDEM ar e given in th e
electrical character isti cs .

-----------------------------------------------------------=

2 p 30 kW´ CDEM´´

1

Receiving
Characteristics

The cut-off frequenc y of the lowpass fi lter is define d by the selecte d baud-rate ra nge
(BR_Range). The BR_Range is defined i n the OPMODE registe r (refer to se ction ‘ Con­figuration of the Receiver’). The BR_Range must be set in accordance to the used baud
rate.

The T5743 is designed to operate with data coding where the DC level of the data signal
is 50%. This is valid for Manchest er and Bi -phase c oding. If ot her modula tion sc hemes
are used, the DC level should always remain withi n the range of V
V

Each BR_Range is also defined by a minimum and a maximum edge-to-edge time
(t
exceeded to maintain full sensitivity of the receiver.

The RF receiver T5743 can be operat ed with and without a SAW front-end filter. In a
typical automotive application, a SAW filter is used to achieve better selectivity. The
selectivity with and without a SAW front-end filter is illustrated in Figure 8. This example
relates to ASK mode an d the 300-kHz bandwid th versi on of the T5743 . FSK mod e and
the 600-kHz bandwidth version of the rec eiver exhibits simi lar behavior. Note that the
mirror frequency is reduced by 40 dB. The plots are printed relatively to the maximum
sensitivity. If a SAW filter is used, an insertion loss of about 4 dB must be considered.

= 66%. The sensitivity may be reduced by up to 2 dB in that condition.

DC_max

). These limits are defined in the electrical characteristics. They should not be

ee_sig

DC_min

= 33% and

8

T5743

4569A–RKE–12/02

T5743

Figure 8. Receiving Frequency Response

0.0

-10.0

-20.0

-30.0

-40.0

-50.0

-60.0

dP (dB)

-70.0

-80.0

-90.0

-100.0

-6.0 -5.0 -4.0 -3.0 -2.0 -1.0 0.0 1.0 2.0 3.0 4.0 5.0 6.0

df (MHz)

When designing the system in terms of receiving bandwidth, the LO deviation must be
considered as it also determines the IF center frequency. The total LO deviation is cal­culated to be the sum of the deviation of the crystal and the XTO deviation of the T5743.
Low-cost crystals are sp ecifi ed to be withi n ±100 ppm. The XT O deviat ion of the T 5743
is an additional d eviation due t o the XTO c ircuit. This de viation is spe cified to be
±30 ppm. If a crystal of ±100 ppm is use d, the to tal deviatio n is ±130 ppm in tha t case.
Note that the receiving bandwidth a nd the IF-filter bandwidth are e quivalent in ASK
mode but not in FSK mode.

without SAW

with SAW

Polling Circuit and
Control Logic

Basic Clock Cycle of the
Digital Circuitry

The receiver is designed to consume less than 1 mA while being sensitive to signals
from a corresponding transmitter. This is achieved via the polling circuit. This circuit
enables the signal path per iodicall y for a short time. Dur ing this time the bit-check logic
verifies the presence of a valid transmitter signal. Only if a valid signal is detected the
receiver remains ac tive and trans fers the d ata to the connec ted mi crocon troller . If there
is no valid signal pres ent the receive r is in sleep mode most of the tim e resulting in low
current consumpt ion . T hi s c ond iti on is c al led polling mode. A c on nec ted mi cr o con troll er
is disabled during that time.

All relevant parameters of the polling logic can be configured by the connected micro­controller. This flexibility enables the user to meet the specifications in terms of current
consumption, system response time, data rate etc.

Regarding the number of con nection wires to the microcontroll er, the receiver is ve ry
flexible. It can be ei ther op erated by a singl e bi-dir ectiona l line to save p orts to the con­nected microcontroller or it can be operated by up to five uni-directional ports.

The complete timing of the digital circuitry and the analog filtering is derived from one
clock. According to Figure 9, th is clock cycle T

is derived from the c rystal osc illator

Clk

(XTO) in combination with a di vide r. The di vision factor i s cont rolled by the l ogical s tate
at Pin MODE. According to section “RF Front-end”, the frequency of the crystal oscillator
(f

) is defined by the RF input signal (f

XTO

of the local oscillator (f

LO

).

) which also defines the operating frequency

RFin

4569A–RKE–12/02

9

Figure 9. Generation of the Basic Clock Cycle

T

Clk

Divider

:14/:10

MODE

16

L : USA(:10)
H: Europe(:14)

f

XTO

XTO

Pin MODE can now be se t in accord ance with t he de sired c lock c ycle T

DVCC

15

XTO

14

Clk

. T

controls

Clk

the following application relevant parameters:

• Timing of the polling circuit including bit check

• Timing of the analog and digital signal processing

• Timing of the register programming

• Frequency of the reset marker

• IF filter center frequency (f
Most applications ar e dominated by two trans missio n frequencies : f

mainly used in USA, f

= 433.92 MHz in Europe. In order to ease the usage of all T

Send

IF0

)

= 315 MHz is

Send

Clk

dependent parameters on this electrical characteristics display three conditions for each
parameter.

• Application USA (f

• Application Europe (f

• Other applications (T
The electrical characteristic is given as a function of T

= 4.90625 MHz, MODE = L, T

XTO

= 6.76438 MHz, MODE = H, T

XTO

is dependent on f

Clk

XTO

= 2.0383 µs)

Clk

= 2.0697 µs)

Clk

and on the logical state of Pin MODE.

).

Clk

The clock cycle of some function blocks depends on the selected baud-rate range
(BR_Range) which is define d in the OPMODE reg ister. T his cloc k cycl e T

is defined

XClk

by the following formulas for further reference:

-

BR_Range = BR_Range0: T

BR_Range1: T
BR_Range2: T
BR_Range3: T

XClk
XClk
XClk
XClk

= 8 ´ T
= 4 ´ T
= 2 ´ T
= 1 ´ T

Clk
Clk
Clk
Clk

Polling Mode According to Figure 10, the receiver stays in polling mode in a continuous cycle of three

different modes. In sleep mode the signal processi ng circuitry is disabled for the time

10

T5743

period T
all signal processing circuits are enabled and settled. In the following bit-check mode,
the incoming data stream is analyzed bit by bit contra a valid transmitter signal. If no
valid signal is present, the receiver is set back to sleep mode after the period T
This period varies check by check as it is a statistical process. An average value for
T

Bit-check

consumption is I
The average curre nt co nsu mpt ion i n p o llin g mode is dependent on the duty cycle of the
active mode and can be calculated as:

while consuming low current of IS=I

Sleep

. During the start-up perio d, T

Soff

is given in the electrical characteristics. During T

=I

S

. The condition of the receiver is indicated on Pin IC_ACTIVE.

Son

Startup

and T

the current

Bit-check

4569A–RKE–12/02

Startup

Bit-check

,

.

T5743

I

I

Spoll

During T

SoffTSleepISon

--------------------------------------------------------------------------------------------------------------=

Sleep

T

SleepTStartupTBit-check

and T

Startup

tee the reception o f a tran sm itte d command the trans mi tte r mus t st ar t th e t ele gr am wi th
an adequate preburst. The required length of the preburst depends on the polling
parameters T
(T

Start,µC

). Thus, T

Sleep

, T

Startup

Bit-check

to be tested.
The following formula indicates how to calculate the preburst length.
T

Preburst

³ T

Sleep

+ T

Startup

Sleep Mode The length of period T

the extension factor XSleep (according to Table 9), and the basic clock cycle T
calculated to be:

T

= Sleep ´ X

Sleep

In US- and European applications, the maximum value of T
is set to 1. The time resolutio n is about 2 ms in that case. The s leep time can be
extended to almost half a second by setting XSleep to 8. XSleep can be set to 8 by bit
XSleep

Std

to 1.

According to Tabl e 8, the hi gh es t reg is ter va lue o f s le ep sets th e re ce iv er i nto a p er ma­nent sleep condition. The receiver remains in that condition until another value for Sleep
is programmed into the O PMODE register. This function is desirable wher e several
devices share a singl e data line and may als o be used for micr ocontroll er polling — vi a
Pin POLLING/_ON, the receiver can be switched on and off.

Sleep

T

+()´+´

StartupTBit-check

++

the receiver i s no t sensi tive to a tra nsm itter s ignal . To gu aran-

, T

depends on the actual bit rate and the number of bits (N

+ T

is defined by the 5-bit word Sleep of the OPMODE register,

Sleep

´ 1024 ´ T

and the start-up time of a connected mi crocontr oller

Bit-check

+ T

Bit-check

Clk

Start_µC

is about 60 ms if XSleep

Sleep

Bit-check

Clk

)

. It is

4569A–RKE–12/02

11

Figure 10. Poll ing Mode Flow Chart

Sleep mode:

Sleep mode:

Sleep mode:

All circuits for signal processing are

All circuits for signal processing are

All circuits for signal processing are
disabled. Only XTO and Polling logic is

disabled. Only XTO and Polling logic is

disabled. Only XTO and Polling logic is
enabled.

enabled.

enabled.
Output level on Pin IC_ACTIVE => low

Output level on Pin IC_ACTIVE => low

Output level on Pin IC_ACTIVE => low

= I

= I

I

I

= I

I

S

Soff

S

Soff

S

Soff

= Sleep ´ X

= Sleep ´ X

T

T

= Sleep ´ X

T

Sleep

Sleep

Sleep

Start-up mode:

Start-up mode:

Start-up mode:

The signal processing circuits are

The signal processing circuits are

The signal processing circuits are
enabled. After the start-up time (T

enabled. After the start-up time (T

enabled. After the start-up time (T
all circuits are in stable

all circuits are in stable

all circuits are in stable
condition and ready to receive.

condition and ready to receive.

condition and ready to receive.
Output level on Pin IC_ACTIVE => high

Output level on Pin IC_ACTIVE => high

Output level on Pin IC_ACTIVE => high

IS = I

IS = I

IS = I

Son

Son

Son

T

T

T

Startup

Startup

Startup

Bit-check mode:

Bit-check mode:

Bit-check mode:

The incomming data stream is

The incomming data stream is

The incomming data stream is
analyzed. If the timing indicates a valid

analyzed. If the timing indicates a valid

analyzed. If the timing indicates a valid
transmitter signal, the receiver is set to

transmitter signal, the receiver is set to

transmitter signal, the receiver is set to
receiving mode. Otherwise it is set to

receiving mode. Otherwise it is set to

receiving mode. Otherwise it is set to
Sleep mode.

Sleep mode.

Sleep mode.
Output level on Pin IC_ACTIVE => high

Output level on Pin IC_ACTIVE => high

Output level on Pin IC_ACTIVE => high

IS = I

IS = I

IS = I

Son

Son

Son

T

T

T

Bit-check

Bit-check

Bit-check

NO

NO

NO

´ 1024 T

´ 1024 T

´ 1024 T

Sleep

Sleep

Sleep

Bit-check

Bit-check

Bit-check

OK ?

OK ?

OK ?

Clk

Clk

Clk

Startup

Startup

Startup

Sleep: 5-bit word defined by Sleep0 to

Sleep: 5-bit word defined by Sleep0 to

Sleep: 5-bit word defined by Sleep0 to
XSleep: Extension factor defined by

XSleep: Extension factor defined by

XSleep: E xtension factor defin ed by
T

T

T

Clk

Clk

Clk

T

T

T

Startup

Startup

)

)

)

Startup

T

T

T

Bit-check

Bit-check

Bit-check

number of bits to be checked (N

number of bits to be checked (N

number of bits to be checked (N

Sleep4 in OPMODE register

Sleep4 in OPMODE register

Sleep4 in OPMODE register

according to Table 9

XSleep

XSleep

: Basic clock cycle defined by f

: Basic clock cycle defined by f

XSleep

: Basic clock cycle defined by f

and Pin MODE

and Pin MODE

and Pin MODE

: Is defined by the selected baud rate

: Is defined by the selected baud rate

: Is defined by the selected baud rate

range and T

range and T

range and TClk. The baud-rate range is

defined by Baud0 and Baud1 in the

defined by Baud0 and Baud1 in the

defined by Baud0 and Baud1 in the

OPMODE register.

OPMODE register.

OPMODE register.

: Depends on the result of the bit check.

: Depends on the result of the bit check.

: Depends on the result of the bit check.

If the bit check is ok, T

If the bit check is ok, T

If the bit check is ok, T

the utilized data rate.

the utilized data rate.

the utilized data rate.

according to Table 9

according to Table 9

Std

Std

Std

. The baud-rate range is

. The baud-rate range is

Clk

Clk

Bit-check

Bit-check

Bit-check

XTO

XTO

XTO

depends on the

depends on the

depends on the

Bit-check

Bit-check

Bit-check

) and on

) and on

) and on

YES

YES

Receiving mode:

Receiving mode:

Receiving mode:

The receiver is turned on permanently

The receiver is turned on permanently

The receiver is turned on permanently
and passes the data stream to the

and passes the data stream to the

and passes the data stream to the
connected microcontroller.

connected microcontroller.

connected mC.
It can be set to Sleep mode through an

It can be set to Sleep mode through an

It can be set to Sleep mode through an
OFF command via Pin DATA or

OFF command via Pin DATA or

OFF command via Pin DATA or
POLLING/_ON.

POLLING/_ON.

POLLING/_ON.
Output level on Pin IC_ACTIVE => high

Output level on Pin IC_ACTIVE => high

Output level on Pin IC_ACTIVE => high

IS = I

IS = I

IS = I

Son

Son

Son

YES

OFF command

OFF command

OFF command

If the bit check fails, the average time period

If the bit check fails, the average time period

If the bit check fails, the average time period

for that check depends on the selected baud-

for that check depends on the selected baud-

for that check depends on the selected baud-

rate range and on T

rate range and on T

rate range and on T

defined by Baud0 and Baud1 in the OPMODE register

defined by Baud0 and Baud1 in the OPMODE register

defined by Baud0 and Baud1 in the OPMODE register

. The baud-rate range is

. The baud-rate range is

. The baud-rate range is

Clk

Clk

Clk

12

T5743

4569A–RKE–12/02

Figure 11. Timing Diagram for Complete Successful Bit Check

T5743

( Number of checked Bits: 3 )

IC_ACTIVE

Bit check

Dem_out

Data_out (DATA)

Start-up mode

T

Start-up

1/2 Bit

1/2 Bit

T

Bit-check

Bit-check mode

Bit check ok

1/2 Bit 1/2 Bit 1/2 Bit 1/2 Bit

Receiving mode

Bit-check Mode In bit-check mode the incomin g data stream is examine d to distinguis h between a vali d

signal from a corresponding transmitter and signals due to noise. This is done by subse­quent time frame checks where the distances between two signal edges are
continuously compared to a programmable time window. The maximum count of this
edge-to-edge te sts before the receiver switches to receiv ing mode is also
programmable.

Configuring the Bit Check Assuming a modulation sche me that contains two edg es per bit, two tim e frame ch ecks

are verifying one bit. This is valid for Manchester, Bi-phase and most other modulation
schemes. The maximum count of bits to be checked can be set to 0, 3, 6 or 9 bits via the
variable N

Bit-check

checks respectively. If N

in the OPMODE r egister. T his implie s 0, 6, 1 2 and 18 edge to edge

Bit-check

is set to a higher value, the receiv er is less likely to
switch to receiv ing mode due to noise. In the presenc e of a valid tr ansmit ter signal, the
bit check takes less time if N
time is not dependent on N

Bit–check

Bit-check

is set to a lower value. In polling mode, the bit-check

. Figure 11 shows a n example where 3 bits are te ste d

successfully and the data signal is transferred to Pin DATA.
According to Figure 12, the time window for the bit check is defined by two separate

time limits. If the edge-to-edge time t
the upper bit-check limit T
T

Lim_min

or tee exceeds T

Lim_max

Lim_max

is in between the lower bit-check limit T

ee

Lim_min

and

, the check will be continued. If tee is smaller than

, the bit check will be terminated and the receiver

switches to sleep mode.
Figure 12. Valid Time Window for Bit Check

1/f

Sig

t

Dem_out

For best noise immunity it is recomme nded to use a low span between T
T

. This is achieved using a fixed frequency at a 50% duty cycle for the transmitter

Lim_max

T

Lim_min

T

Lim_max

ee

and

Lim_min

preburst. A “11111...” or a “10101...” sequence in Manchester or Bi-phase is a good
choice concerning that advice. A good compromise between receiver sensitivity and
susceptibility to noise is a time window of ±25% regarding the expected edge-to-edge
time t

. Using pre-burst patterns that contain various edge-to-edge ti me periods, the

ee

bit-check limits must be programmed according to the required span.
The bit-check limits are determined by means of the formula below.

4569A–RKE–12/02

13

T
T

= Lim_min ´ T

Lim_min

= (Lim_max –1) ´ T

Lim_max

Lim_min and Lim_max are defined by a 5-bit word each within the LIMIT register.
Using above formulas, Lim_min and Lim_max can be determined according to the

required T
T

. The minimum edge-to-edge time tee (t

XClk

to the section ‘Receiving Mode’. The lower limit should be set to Lim_min ³ 10. The
maximum value of the upper limit is Lim_max = 63.

If the calculated value for Lim_min is < 19, it is recommended to check 6 or 9 bits
(N

) to prevent switching to receiving mode due to noise.

Bit-check

Figure 13, Figure 14 and Figure 15 illustrate the bit check for the bit-check li mits
Lim_min = 14 and Lim_max = 24. When the IC is enabled, the signal processing circuits
are enabled during T
fined during that period. Whe n the bit check becomes active, the bit-ch eck counter is
clocked with the cycle T

Figure 13 shows how the bit check proceeds i f the bit-check counter value CV_Lim is
within the limits defined by Lim_min and Lim_max at the occurrence of a signal edge. In
Figure 14 the bit check fails as the va lue CV_l im is lower than the li mi t Lim _min. T he bi t
check also fails if CV_Lim reaches Lim_max. This is illustrated in Figure 15.

Figure 13. Timing Diagram During Bit Check

Lim_min

, T

XClk

Lim_max

Startup

XClk

and T

. The time resolution de fining T

XClk

DATA_L_min

, t

DATA_H_min

and T

Lim_min

Lim_max

) is defined according

. The output of the ASK/FSK demodulator (Dem_out) is unde-

.

XClk

is

( Lim_min = 14, Lim_max = 24 )

IC_ACTIVE

Bit check

Dem_out

Bit-check­counter

0

T

Start-up

Start-up mode

1/2 Bit

8

7

6 245

345

1

2

T

XClk

3 6789 111213

1

10

T

Bit-check mode

14

Bit-check

Bit check ok

17 181234

15 16

Figure 14. Timing Diagram for Failed Bit Check (Condition: CV_Lim < Lim_min)

( Lim_min = 14, Lim_max = 24 )

IC_ACTIVE

Bit check

Dem_out

Bit-check­counter

0

T

Start-up

Start-up mode

2345

1 1

6 245

36

T

Bit-check

Bit-check mode

Bit check failed ( CV_Lim < Lim_min )

1/2 Bit

789 111210

0

Sleep mode

T

Sleep

Bit check ok

1/2 Bit 1/2 Bit

56

78910111213

14 15

1234

14

T5743

4569A–RKE–12/02

Figure 15. Timing Diagram for Failed Bit Check (Condition: CV_Lim ³ Lim_max)

T5743

( Lim_min = 14, Lim_max = 24 )

IC_ACTIVE

Bit check

Dem_out

Bit-check­counter

0

T

Start-up

Start-up mode

23

45

1/2 Bit

6

2451

36789

1

7

T

Bit-check

Bit-check mode

11 1210

14 15 161718 19 21 22 23 24

13

Bit check failed ( CV_Lim >= Lim_max )

20

0

T

Sleep

Sleep mode

Duration of the Bit Check If no transmitter signal is present during the bit check, the output of the ASK/FSK

demodulator deli ve rs random signals. T he bit ch ec k is a sta tis ti ca l p r oce ss a nd T
varies for each check. T herefor e, an aver age v alue for T
characteristics. T
baud-rate range causes a lo wer va lu e for T

depends on the selected baud-rate range and on T

Bit-check

resulting in a lower current consump-

Bit-check

is given in the electrical

Bit-check

Bit-check

. A higher

Clk

tion in polling mode.
In the presence of a valid transmitter signal, T

that signal, f
thereby results in a long er per io d for T
pre-burst T

, and the count of the checked bits, N

Sig

Bit-check

Preburst

.

requiring a higher val ue fo r the tr ans mitter

Receiving Mode If the bit check was successful for all bits sp ecified by N

is dependent on the frequency of

Bit-check

. A higher value fo r N

Bit-check

, the receiver switches to

Bit-check

Bit-check

receiving mode. According to Figure 11, the internal data signal is switched to Pin DATA
in that case and the data clock is avai lable aft er the start bi t has been de tected (F igure

22). A connected microcontroller can be woken up by the negative edge at Pin DATA or
by the data clock at Pin DATA_CLK. The receiver stays in that condition until it is
switched back to polling mode explicitly.

Digital Signal Processing The data from the ASK/FSK demodulator (Dem_out) is digitally proce ssed in different

ways and as a result co nve rted i nto the o utput signal data. This pr oc ess in g dep end s o n
the selected baud-rate range (BR_Ran ge). Figure 16 illustrates how Dem_out is syn­chronized by the extended clock cycle T
counter. Data can change its state on ly after T
period t

of the Data signal as a result is always an integral multiple of T

ee

The minimum time peri od between two edges of the data signal is limited to t
T

DATA_min

. This implies an efficient suppression of spikes at the DATA output. At the

. This clock is als o used for the bi t-check

XClk

has elapsed. The edg e-to- edge tim e

XClk

XClk

.

ee

³

same time it limits the maximum frequency of edges at DATA. This eases the interrupt
handling of a connected microcontroller.

The maximum time period for DATA to stay Low is limited to T

DATA_L_max

. This function is
employed to ensu re a finite res ponse time in pro grammin g or switc hing off the recei ver
via Pin DATA. T

DATA_L_max

is thereby longer than the maxi mum tim e peri od indi cated by
the transmitter data stream. Figure 18 gives an example where Dem_out remains Low
after the receiver has switched to receiving mode.

15

4569A–RKE–12/02

Figure 16. Synchronization of the Demodulator Output

T

XClk

Clock bit-check
counter

Dem_out

Data_out (DATA)

t

ee

Figure 17. Debouncing of the Demodulator Output

Dem_out

Data_out (DATA)

t

DATA_min

t

ee

t

DATA_min

t

ee

Figure 18. Steady L State Limited DATA Output Pattern After Transmission

IC_ACTIVE

Bit check

t

DATA_min

t

ee

16

Dem_out

Data_out (DATA)

T5743

Start-up mode

t

DATA_L_max

Bit-check mode

Receiving mode

t

DATA_min

After the end of a data transmission, the receiver remains active. Depending on the bit
Noise_Disable in the OPMODE register, the output signal at Pin DATA is high or ran­dom noise pulses appear at Pin DATA (see section “Digital Noise Supression”). The
edge-to-edge time period t
higher than T

DATA_min

.

of the majority of these noise pulses is equal or slightly

ee

4569A–RKE–12/02

T5743

Switching the Receiver Back
to Sleep Mode

The receiver can be set back to polling mode via Pin DATA or via Pin POLLING/_ON.
When using Pin DATA, this pin must be pulled to Low for the period t1 by the connected

microcontroller. Figure 19 illustrates the timing of the OFF co mmand (see also Figure

34). The minimum v alue of t1 depen ds on BR_Ran ge. The maxi mum va lue for t1 is not
limited but it is recommended not to exceed the specified value to prevent erasing the
reset marker. Note also that an internal reset for the OPMODE and the LIMIT register
will be generated if t1 exceeds the specified values. This item is explained in more detail
in the section “Configuration of the Receiver”. Setting the receiver to sleep mode via
DATA is achieved by pr ogramming bit 1 to be “1” dur in g th e r egister configuration. O nly
one sync pulse (t3) is issued.

The duration of the OFF c ommand is determ ined by th e sum of t1, t2 and t10. Afte r the
OFF command the sl ee p ti me T
is limited (see section “Data Interface”).

Figure 19. Timing Diagram of the OFF-command via Pin DATA

IC_ACTIVE

IC_ACTIVE

IC_ACTIVE

IC_ACTIVE

Out1

Out1

Out1

Out1 (mC)

(microcontroller)

(microcontroller)

(microcontroller

Data_out (DATA)

Data_out (DATA)

Data_out (DATA)

Data_out (DATA)

X

X

X

X

t1 t2 t3t4t5

t1 t2 t3

t1 t2 t3

t1 t2 t3

t4

t4

t4

t5

t5

t5

t10

t10

t10

t10

t7

t7

t7

t7

elapses. Note that the c apa ci tiv e loa d a t P in DATA

Sleep

Serial bi-directional

Serial bi-directional

Serial bi-directional

Serial bi-directional

data line

data line

data line

data line

X

X

X

X

Receiving

Receiving

Receiving

Receiving

mode

mode

mode

mode

OFF-command

OFF-command

OFF-command

OFF-command

Bit 1

Bit 1

Bit 1

Bit 1

("1")

("1")

("1")

("1")

(Start bit)

(Start bit)

(Start bit)

(Start bit)

Figure 20. Timing Diagram of the OFF-command via Pin POLLING/_ON

IC_ACTIVE

POLLING/_ON

Data_out (DATA)

Serial bi-directional
data line

t

on2

X

X

Receiving mode

t

on3

Sleep mode Start-up mode Bit-check mode Receiving mode

T

T

T

Sleep

Sleep

Sleep

T

Sleep

Sleep mode

Sleep mode

Sleep mode

Sleep mode

Bit check ok

T

T

T

Start-up

Start-up

Start-up

T

Start-up

Start-up mode

Start-up mode

Start-up mode

Start-up mode

X

X

4569A–RKE–12/02

17

Figure 21. Activating the Receiving Mode via Pin POLLING/_ON

IC_ACTIVE

t

on1

POLLING/_ON

Data_out (DATA)

Serial bi-directional
data line

X

X

Sleep mode Receiving mode

Start-up mode

Figure 20 illustrates how to set the receiver back to polling mode via Pin POLLING/_ON.
The Pin POLLING/_ON must be held to low for the time per iod t
edge on Pin POLLING /_ON and t he del ay t
time T

Sleep

elapses.

, the polling mode is ac tive and the sleep

on3

. After the positive

on2

This command is faster than using Pin DATA at the cost of an additional connection to
the microcontroller.

Figure 21 illustrates how to set the receiver to receiv ing mode via the Pin POLL­ING/_ON. The Pin PO LLI NG/_O N mu st be he ld t o Lo w. Af ter t he de lay t
changes from sleep mode to start-up mode regardless the programmed values for T
and N

Bit-check

will be ignored, but not deleted (see also section “Digital Noise Suppression”).

check

If the receiver is polled exclusively by a microcontroller, T

. As long as POLLING /_ON is held t o Low, the v alues for T

must be programmed to

Sleep

, the recei ve r

on1

and N

Sleep

Sleep

Bit-

31 (permanent sleep m ode ). In thi s ca se the r ec ei ver remains in sleep mode as lon g as
POLLING/_ON is held to High.

Data Clock The Pin DATA_CLK makes a data shift clock available to sample the data stream into a

shift register. Using this data clo ck, a microcontrolle r can easily synchron ize the data
stream. This clock can only be used for Manchester and Bi-phase coded signals.

Generation of the data clock:
After a successfu l bit ch eck, the re ceiv er sw itche s from po llin g mode to rec eiving mod e

and the data stream i s ava ilable a t Pin DATA. In rece iving m ode, the dat a clock contro l
logic (Manchester/Bi-phase demodulator) is active and examines the incoming data
stream. This is done, like in the bit check, by subsequent time frame checks where the
distance between two edges is continuously compared to a programmable time window.
As illustrated in Figure 22, only two distances between two edges in Manchester and Bi­phase coded signals are valid (T and 2T).

The limits for T are the same as us ed fo r the bi t che ck. T he y can be pr ogrammed in the
LIMIT-register (Lim_min and Lim_max, see Table 11 and Table 12).

The limits for 2T are calculated as follows:
Lower limit of 2T: Lim_min_2T = (Lim_min + Lim_max) - (Lim_max - Lim_min)/2
Upper limit of 2T: Lim_max_2T= (Lim_min + Lim_max) + (Lim_max - Lim_min)/2
(If the result for “Lim_min_2T” or “Lim_max_2T” is not an integer value, it will be round

up.)

18

T5743

4569A–RKE–12/02

The data clock is available, after the data clock control logic has detected the distance
2T (Start bit) and is issued with the delay t

22).
If the data clock control logic detects a ti ming or logical er ror (Manchester code viola-

tion), like illustrated in Figure 23 and Figure 24, it stops the output of the data clock. The
receiver remains in receiving mode and starts with the bit check. If the bit check was
successful and the start bit has been detected, the data clock control logic starts again
with the generation of the data clock (see Figure 25).

It is recommended to use the function of the data clock only in conjunction with the bit
check 3, 6 or 9. If the bit check is set to 0 or the receiver is set to receiving mode via the
Pin POLLING/_ON, the data clock is available if the data clock control logic has
detected the distance 2T (Start bit).

Note that for Bi-phase-coded signals, the data clock is issued at the end of the bit.

Figure 22. Timing Diagram of the Data Clock

Bit check ok

after the edge on Pin DATA (see figure

Delay

Preburst Data

T2T

T5743

'1' '1' '1' '1' '1' '0' '1' '1' '0' '1' '0'

Dem_out

Data_out (DATA)

DATA_CLK

Bit-check mode

Figure 23. Data Clock Disappears Because of a Timing Error

Timing error

'1' '1' '1' '1' '1' '0' '1' '1' '0' '1' '0'

Dem_out

Data_out (DATA)

(Tee < T

T

ee

Lim_min

OR T

Lim_max

Start bit

Data

<Tee< T

t

Lim_max_2T

Delay

)

Receiving mode,
data clock control logic active

OR Tee > T

Lim_min_2T

t

P_Data_Clk

4569A–RKE–12/02

DATA_CLK

Receiving mode,
data clock control
logic active

Receiving mode,
bit check active

19

Figure 24. Data Clock Disappears Because of a Logical Error

'1' '1' '1' '0' '1' '1' '?' '0' '0' '1' '0'

Dem_out

Data_out (DATA)

DATA_CLK

Receiving mode,
data clock control
logic active

Figure 25. Output of the Data Clock After a Successful Bit Check

Bit check ok

'1' '1' '1' '1' '1' '0' '1' '1' '0' '1' '0'

Data

Logical error (Manchester code violation)

Receiving mode,
bit check aktive

Data

Dem_out

Data_out (DATA)

DATA_CLK

Receiving mode,
bit check active

Start bit

Receiving mode,
data clock control
logic active

The delay of the data clock is calculated as follows:
t

= t

Delay

t

is the delay between the internal signals Data_Out and Data_In. For the rising

Delay1

edge, t
resistor R

+ t

Delay1

Delay1

Delay2

depends on the cap acitive loa d CL at Pin DATA and the external pull-up
. For the falling edge, t

pup

depends additionally on the external voltage V

Delay1

(see Figure 26, Figure 27 and Figure 34). When the level of Data_In is equal to the level
of Data_Out, the data clock is issued after an additional delay t

Delay2

.

Note that the capacitive load at Pin DATA is limited. If the maximum tolerated capacitive
load at Pin DATA is exceeded, the data clock disappears (see section “Data Interface”).

X

20

T5743

4569A–RKE–12/02

T5743

Figure 26. Timing Characteristic of the Data Clock (Rising Edge on Pin DATA)

Data_Out

Serial bi-directional
data line

Data_In

DATA_CLK

V

V

= 0,65 * V

Ih

= 0,35 * V

Il

V

X

S

S

t

t

Delay1

Delay2

t

t

P_Data_Clk

Delay

Figure 27. Timing Characteristic of the Data Clock (Falling Edge of the Pin DATA)

Data_Out

V

X

V

= 0,65 * V S

Serial bi-directional
data line

Data_In

DATA_CLK

t

Delay1

t

Delay

t

Delay2

t

P_Data_Clk

Ih

VIl = 0,35 * V S

Digital Noise
Suppression

Automatic Noise Suppression
(see Figure 29)

After a data transmission, digital noise appears on the data output (see Figure 28). To
prevent that digital noise keeps the connected microcontroller busy, it can be sup­pressed in two different ways.

If the bit Noise_Disable (Table 10) in the OPMODE register is set to 1 (default), the
receiver changes to bit-check mode at the end of a valid data stream. The digital noise
is suppressed and the level at Pin DATA is High in that case. The receiver changes
back to receiving mode, if the bit check was successful.

This way to suppress the n oi se is re co mme nde d if the d a ta str ea m is Ma nc hes ter or B i­phase coded and is active after power on.

Figure 30 illustrates the behavior of the data output at the end of a data stream. Note
that if the last period of the data stream is a high period (rising edge to falling edge), a
pulse occurs on Pin DATA . The len gth of the pulse d epends on the sele cted ba ud-rat e
range.

4569A–RKE–12/02

21

Figure 28. Output of Digital Noise at the End of the Data Stream

< T

OR tee> T

Lim_max_2T

)

Bit check ok

Bit check ok

Preburst Data Digital Noise Preburst Data Digital NoiseDigital Noise

Data_out (DATA)

Data_out (DATA)

DATA_CLK

DATA_CLK

Bit-check

Bit-check

mode

mode

Preburst Data Digital Noise Preburst Data Digital NoiseDigital Noise

Receiving mode,

Receiving mode,

data clock control

data clock control

logic active

logic active

Receiving mode,

Receiving mode,

bit check aktive

bit check aktive

Figure 29. Automatic Noise Suppression

Bit check ok Bit check ok

Bit check ok

Bit check ok

Receiving mode,

Receiving mode,

data clock control

data clock control

logic active

logic active

Receiving mode,

Receiving mode,

bit check aktive

bit check aktive

Data_out (DATA)

DATA_CLK

Bit-check
mode

Preburst Data Preburst Data

Receiving mode,
data clock control
logic active

Bit-check
mode

Figure 30. Occurence of a Pulse at the End of the Data Stream

OR T

Lim_min

Lim_max

Dem_out

Data_out (DATA)

DATA_CLK

Timing error

Data stream Digital noise

'1' '1' '1'

data clock control
logic active

(tee < T

T

ee

Receiving mode,
data clock control
logic active

Lim_min_2T

< t

ee

T

Pulse

Bit-check modeReceiving mode,

Bit-check
mode

Controlled Noise Suppression
by the Microcontroller (see
Figure 31)

22

T5743

If the bit Noise_Disable (se e Table 10) in the OPMODE register is set to 0, digit al no ise
appears at the end of a valid data stream. To suppress the noise, the Pin POLL­ING/_ON must be set to Low . The rece iver rema ins in re ceiving mode. The n, the OFF­command causes the chang e to the star t-up mode. The programmed s leep time (see
Table 8) will not be exec uted b ecause the le vel a t Pin POL LING/_ON is low, but the bit
check is active in that case. The OFF-command activates the bit check also if the Pin
POLLING/_ON is held to Low. The receive r changes back to rece iving mode if the b it
check was succes sf ul. To ac tiv at e the pol li ng m ode at th e en d of the data transmissio n,
the Pin POLLING/_ON must be set to High.

This way to suppress the noise is recommended if the data stream is not Manchester or
Bi-phase coded.

4569A–RKE–12/02

Figure 31. Controlled Noise Suppression

T5743

Bit check ok Bit check ok

Serial bi-directional
data line

(DATA_CLK)

POLLING/_ON

Bit-check
mode

Configuration of the
Receiver

OFF-command

Preburst Data Digital Noise Preburst Data Digital Noise

Receiving mode

Start-up
mode

Bit-check
mode

Receiving mode

Sleep
mode

The T5743 receiver is configured via two 12-bit RAM registers called OPMODE and
LIMIT. The registers can be programmed by means of the bidirectional DATA port. If the
register contents have ch anged due to a voltage drop, this conditi on is indicated by a
certain output patter n cal le d res et m ar ker ( RM). T he rec eiv er m us t be r eprog ra mme d i n
that case. After a power-on reset (POR), the registers are set to default mode. If the
receiver is operated in defau lt mode , there is no need to program the regi sters. Ta ble 4
shows the structure of the reg isters. Ac cordin g to Table 2 bit 1 defin es if the receiv er is
set back to polling mode via the OFF-command (see section “Receiving Mode”) or if it is
programmed. Bit 2 rep re se nts the regi ste r add ress . It se le cts th e ap pr opri ate re gi ste r to
be programmed. To get a high programming reliability, Bit15 (Stop bit), at the end of the
programming operation, must be set to 0.

Table 2. Effect of Bit 1 and Bit 2 on Programming the Registers

Bit 1 Bit 2 Action

1 x The receiver is set back to polling mode (OFF command)
0 1 The OPMODE register is programmed
0 0 The LIMIT register is programmed

4569A–RKE–12/02

Table 3. Effect of Bit 15 on Programming the Register

Bit 15 Action

0 The values will be written into the register (OPMODE or LIMIT)
1 The values will not be written into the register

23

Table 4. Effect of the Configuration Words Within the Registers

Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8 Bit 9 Bit 10 Bit 11 Bit 12 Bit 13 Bit 14 Bit 15

OFF-command

1

OPMODE register

01

Default values

of Bit 3...14

00

Default values

of Bit 3...14

BR_Range N

Baud1 Baud0 BitChk1 BitChk0

00010001100 1

Lim_
min5

01010110100 1

Lim_
min4

Bit-check

Lim_min Lim_max

Lim_
min3

Lim_
min2

Modu-

lation

ASK/_

FSK

Lim_
min1

Sleep

Sleep4 Sleep3 Sleep2 Sl eep1 Sleep0 X

LIMIT register

Lim_
min0

Lim_

max5

Lim_

max4

Lim_

max3

Lim_

max2

X

Sleep

SleepStd

Lim_

max1

Noise

Suppression

Noise_

Disable

Lim_max0

Table 5 to Table 12 illustrate the effect of the individual configuration words. The default
configuration is highlighted for each word.

BR_Range sets the appropr iate baud-r ate range and simulta neously defi nes XLim .
XLim is used to define the bit-check limits T

Lim_min

and T

as shown in table 11 and

Lim_max

table 12.

Table 5. Effect of the Configuration Word BR_Range

BR_Range

Baud-Rate Range/E xtension Fact or for Bit-Ch eck Limits (XLim)Baud1 Baud0

0

0

00

01

10

11

BR_Range0 (application USA/Europe: BR_Range0 = 1.0 kBaud to

1.8 kBaud) XLim = 8 (default)
BR_Range1 (application USA/Europe: BR_Range1 = 1.8 kBaud to

3.2 kBaud) XLim = 4
BR_Range2 (application USA/Europe: BR_Range2 = 3.2 kBaud to

5.6 kBaud) XLim = 2
BR_Range3 (application USA/Europe: BR_Range3 = 5.6 kBaud to

10 kBaud) XLim = 1

Table 6. Effect of the Configuration Word N

N

Bit-check

00 0
0 1 3 (default)
10 6
11 9

Bit-check

Number of Bits to be CheckedBitChk1 BitChk0

24

T5743

4569A–RKE–12/02

Table 7. Effect of the Configuration Bit Modulation

Modulation Selected Modulation

ASK/_FSK

0 FSK (defaul t)
1 ASK

Table 8. Effect of the Configuration Word Sleep

Sleep

00000

00001

00010 2
00011 3

... ... ... ... ... ...

Start Value for Sleep Counter

(T

= Sleep × Xsleep × 1024 × T

Sleep

0 (Receiv e r is continuously polling until a

valid signal occurs )

1 (T

» 2 ms for XSleep = 1 in US-/

Sleep

European applications)

T5743

)Sleep4 Sleep3 Sleep2 Sleep1 Sleep0

Clk

00110

6 (USA: T

T

Sleep

= 12.52 ms, Europe:

Sleep

= 12.72 ms) (defau lt)

... ... ... ... ... ...

11101 29
11110 30
11111 31 (Permanent sleep mode)

Table 9. Effect of the Configuration Bit XSleep

XSleep

Std

0 1 (default)
18

Extension Factor for Sleep Time

= Sleep × Xsleep × 1024 × T

(T

Sleep

Clk

)XSleep

Table 10. Effect of the Configuration Bit Noise Suppression

Noise Suppression

Suppression of the Digital Noise at Pin DATANoise_Disable

0 Noise suppression is inactive
1 Noise suppression is active (default)

4569A–RKE–12/02

25

Table 11. Effect of the Configuration Word Lim_min

Lim_min

(1)

(Lim_min < 10 Is Not Applicable) Lower Limit Value for Bit Check

Lim_min5 Lim_min4 Lim_min3 Lim_min2 Lim_min1 Lim_min0 (T

= Lim_min × Lim × T

Lim_min

001010 10
001011 11
001100 12

... ... ... ... ... ...

010101

USA: T

Lim_min

21 (default)

= 342 µs, Europe: T

... ... ... ... ... ...

111101 61
111110 62
111111 63

Note: 1. Lim_min is also be used to determine the margins of the data clock control logic (see section “Data Clock”).

Table 12. Effect of the Configuration Word Lim_max

Lim_max

Lim_max5 Lim_max4 Lim_max3 Lim_max2 Lim_max1 Lim_max0 (T

001100 12
001101 13

(1)

(Lim_max < 12 Is Not Applicable) Upper Limit Value for Bit Check

= (Lim_max - 1) × XLim × T

Lim_max

Lim_min

)

Clk

= 348 µs)

)

Clk

001110 14

... ... ... ... ... ...

41 (default)

101001

USA: T

Europe: T

Lim_max

Lim_max

= 652 ms,

= 662 µs)

... ... ... ... ... ...

111101 61
111110 62
111111 63

Note: 1. Lim_max is also be used to determine the margins of the data clock control logic (see section “Data Clock”).

Conservation of the Register
Information

The T5743 implies an integrated power-on reset and brown-out detection circuitry to
provide a mechanism to preserve the RAM register information.

According to Figure 32, a power-on reset (POR) is gen erated if the supply vo ltage V
drops below the threshold voltage V
the configuration registers in that condition. Once V
celled after the minimum reset period t

. The default parameters are programmed into

ThReset

. A POR is also generated when the supply

Rst

exceeds V

S

the POR is can-

ThReset

voltage of the receiver is turned on.
To indicate that condition, the receiver displays a reset marker (RM) at Pin DATA after a

reset. The RM is represented by the fixed frequency f

at a 50% duty-cyc le. RM can be

RM

cancelled via a Low pulse t1 at Pin DATA.

S

26

T5743

4569A–RKE–12/02

The RM implies the following characteristics:

•f

is lower than the lowest feasible frequency of a data signal. By this means, RM

RM

cannot be misinterpreted by the connected microcontroller.

• If the receiver is set back to polling mode via Pin DATA, RM cannot be cancelled by

accident if t1 is applied according to the proposal in the section “Programming the
Configuration Registers”.

By means of t hat mechan ism the receiv er cannot lose i ts regis ter infor mation without
communicating that condition via the reset marker RM.

Figure 32. Generation of the Power-on Reset

V

S

POR

t

Rst

Data_out (DATA)

X

V

ThReset

1 / f

T5743

RM

Programming the Configuration Register
Figure 33. Timing of the Register Programming

IC_ACTIVE

t1 t2 t3t4t5

Out1 (µC)

Data_out (DATA)

Serial bi-directional
data line

X

X

Receiving
mode

(Start bit)

Bit 1
("0")

t6

t7

Bit 2
("1")

(Register­ select)

Programming frame

Bit 14
("0")

(Poll8) (Stop bit)

Bit 15
("0")

t9

t8

T

Sleep
mode

SleepTStart-up

Start-up
mode

4569A–RKE–12/02

27

Figure 34. Data Interface

VS= 4.5 V to 5.5 V

Data_In

Data_out

VS= 4.5 V to 5.5 V

Data_In

Data_out

Input ­Interface

VX= 5 V to 20 V

T5743 Microcontroller

Input -
Interface

T5743 Microcontroller

R

0 ... 20 V0 V / 5 V

DATA

0 ... 20 V0 V / 5 V

I

D

DATA

Serial bi-directional data line

I

D

C

VX= 5 V to 20 V

pup

R

Serial bi-directional data line

L

C

pup

I/O

L

I/O

Out1 mîcrocontroller

Out1 mîcrocontroller

The configuration registers are programmed serially via the bi-directional data line
according to Figure 33 and Figure 34.

To start programming, the serial data line DATA is pulled to Low for the time period t1 by
the microcontroller. When DATA has been released, the receiver becomes the master
device. When the programming delay period t2 has elapsed, it emits 15 subsequent
synchronization pulses with the pulse length t3. After each of these pulses, a program­ming window occurs. The delay until the program window starts is determined by t4, the
duration is defined by t5. Within the programming window, the individual bits are set. If
the microcon trolle r pulls down P in DATA f or the ti me per iod t7 du ring t5 , the acco rdin g
bit is set to “0”. If no pr ogram ming p ulse t7 i s is sued, th is bi t is se t to “ 1”. A ll 15 bi ts are
subsequently programmed this way. The time frame to program a bit is defined by t6.

Bit 15 is followed by the equivalent time window t9. During this window, the equivalence
acknowledge pulse t8 (E_Ack) occurs if the just programmed mode word is equivalent to
the mode word that was already stored in that register. E_Ack should be used to verify
that the mode word was correctly transferred to the register. The register must be pro­grammed twice in that case.

Programming of a register is possible both in sleep- and in active-mode of the receiver.
During programming, the LNA, LO, lowpass filter IF- amplifier and the FSK/A SK

Manchester demodulat or are disabled.
The programming start pulse t1 initi ates the pr ogrammi ng of the config uration re gisters .

If bit 1 is set to “1”, it represents the OFF-command to set the receiver back to polling
mode at the same time. For the length of the programming start pulse t1, the following
convention should be considered:

• t1(min) < t1 < 5632 ´ T

: t1(min) is the minimum specified value for the relevant

Clk

BR_Range

Programming respectively OFF-command is initiated if the receiver is not in reset
mode.If the receiver is in reset mode, programming respectively Off-command is not ini­tiated and the reset marker RM is still present at Pin DATA.

This period is generally used to switch the receiver to polling mode or to start the pro­gramming of a register. In reset condition, RM is not cancelled by accident.

• t1 > 7936 ´ T

Clk

28

T5743

4569A–RKE–12/02

T5743

Programming respectively OF F-command is initiated in any case. The registers
OPMODE and LIMIT are set to the default values. RM is cancelled if present.

This period is used if the connected microcontroller detected RM. If the receiver oper­ates in default mode, this time period for t1 can generally be used.

Note that the capacitive load at Pin DATA is limited.

Data Interface The data interface (see Figure 34) is desig ned for automotive requirements. It c an be

connected via the pull-up resistor R
The applicable pull-up resistor R

the selected BR _rang e (see Tab le 13). More det ailed in forma tion abou t the cal culati on
of the maximum load capacity at Pin DATA is given in the “Application Hints U3743BM”.

up to 20 V and is short-circuit-protected.

pup

depends on the load capacity CL at Pin DATA and

pup

Table 13. Applicable R

pup

CL £ 1 nF

CL £ 100 pF

Figure 35. Application Circuit: fRF = 433.92 MHz without SAW Filter

VS

C7

GND

2.2u
10%

C6
10n
10%

15p
5%
np0

1

SENS

33n 5%

C15
150p
10%

2
3

4
5
6

7
8

9
10

IC_ACTIVE
CDEM

AVCC
TEST
AGND

MIXVCC
LNAGND

LNA_IN
NC

C14

C13
10n
10%

C3

56k to 150k

T5743

POLLING/_ON

DATA_CLK

C12

R2

10n
10%

DATA
DGND
MODE
DVCC

XTO
LFGND
LFVCC

20
19
18
17
16

15
14
13

12

LF

11

BR_range Applicable R

B0 1.6 k

W to 47 kW

B1 1.6 kW to 22 kW
B2 1.6 kW to 12 kW
B3 1.6 kW to 5.6 kW
B0 1.6 k

W to 470 kW

B1 1.6 kW to 220 kW
B2 1.6 kW to 120 kW
B3 1.6 kW to 56 kW

IC_ACTIVE
Sensitivity reduction

DATA
POLLING/_ON

DATA_CLK

Q1

6.7643MHz

C11

12p

2%

C8
150p
10%

np0

R3

>= 1.6k

VX = 5 V to 20 V

pup

COAX

4569A–RKE–12/02

C17

3.3p
5%

np0

L2 TOKO LL2012 F22NJ
22n
5%

C16

100p
5%

np0

R1
820
5%

C9

4.7n
5%

C10
1n
5%

29

Figure 36. Application Circuit: fRF = 315 MHz without SAW Filter

VS

C7

C6

2.2u

10n

10%

10%

GND

COAX

C17

3.3p
5%

np0 np0

Figure 37. Application Circuit: f

R2

56k to 150K

1

33n 5%

C15
150p
10%

100p
5%

2
3

4
5
6

7
8

9
10

C14

C13
10n
10%

C3

33p
5%
np0

C16

L2 TOKO LL2012 F39NJ
39n
5%

= 433.92 MHz with SAW Filter

RF

T5743

SENS
IC_ACTIVE
CDEM

AVCC
TEST
AGND

MIXVCC
LNAGND

LNA_IN
NC

DATA

POLLING/_ON

DGND

DATA_CLK

MODE
DVCC

LFGND

LFVCC

C12

10n
10%

XTO

IC_ACTIVE

= 5 V to 20 V

Sensitivity reduction

DATA
POLLING/_ON

DATA_CLK

V

X

R3

>= 1.6k

20
19
18
17
16

15
14
13

12

LF

11

Q1

4.906MHz

R1
820
5%

C9

4.7n
5%

C11

15p
2%

C8
150p
10%

C10
1n
5%

np0

VS

GND

COAX

C7

2.2u
10%

L2 TOKO LL2012
F33NJ

33n
5%

C2

8.2p
5%
np0

C6
10n
10%

1
2

3
4

C14

33n 5%

C13
10n
10%

C3

22p
5%

np0

IN
IN_GND

CASE_GND

B3555

C15
150p
10%

1
2
3

4
5
6

7
8

9
10

C16

100p
5%

np0

OUT

OUT_GND

CASE_GND

56k to 150k

T5743

SENS
IC_ACTIVE

POLLING/_ON

CDEM
AVCC

TEST
AGND

MIXVCC
LNAGND

LNA_IN
NC

C12

C17

8,2p

np0

5%

L3 TOKO LL2012
F27 NJ
27n
5%

5
6

7
8

R2

DATA

DGND

DATA_CLK

MODE

DVCC

XTO

LFGND

LFVCC

10n
10%

IC_ACTIVE
Sensitivity reduction

= 5 V to 20 V

V

R3

C11

2%

C10
1n
5%

12p

np0

C8

150p
10%

>= 1.6k

20
19
18
17
16

15
14
13

12

LF

11

Q1

6.7643MHz

R1
820
5%

C9

4.7n
5%

X

DATA
POLLING/_ON

DATA_CLK

30

T5743

4569A–RKE–12/02

Figure 38. Application Circuit: fRF = 315 MHz with SAW Filter

T5743

VS

GND

COAX

C7

2.2u
10%

L2 TOKO LL2012
F82NJ

82n
5%

C2
10p
5%

np0

C6
10n
10%

1
2

3
4

C14

33n 5%

C13
10n
10%

C3

47p
5%

np0

IN
IN_GND

CASE_GND
B3551

C15

150p
10%

1
2
3

4
5
6

7
8

9
10

C16

100p
5%

np0

OUT

OUT_GND

CASE_GND

56k to 150k

T5743

SENS
IC_ACTIVE
CDEM

AVCC
TEST
AGND

MIXVCC
LNAGND

LNA_IN
NC

POLLING/_ON

C17

22p

np0

5%

L3 TOKO LL2012
F47NJ
47n
5%

5
6

7
8

R2

DATA

DGND

DATA_CLK

MODE

DVCC

XTO

LFGND

LFVCC

C12

10n
10%

IC_ACTIVE

VX = 5 V to 20 V

R3

C11

2%

C10
1n
5%

15p

np0

C8
150p

10%

>= 1.6k

20
19
18
17
16

15
14
13

12

LF

11

Q1

4.906MHz

R1
820
5%

C9

4.7n
5%

Sensitivity reduction

DATA
POLLING/_ON

DATA_CLK

Absolute Maximum Ratings

Parameters Symbol Min. Max. Unit

Supply voltage V
Power dissipation P
Junction tem p erature T
Storage temperature T
Ambient temperature T
Maximum input level, input ma tch ed to 50

W P

in_max

tot

stg

amb

S

j

-55 +125 °C

-40 +105 °C

6V

1000 mW

150 °C

10 dBm

Thermal Resistance

Parameters Symbol Value Unit

Junction ambient R

thJA

100 K/W

4569A–RKE–12/02

31

Electrical Characteristics

All parameters refer to GND, T
(For typical values: V

Parameter Test Conditions Symbol
Basic Clock Cycle of the Digital Circuitry

Basic clo ck
cycle

Extended basic
clock cycle

Polling Mode

Sleep time (see
Figure 10,
Figure 19, and
Figure 33)

Start-up time
(see Figure 10,
and Figure 11)

= 5 V, T

S

MODE = 0 (USA)
MODE = 1 (Europe)

BR_Range0
BR_Range1
BR_Range2
BR_Range3

Sleep and XSleep
are defined in the
OPMODE register

BR_Range0
BR_Range1
BR_Range2
BR_Range3

= -40°C to +105°C, VS = 4.5 V to 5.5 V, f0 = 433.92 MHz and f0= 315 MHz, unless otherwise spe cified .

amb

= 25°C)

amb

T

Clk

T

XClk

T

Sleep

T

Startup

6.76438 MHz Osc.
(MODE: 1)

2.0697 2.0697

16.6

8.3

4.1

2.1

Sleep ´

´

X

Sleep

1024 ´

2.0697
1855

1061
1061

663

16.6

8.3

4.1

2.1

Sleep ´
X

Sleep

1024 ´

2.0697
1855

1061
1061

663

4.90625 MHz Osc.
(MODE: 0) Variable Oscillator

2.0383 2.0383

16.3

8.2

4.1

2.0

Sleep ´

´

X

´

Sleep

1024 ´

2.0383
1827

1045
1045

653

16.3

8.2

4.1

2.0

Sleep ´
X

´

Sleep

1024 ´

2.0383
1827

1045
1045

653

1/f

XTO

1/f

XTO

8 ´ T
4 ´ T
2 ´ T
1 ´ T

Sleep ´
X

Sleep

1024 ´ T

896.5

512.5

512.5

320.5 ´ T

/10
/14

Clk
Clk
Clk
Clk

´

Clk

Clk

1/f

XTO

1/f

XTO

8 ´ T
4 ´ T
2 ´ T
1 ´ T

Sleep ´
X

Sleep

1024 ´ T

896.5

512.5

512.5

320.5 ´
T

Clk

/10
/14

Clk
Clk
Clk
Clk

´

UnitMin. Typ. Max. Min. Typ. Max. Min. Typ. Max.

µs
µs

µs
µs
µs
µs

ms

Clk

µs
µs
µs
µs

Time for bit
check (see
Figure 10)

Receiving Mode

Intermediate
frequency

Baud-rate
range

Minimum time
period between
edges at Pin
DATA
(see Figure 7,
Figure 17 and
Figure 18, with
the exception of
parameter

)

T

Pulse

Average bit-check
time while polling,
no RF applied
(see Figure 14, and
Figure 15)
BR_Range0
BR_Range1
BR_Range2
BR_Range3

Bit-check time for a
valid input signal f

Sig ,

(see Figure 11)
N

= 0

Bit-check

= 3

N

Bit-check

N

= 6

Bit-check

= 9

N

Bit-check

MODE = 0 (USA)
MODE = 1 (Europe)

BR_Range0
BR_Range1
BR_Range2
BR_Range3

BR_Range =

BR_Range0
BR_Range1
BR_Range2
BR_Range3

T

Bit-check

T

Bit-check

BR_Range

t

DATA-min

0.45

0.24

0.14

0.08

3/f

Sig

6/f

Sig

9/f

Sig

f

IF

1.0

1.8

3.2

5.6

165

83

41.4

20.7

3.5/f

6.5/f

9.5/f

Sig
Sig
Sig

3/f
6/f
9/f

1.0 1.0

1.8

3.2

5.6

10.0

165

163

83

41.4

20.7

40.7

20.4

1.0

1.8

3.2

5.6

81

Sig
Sig
Sig

0.45

0.24

0.14

0.08

3.5/f

6.5/f

9.5/f

1.8

3.2

5.6

10.0

163

40.7

20.4

81

Sig
Sig
Sig

1 X T

XClk

3/f

Sig

6/f

Sig

9/f

Sig

f

´ 64/314

XTO

´ 64/432.92

f

XTO

BR_Range0 ´ 2 ms/T
BR_Range1 ´ 2 ms/T
BR_Range2 ´ 2 ms/T
BR_Range3 ´ 2 ms/T

10 ´ T

XClk

10 ´ T

XClk

10 ´ T

XClk

10 ´ T

XClk

1 ´ T

3.5/f

6.5/f

9.5/f

Clk
Clk
Clk
Clk

10 ´ T
10 ´ T
10 ´ T
10 ´ T

Clk
Sig
Sig
Sig

XClk

XClk

XClk

XClk

ms
ms
ms
ms

ms
ms
ms
ms

MHz
MHz

kBaud
kBaud
kBaud
kBaud

µs
µs
µs
µs

32

T5743

4569A–RKE–12/02

Electrical Characteristics (Continued)

All parameters refer to GND, T
(For typical values: V

Parameter Test Conditions Symbol

Maximum Low
period at Pin
DATA (see
Figure 7 and
Figure 18)

Delay to
activate the
start-up mode
(see Figure 21)

OFF- command
at Pin
POLLING/_ON
(see Figure 20)

Delay to
activate the
sleep mode
(see Figure 20)

Pulse on Pin
DA TA at the end
of a data
stream (see
Figure 30)

Configuration of the Receiver

Frequency of
the reset
marker

Programming
start pulse (see
Figure 19 and
Figure 33)

Programming
delay period

Synchroni­zation pulse

Delay until of
the program
window starts

Programming
window

Time frame
of a bit
(see Figure 33)

Programming
pulse (see
Figure 19 and
Figure 33)

= 5 V, T

S

BR_Range =

BR_Range0
BR_Range1
BR_Range2
BR_Range3

BR_Range =

BR_Range0
BR_Range1
BR_Range2
BR_Range3

(see Figure 31)

BR_Range =

BR_Range0
BR_Range1
BR_Range2
BR_Range3
after POR

(see Figure 19 and
Figure 33)

= -40°C to +105°C, VS = 4.5 V to 5.5 V, f0 = 433.92 MHz and f0= 315 MHz, unless otherwise spe cified .

amb

= 25°C)

amb

6.76438 MHz Osc.
(MODE: 1)

t

DATA_L_max

2152
1076

538
270

Ton1 19.7 21.8 19.4 21. 5 9.5 ´ T

Ton2 16.6 16.4 8 ´ T

Ton3 17.6 19.7 17.4 19. 4 8.5 ´ T

T

Pulse

16.6

8.3

4.1

2.1

f

RM

117.9 117.9 119.8 119.8 Hz

3367
2277

t1

1735
1464

16.43

t2 795 798 783 786 384.5 ´ T

t3 265 265 261 261 128 ´ T

t4 131 131 129 129 63.5 ´ T

t5 530 530 522 522 256 ´ T

t6 1060 1060 1044 1044 512 ´ T

t7 132 529 130 521 64 ´ T

2152
1076

538
270

16.6

8.3

4.1

2.1

11650
11650
11650
11650

4.90625 MHz Osc.
(MODE: 0) Variable Oscillator

2120
1060

530
265

16.3

8.2

4.1

2.0

3311
2243
1709
1442

16.18

2120
1060

530
265

16.3

8.2

4.1

2.0

11470
11470
11470
11470

130 ´ T

XClk

130 ´ T

XClk

130 ´ T

XClk

130 ´ T

XClk

Clk

8 ´ T

Clk

4 ´ T

Clk

2 ´ T

Clk

1 ´ T

Clk

1

-------------------------------

4096 T

´

1624 ´ T

1100´ T

838 ´ T
707 ´ T

7936 ´ T

Clk

Clk

Clk

Clk

Clk
Clk
Clk

Clk

Clk

Clk

Clk

Clk

Clk

Clk

T5743

130 ´ T

XClk

130 ´ T

XClk

130 ´ T

XClk

130 ´ T

XClk

10.5 ´ T

9.5 ´ T

8 ´ T

Clk

4 ´ T

Clk

2 ´ T

Clk

1 ´ T

Clk

1

-------------------------------

4096 T

´

Clk

5632 ´ T
5632 ´ T
5632 ´ T
5632 ´ T

385.5 ´
T

Clk

128 ´ T

63.5 ´ T

256 ´ T

512 ´ T

256 ´ T

Clk

Clk

Clk

Clk

Clk

Clk

Clk

Clk
Clk
Clk
Clk

UnitMin. Typ. Max. Min. Typ. Max. Min. Typ. Max.

µs
µs
µs
µs

µs

µs

µs

µs
µs
µs
µs

µs
µs
µs
µs
µs

µs

µs

µs

µs

µs

µs

4569A–RKE–12/02

33

Electrical Characteristics (Continued)

All parameters refer to GND, T
(For typical values: V

Parameter Test Conditions Symbol

Equivalent
acknowledge
pulse: E_Ack
(see Figure 33)

Equivalent time
window (see
Figure 33)

OFF-bit
programming
window (see
Figure 19)

Data Clock

Minimum delay
time between
edge at DATA
and DATA_CLK
(see Figure 26
and Figure 27)

Pulswidth of
negative pulse
at Pin
DATA_CLK
(see Figure 26
and Figure 27)

= 5 V, T

S

BR_Range =

BR_Range0
BR_Range1
BR_Range2
BR_Range3

BR_Range =

BR_Range0
BR_Range1
BR_Range2
BR_Range3

= -40°C to +105°C, VS = 4.5 V to 5.5 V, f0 = 433.92 MHz and f0= 315 MHz, unless otherwise spe cified .

amb

= 25°C)

amb

6.76438 MHz Osc.
(MODE: 1)

t8 265 265 261 261 128 ´ T

t9 534 534 526 526 258 ´ T

t10 930 930 916 916 449.5 ´ T

0

t

Delay2

t

P_DATA_CLK

0
0
0

66.2

33.1

16.56

8.3

16.6

8.3

4.15

2.07

66.2

33.1

16.56

8.3

4.90625 MHz Osc.
(MODE: 0) Variable Oscillator

Clk

Clk

Clk

0
0
0
0

65.2

32.6

16.3

8.2

16.3

8.2

4.08

2.04

65.2

32.6

16.3

8.2

4 ´ T
4 ´ T
4 ´ T
4 ´ T

0
0
0
0

XClk
XClk
XClk
XClk

128 ´ T

258 ´ T

449.5 ´ T

1 ´ T
1 ´ T
1 ´ T
1 ´ T

4 ´ T
4 ´ T
4 ´ T
4 ´ T

XClk
XClk
XClk
XClk

XClk
XClk
XClk
XClk

Clk

Clk

Clk

UnitMin. Typ. Max. Min. Typ. Max. Min. Typ. Max.

µs

µs

µs

µs
µs
µs
µs

µs
µs
µs
µs

Electrical Characteristics (Continued)

All parameters refer to GND, T
(For typical values: V

= 5 V, T

S

Parameters Test Conditions Symbol Min. Typ. Max. Unit

Current consumptio n Sl eep mode

LNA Mixer (Input Matched According to Figure 6)

Third-order intercept point LNA/mixer/IF amplifier IIP3 -28 dBm
LO spurious emission at RF
Noise figure LNA and mixer (DSB) NF 7 dB
LNA_IN input impedance at 433.92 MHz

1 dB compression point (LN A, mix er ,
IF amplifier)

34

T5743

= -40°C to +105°C, VS = 4.5 V to 5.5 V, f0 = 433.92 MHz and f0 = 315 MHz, unless otherwise specified.

amb

= 25°C)

amb

(XTO and polling logic active)

IS

off

170 276 µA

IC active (start-up-, bit check-,
receiving mode) Pin DATA = H
FSK
ASK

In

Required according to I-ETS 300220 IS

at 315 MHz
Referred to RF

in

Zi

IP

IS

on

LORF

LNA_IN

1db

7.5

7.1

9.1

8.7

-73 -57 dBm

1.0 || 1.56

1.3 || 1.0

-40 dBm

4569A–RKE–12/02

mA
mA

kW || pF
kW || pF

T5743

Electrical Characteristics (Continued)

All parameters refer to GND, T
(For typical values: V

= 5 V, T

S

Parameters Test Conditions Symbol Min. Typ. Max. Unit

Maximum input level BER £ 10-3,

Local Oscillator

Operating frequency range VCO f
Phase noise VCO/LO f

Spurious of the VCO at ± f
VCO gain K
Loop bandwidth of the PLL For best LO noise (design

Capacitive load at Pin LF The capacitive load at Pin LF is

XTO o perating frequency XTO crystal frequency, appropriate

Series resonance resistor of the
crystal

Static capacitance at Pin XTO to
GND

Analog Signal Processing

Input sensitivity ASK
300 kHz IF-filter

= -40°C to +105°C, VS = 4.5 V to 5.5 V, f0 = 433.92 MHz and f0 = 315 MHz, unless otherwise specified.

amb

= 25°C)

amb

FSK mode
ASK mode

= 432.92 MHz

osc

at 1 MHz
at 10 MHz

XTO

P

in_max

VCO

299 449 MHz

L (fm) -93

-113

-55 -47 dBC

VCO

190 MH z/V

-22

-20

-90

-110

parameter)
R1 = 820

W

B

Loop

100 kHz
C9 = 4.7 nF
C10 = 1 nF

limited if bit check is used. The
limitation therefore also applies to

C

LF_tot

10 nF

self polling.

load capacitanc e must b e connected
to XTAL
f

= 6.764375 MHz (EU)

XTAL

= 4.90625 MHz (US)

f

XTAL

f

= 6.764 MHz,

XTO

f

= 4.906 MHz

XTO

f

XTO

R

C

-30 ppm f

S

0

XTAL

+30 ppm MHz

150
220

6.5 pF

Input matched according to
Figure 6
ASK (level of carrier)
BER

= 433.92 MHz/315 MHz

f

in

V

S

BR_Range0
BR_Range1
BR_Range2
BR_Range3

£ 10

= 5 V, T

-3

, BW = 300 kHz

= 25°C, fIF = 1 MHz

amb

P

Ref_ASK

-109

-107

-106

-104

-111

-109

-108

-106

-113

-111

-110

-108

dBm
dBm

dBC/Hz
dBC/Hz

dBm
dBm
dBm
dBm

W
W

4569A–RKE–12/02

35

Electrical Characteristics (Continued)

All parameters refer to GND, T
(For typical values: V

= 5 V, T

S

Parameters Test Conditions Symbol Min. Typ. Max. Unit

Input sensitivity ASK
600 kHz IF-filter

Sensitivity variation ASK for the full
operating range compared to

=25°C, VS=5V

T

amb

Sensitivity variation ASK for full
operating range including IF-filter
compared to T

=25°C, VS = 5 V,

amb

Input sensitivity FSK
300 kHz IF-filter

= -40°C to +105°C, VS = 4.5 V to 5.5 V, f0 = 433.92 MHz and f0 = 315 MHz, unless otherwise specified.

amb

= 25°C)

amb

Input matched according to
Figure 6
ASK (level of carrier)
BER
f

= 433.92 MHz/315 MHz

in

V

S

BR_Range0
BR_Range1
BR_Range2
BR_Range3

£ 10

= 5 V, T

-3

, BW = 600kHz

= 25°C, fIF = 1 MHz

amb

P

Ref_ASK

-108

-106.5

-106

-104

-110

-108.5

-108

-106

-112

-110.5

-110

-108

300 kHz and 600 kHz version

= 433.92 MHz/315 MHz

f

in

f

= 1 MHz, P

IF

ASK

= P

Ref_ASK

+ DP

Ref

DP

Ref

+2.5 -1.5 dB

300 kHz v e rsion

= 433.92 MHz/315 MHz

f

in

f

= 0.89 MHz to 1.11 MHz

IF

= 0.86 MHz to 1.14 MHz

f

IF

= P

P

ASK

Ref_ASK

+ DP

Ref

DP

Ref

+5.5
+7.5

-1.5

-1.5

600 kHz v e rsion
f

= 433.92 MHz/315 MHz

in

= 0.79 MHz to 1.21 MHz

f

IF

= 0.73 MHz to 1.27 MHz

f

IF

P

ASK

= P

Ref_ASK

+ DP

Ref

DP

Ref

+5.5
+7.5

-1.5

-1.5

Input matched according to
Figure 6
BER
f

= 433.92 MHz/315 MHz

in

V

S

= 1 MHz

f

IF

£ 10

= 5 V, T

-3

, BW = 300 kHz

= 25°C

amb

BR_Range0
df = ±16 kHz
df = ±10 kHz to ± 30 kHz

P

Ref_FSK

-101

-99

-104 -105.5

-105.5

BR_Range1
df = ±16 kHz
df = ±10 kHz to ± 30 kHz

P

Ref_FSK

-99

-97

-102 -103.5

-103.5

BR_Range2
df = ± 16 kHz
df = ±10 kHz to ± 30 kHz

P

Ref_FSK

-97.5

-95.5

-100.5 -102

-102

BR_Range3
df = ±16 kHz
df = ±10 kHz to ± 30 kHz

P

Ref_FSK

-95.5

-93.5

-98.5 -100

-100

dBm
dBm
dBm
dBm

dB
dB

dB
dB

dBm
dBm

dBm
dBm

dBm
dBm

dBm
dBm

36

T5743

4569A–RKE–12/02

T5743

Electrical Characteristics (Continued)

All parameters refer to GND, T
(For typical values: V

= 5 V, T

S

Parameters Test Conditions Symbol Min. Typ. Max. Unit

Input sensitivity FSK
600 kHz IF-filter

Sensitivity variation FSK for the full
operating range compared to

=25°C, VS = 5 V

T

amb

Sensitivity variation FSK for the full
operating range including IF-filter
compared to T

= 25°C, VS = 5 V

amb

S/N ratio to suppress inband noise
signals. Nois e sign als m ay have any
modulation scheme

Dynamic ran ge RSSI ampl. DR
Lower cut-off frequency of the data

filter

= -40°C to +105°C, VS = 4.5 V to 5.5 V, f0 = 433.92 MHz and f0 = 315 MHz, unless otherwise specified.

amb

= 25°C)

amb

Input matched according to
Figure 6
BER

= 433.92 MHz/315 MHz

f

in

V

S

f

= 1 MHz

IF

£ 10

= 5 V, T

-3

, BW = 600 kHz

= 25°C

amb

BR_Range0
df = ±16 kHz
df = ±10 kHz to ± 100 kHz

P

Ref_FSK

-101

-99

-104 -105.5

-105.5

BR_Range1
df = ±16 kHz
df = ±10 kHz to ± 100 kHz

P

Ref_FSK

-99

-97

-102 -103.5

-103.5

BR_Range2
df = ±16 kHz
df = ±10 kHz to ± 100 kHz

P

Ref_FSK

-97.5

-95.5

-100.5 -102

-102

BR_Range3
df = ±16 kHz
df = ±10 kHz to ± 100 kHz

P

Ref_FSK

-95.5

-93.5

-98.5 -100

-100

300 kHz and 600 kHz version
f

= 433.92 MHz/315 MHz

in

= 1 MHz

f

IF

P

FSK

= P

Ref_FSK

+ DP

Ref

DP

Ref

+3 -1.5 dB

300 kHz v e rsion
f

= 433.92 MHz/ 315 MHz

in

= 0.89 MHz to 1.11 MHz

f

IF

f

= 0.86 MHz to 1.14 MHz

IF

= 0.82 MHz to 1.18 MHz

f

IF

= P

P

FSK

Ref_FSK

+ DP

Ref

DP

Ref

+6
+8

+11

-2

-2

-2

600 kHz v e rsion
f

= 433.92 MHz/ 315 MHz

in

f

= 0.85 MHz to 1.15 MHz

IF

= 0.80 MHz to 1.20 MHz

f

IF

f

= 0.74 MHz to 1.26 MHz

IF

P

FSK

= P

Ref_FSK

+ DP

Ref

ASK mode
FSK mode

CDEM = 33 nF

f

cu_DF

--------------------------------------------------------- --=

2 p 30 kW CDEM´´´

1

DP

SNR
SNR

f

cu_DF

Ref

ASK
FSK

RSSI

+6
+8

+11

-2

-2

-2

12

3

60 dB

0.11 0.16 0.20 kHz

dBm
dBm

dBm
dBm

dBm
dBm

dBm
dBm

dB
dB
dB

dB
dB
dB

dB
dB

Recommended CDEM for best
performance

4569A–RKE–12/02

BR_Range0 (default)
BR_Range1
BR_Range2
BR_Range3

CDEM

39
22
12

8.2

nF
nF
nF
nF

37

Electrical Characteristics (Continued)

All parameters refer to GND, T
(For typical values: V

= 5 V, T

S

Parameters Test Conditions Symbol Min. Typ. Max. Unit

Edge-to-edge time period of the
input data signal for full sensitivity

Upper cut-off frequency data filter Upper cut-off frequency

Reduced sensitiv ity R

Reduced sensitivity variation over
full operating range

Reduced sensitivity variation for
different values of R

Sense

Threshold voltage for reset V

= -40°C to +105°C, VS = 4.5 V to 5.5 V, f0 = 433.92 MHz and f0 = 315 MHz, unless otherwise specified.

amb

= 25°C)

amb

BR_Range0 (default)
BR_Range1
BR_Range2
BR_Range3

t

ee_sig

270
156

89
50

1000

560
320
180

programmable in 4 ranges
via a serial mode word
BR_Range0 (default)
BR_Range1
BR_Range2
BR_Range3

connected from Pin Sens

Sense

to V

input matched according to

S,

2.8

f

u

4.8

8.0

15.0

3.4

6.0

10.0

19.0

4.0

7.2

12.0

23.0

Figure 6

= 56 kW, fin= 433.92 MHz,

R

Sense

at BW = 300 kHz
at BW = 600 kHz

= 100 kW, fin=433.92MHz,

R

Sense

at BW = 300 kHz
at BW = 600 kHz

= 56 kW, fin= 315 MHz,

R

Sense

at BW = 300 kHz
at BW = 600 kHz

= 100 kW, fin=315MHz,

R

Sense

at BW = 300 kHz
at BW = 600 kHz

= 56 kW

R

Sense

R

= 100 kW

Sense

P

= P

Red

V alues relative to R
R

= 56 kW

Sense

R

= 68 kW

Sense

R

= 82 kW

Sense

R

= 100 kW

Sense

R

= 120 kW

Sense

R

= 150 kW

Sense

P

= P

Red

Ref_Red

Ref_Red

+ DP

+ DP

Red

Sense

Red

= 56 kW

P

Ref_Red

DP

Red

DP

Red

DP

Red

DP

Red

DP

Red

DP

Red

DP

Red

ThRESET

-71

-67

-80

-76

-72

-68

-81

-77
5

6

-76

-72

-85

-81

-77

-73

-86

-82
0

0

-81

-77

-90

-86

-82

-78

-91

-87
0

0

0

-3.5

-6.0

-9.0

-11.0

-13.5

1.95 2.8 3.75 V

kHz
kHz
kHz
kHz

dBm

(peak

level)

dBm
dBm

dBm
dBm

dBm
dBm

dBm
dBm

dB
dB

dB
dB
dB
dB
dB
dB

µs
µs
µs
µs

38

T5743

4569A–RKE–12/02

T5743

Electrical Characteristics (Continued)

All parameters refer to GND, T
(For typical values: V

= 5 V, T

S

Parameters Test Conditions Symbol Min. Typ. Max. Unit
Digital Ports

Data output

- Saturation voltage Low

- max voltage at Pin DATA

- quiescent curren t

- short-circuit current

- ambient temperature in case of
permanent short-circuit

Data input

- Input voltage Low

- Input voltage High

DATA_CLK output

- Saturation voltage Low

- Saturation voltage High

IC_ACTIVE output

- Saturation voltage Low

- Saturation voltage High

POLLING/_ON input

- Low level input voltage

- High level input v o ltage

MODE input

- Low level input voltage

- High level input v o ltage

TEST input

- Low level input voltage

= -40°C to +105°C, VS = 4.5 V to 5.5 V, f0 = 433.92 MHz and f0 = 315 MHz, unless otherwise specified.

amb

= 25°C)

amb

£ 12 mA

I

ol

I

= 2 mA

ol

V

= 20 V

oh

= 0.8 V to 20 V

V

ol

= 0 V to 20 V

V

oh

IDATA_CLK = 1 mA
IDATA_CLK = -1 mA

IIC_ACTIV E = 1 mA
IIC_ACTIV E = -1 mA

Receiving mode
Polling mode

Division factor = 10
Division factor = 14

Test input must always be set to Low

V
V

V

oh

I

qu

I

ol_lim

t

amb_sc

V

V

ich

V

V

oh

V

V

oh

V

V

V

V

V

ol
ol

13

Il

ol

ol

Il

Ih

Il

Ih

Il

0.65

´ V

VS-0.4 V

VS-0.4 V

0.8 ´ V

0.8 ´ V

0.35

0.08

0.8

0.3
20
20

30

45
85

0.35

´ V

S

S

0.1

-0.15 V

V

S

0.1

-0.15 V

V

S

S

S

0.4 V

0.4 V

0.2 ´ V

S

0.2 ´ V

S

0.2 ´ V

S

µA

mA

°C

V
V
V

V
V

V

V

V
V

V
V

V

4569A–RKE–12/02

39

Ordering Information

Extended Type Number Package Remarks

T5743P3-TG SO20 Tube, IF bandwidth of 300 kHz
T5743P3-TGQ SO20 Taped and reeled, IF bandwidth of 300 kHz
T5743P6-TG SO20 Tube, IF bandwidth of 600 kHz
T5743P6-TGQ SO20 Taped and reeled, IF bandwidth of 600 kHz

Package Information

Package SO20

Dimensions in mm

0.4

1.27

20 11

12.95

12.70

11.43

0.25

0.10

2.35

technical drawings
according to DIN
specifications

9.15

8.65

7.5

7.3

0.25

10.50

10.20

40

110

T5743

4569A–RKE–12/02

Atmel Headquar ters Atmel Operation s

Corporate Headquarters

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TEL [phone]
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Chuo-ku, Tokyo 104-0033
Japan
TEL [phone]
FAX [phone]

Memory

2325 Orchard Parkway
San Jose, CA 95131
TEL [phone]
FAX [phone]

Microcontrollers

2325 Orchard Parkway
San Jose, CA 95131
TEL [phone]
FAX [phone]

La Chantrerie
BP 70602
44306 Nantes Cedex 3, France
TEL [phone]
FAX [phone]

ASIC/ASSP/Smart Cards

Zone Industrielle
13106 Rousset Cedex, France
TEL [phone]
FAX [phone]

1150 East Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906
TEL [phone]
FAX [phone]

Scottish Enterprise Technology Park
Maxwell Building
East Kilbride G75 0QR, Scotland
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FAX [phone]

RF/Automotive

Theresienstrasse 2
Postfach 3535
74025 Heil bronn , Ger many
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FAX [phone]

1150 East Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906
TEL [phone]
FAX [phone]

Biometrics/Imaging/Hi-Rel MPU/
High Speed Converters/RF Datacom

Avenue de Rochepleine
BP 123
38521 Saint-Egreve Cedex, France
TEL [phone]
FAX [phone]

e-mail

[e-mail]

Web Site

http://www.atmel.com

© Atmel Corporation 2002.

Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty
which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors
which may appear in this document, reserves the right t o change devices or specifications detailed herein at any time without n otice, and does
not make any commitment to update the information contained herein. No licenses to patents or other intellectual proper ty of Atmel are granted
by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical
components in life support devices or systems.

Atmel® is the registered trademark of Atmel.
Other terms and product names may be the trademarks of others.

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