Datasheet SY10E446, SY100E446 Datasheet (MICREL)

4-BIT PARALLEL-TO-SERIAL
CONVERTER

SY10E446

SY100E446

FEATURES

■ On-chip clock ÷4 and ÷8

■ Extended 100E V

EE range of –4.2V to –5.5V

■ 1.6Gb/s typical data rate capability

■ Differential clock and serial inputs

■ VBB output for single-ended use

■ Asynchronous data synchronization

■ Mode select to expand to 8 bits

■ Internal 75KΩ input pulldown resistors

■ Fully compatible with Motorola MC10E/100E446

■ Available in 28-pin PLCC package

PIN CONFIGURATION

1

3

2

0

D

D

D

TOP VIEW

PLCC

J28-1

MODE

NC

NC

18

NC

17

NC

16

V

CC

15

SOUT

14

SOUT

13

V

CCO

12

NC

CLK
CLK

V

BB

V

EE

SIN
SIN

SYNC

D

25

24 23 22 21 20 19

26
27
28

1
2
3
4

567891011

DESCRIPTION

The SY10/100E446 are integrated 4-bit parallel-to­serial data converters. These devices are designed to
operate for NRZ data rates of up to a minimum of 1.3Gb/
s. The chips generate a divide-by-4 and a divide-by-8
clock for both 4-bit conversion and a two-chip 8-bit
conversion function. The conversion sequence was
chosen to convert the parallel data into a serial stream
from bit D
two E446 devices for 8-bit conversion applications.

The SYNC input will asynchronously reset the internal
clock circuitry. This pin allows the user to reset the internal
clock conversion unit and, thus, select the start of the
conversion process.

The MODE input is used to select the conversion mode
of the device. With the MODE input LOW (or open) the
device will function as a 4-bit converter. When the mode
input is driven HIGH, the internal load clock will change
on every eighth clock cycle, thus allowing for an 8-bit
conversion scheme using two E446s. When cascaded in
an 8-bit conversion scheme, the devices will not operate
at the 1.3Gb/s data rate of a single device. Refer to the
applications section of this data sheet for more information
on cascading the E446.

For lower data rate applications, a VBB reference
voltage is supplied for single-ended inputs. When
operating at clock rates above 500MHz, differential input
signals are recommended. For single-ended inputs, the
VBB pin is tied to the inverting differential input and
bypassed via a 0.01µF capacitor. The VBB provides the
switching reference for the input differential amplifier. The
VBB can also be used to AC couple an input signal.

0 to D3. A serial input is provided to cascade

CCO

V

CL/8

CL/8

CCO

V

CL/4

CL/4

CCO

V

PIN NAMES

Pin Function

SIN, SIN Differential Serial Data Input
D0 – D3 Parallel Data Input
SOUT, SOUT Differential Serial Data Output
CLK, CLK Differential Clock Input
CL/4, CL/4 Differential 4 Clock Output
CL/8, CL/8 Differential 8 Clock Output
MODE Conversion Mode, 4-bit/8-bit
SYNC Conversion Synchronizing Input

CCO VCC to Output

V

Rev.: C Amendment: /1

1

Issue Date: February, 1998

Micrel

BLOCK DIAGRAM

SY10E446

SY100E446

SIN
SIN

D3

D2

D1

0

DQ

1

CLK

0

DQ

1

CLK

0

DQ

1

CLK

D0

MODE

CLK
CLK

SYNC

VBB

DELAY

0

DQ

1

CLK

01

÷4

R

÷8

R

SOUT
SOUT

CL/8

CL/8

CL/4
CL/4

2

SY10E446

Micrel

SY100E446

TRUTH TABLE

Mode Conversion

L 4-Bit

H 8-Bit

DC ELECTRICAL CHARACTERISTICS

VEE = VEE (Min.) to VEE (Max.); VCC = VCCO = GND

TA = 0°CTA = +25°CTA = +85°C

Symbol Parameter Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit Condition

IIH Input HIGH Current ——150 ——150 ——150 µA —

OH Output HIGH Voltage V1

V

(SOUT Only) 10E –1020 —–790 –980 —–760 –910 —–670

(SOUT Only) 100E –1025 —–830 –1025 —–830 –1025 —–830

BB Output Reference Voltage V —

V

10E –1.38 —–1.27 –1.35 —–1.25 –1.31 —–1.19

100E –1.38 —–1.26 –1.38 —–1.26 –1.38 —–1.26

EE Power Supply Current mA —

I

10E — 110 132 — 110 132 — 110 132

100E — 110 132 — 110 132 — 127 152

NOTE:

1. The maximum VOH limit was relaxed from standard ECL due to the high frequency output design. All other outputs are specified with the standard 10E
and 100E VOH levels.

AC ELECTRICAL CHARACTERISTICS

VEE = VEE (Min.) to VEE (Max.); VCC = VCCO = GND

A = 0°CTA = +25°CTA = +85°C

T

Symbol Parameter Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit Condition

MAX Max. Conversion Frequency 1.3 1.6 — 1.3 1.6 — 1.3 1.6 — Gb/s —

f

NRZ

t

PLH Propagation Delay to Output ps —

tPHL CLK to SOUT 1000 1400 1700 1000 1400 1700 1000 1400 1700

CLK to CL/4 500 800 1100 500 800 1100 500 800 1100
CLK to CL/8 800 1100 1400 800 1100 1400 800 1100 1400
SYNC to CL/4, CL/8 500 800 1100 500 800 1100 500 800 1100

S Set-up Time ps —

t

SIN –200 –400 —–200 –400 —–200 –400 —
Dn –200 –400 —–200 –400 —–200 –400 —
Mode 0 –250 — 0 –250 — 0 –250 —

H Hold Time ps —

t

SIN 750 550 — 750 550 — 750 550 —
Dn 800 600 — 800 600 — 800 600 —
Mode 500 300 — 500 300 — 500 300 —

tRR Reset Recovery Time 500 200 — 500 200 — 500 200 — ps —

PW Minimum Pulse Width 400 ——400 ——400 ——ps —

t

CLK, MR

r Rise/Fall Time ps 20–80%

t
tf SOUT 100 225 350 100 225 350 100 225 350

Other 200 425 650 200 425 650 200 425 650

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TIMING DIAGRAMS

CLK

RESET

0

D

D

1

D

2

D

3

SY10E446

SY100E446

0–1

D

D

1–1

D

2–1

D

3–1

D

0–2

D

1–2

D

2–2

D

3–2

SOUT

CL/4

CL/8

D

0–1D1–1D2–1D3–1D0–2D1–2D2–2D3–2

Timing Diagram A. 4:1 Parallel-to-Serial Conversion

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TIMING DIAGRAMS (CONTINUED)

CLK

RESET

D

0

D

1

D

2

D

3

SY10E446

SY100E446

0–1

D

D

1–1

D

2–1

D

3–1

D

0–2

D

1–2

D

2–2

D

3–2

D4(D0B)

D5(D1B)

6(D2B

D

D

7(D3B

SOUT

CL/4

CL/8

4–1

D

D

5–1

)

)

Timing Diagram B. 8:1 Parallel-to-Serial Conversion

D

6–1

D

7–1

D

0–1D1–1D2–1D3–1D4–1D5–1D6–1D7–1

D

4–2

D

5–2

D

6–2

D

7–2

D

0–2D1–2

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APPLICATIONS INFORMATION

SY10E446

SY100E446

The SY10E/100E446 are integrated 4:1 parallel-to-serial

converters. The chips are designed to work with the E445
device to provide both transmission and receiving of a high­speed serial data path. The E446 can convert 4 bits of
data into a 1.3Gb/s NRZ data stream. The device features
a SYNC input which allows the user to reset the internal
clock circuitry and restart the conversion sequence (see
Timing Diagram A). Note that SOUT is triggered by negative
clock edges.

The E446 features a differential serial input and internal

divide-by-eight circuitry to facilitate the cascading of two
devices to build an 8:1 multiplexer. Figure 1 illustrates the
architecture for an 8:1 multiplexer using two E446s (see
Timing Diagram B). Notice the serial outputs (SOUT) of the
lower order converter feed the serial inputs of the higher
order device. This feed through of the serial inputs bounds
the upper end of the frequency of operation. The clock-to­serial output propagation delay, plus the set-up time of the

CLK
CLK

serial input pins, must fit into a single clock period for the
cascade architecture to function properly. Using the worst
case values for these two parameters from the data sheet,
tPD CLK to SOUT = 1600ps and ts for SIN = –200ps, yields
a minimum period of 1400ps or a clock frequency of
700MHz.

The clock frequency is somewhat lower than that of a
single converter. In order to increase this frequency, it is
recommended that the clock edge feeding the E446A be
delayed with respect to the E446B, as shown in Figure 2.

Perhaps the easiest way to delay the second clock relative
to the first is to take advantage of the differential clock
inputs of the E446. By connecting the clock for E446A to
the complimentary clock input pin, the device will clock a
half a clock period after E446B (Figure 2). Utilizing this
simple technique will raise the potential conversion frequency
up to the maximum 1.3GHz of a stand-alone E446.

CLK

PD

t
CLK to SOUT

E446B

SOUT
SOUT

D3D2D1D

D7D6D5D

SIN
SIN

0

4

PARALLEL DATA

1400ps

D3D2D1D

D3D2D1D

1600ps

E446A

SOUT
SOUT

200ps

SERIAL
DATA

0

0

Figure 1. Cascaded 8:1 Converter Architecture

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APPLICATIONS INFORMATION

CLK
CLK

SY10E446

SY100E446

CLKB
CLKA

t

PD

CLK to SOUT

E446B

SOUT
SOUT

D3D2D1D

D7D6D5D

SIN
SIN

0

4

D3D2D1D

D3D2D1D

PARALLEL DATA

1.3GHz
770ps

E446A

SOUT
SOUT

SERIAL
DATA

0

0

Figure 2. Extended Frequency 8:1 Converter Architecture

PRODUCT ORDERING CODE

Ordering Package Operating

Code Type Range

SY10E446JC J28-1 Commercial
SY10E446JCTR J28-1 Commercial
SY100E446JC J28-1 Commercial
SY100E446JCTR J28-1 Commercial

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28 LEAD PLCC (J28-1)

SY10E446

SY100E446

Rev. 03

MICREL-SYNERGY 3250 SCOTT BOULEVARD SANTA CLARA CA 95054 USA

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