Datasheet STLC5432 Datasheet (SGS Thomson Microelectronics)

2Mbit CEPT & PRIMARY RATE CONTROLLER DEVICE

ONE CHIP SOLUTION FROM PCM BUS TO
TRANSFORMER (CEPTSTANDARD)

ISDN PRIMARY ACCESS CONTROLLER
(COMPATIBLEWITHETSI,OPTION1 AND 2)

HDB3/BIN ENCODER AND DECODER ON
CHIP

MULTIFRAME STRUCTURE HANDLING
BUILTIN CRC4
EASY LINK TO ST5451/MK50H25/MK5027

LINK CONTROLLERS.
DATA RATE: 2048, 4096 AND 8192 Kb/s FOR

MULTIPLEXEDAPPLICATIONS
FOURLOOPBACKMODES FORTESTING
PSEUDO RANDOM SEQUENCE GENER-

ATOR AND ANALYZER FOR ON-LINE, OFF­LINE AND AUTOTEST

CLOCKRECOVERY CIRCUITRYON CHIP
64 BYTE ELASTIC MEMORY FOR TIME

COMPENSATION AND AUTOMATIC FRAME
AND SUPERFRAMEALIGNMENT

32 ON CHIP REGISTERS FOR CONFIGURA­TIONS, TESTING, ALARMS, FAULT AND ER­ROR RATE CONTROL.

AUTO ADAPTATIVE DETECTION THRESH­OLD

AUTOMATIC EQUALIZEROPTION
5V POWERSUPPLY
AMI OR HDB3 CODESELECTION
PARALLEL OR SERIAL MICROPROCESSOR

INTERFACEOPTION
BOTH µp AND STAND ALONE MODE AVAIL-

ABLE

DESCRIPTION

STLC5432, CMOS device, interfaces the multi­plex system to the physical CEPT Transmission
link at 2048Kb/s. Furthermore, thanks to its flexi­bility, it is the optimum solution also for the ISDN
application as PRIMARY RATE CONTROLLER.
The receive circuit performances exceed CCITT
recommendation and the line driver outputs meet
the G.703 specifications.
STLC5432 is the real single chip solution that al­lows the best system flexibility and easy design.
STLC5432 can work either in 2048 or 4096 or
8192 Kbit/s systemsprogramming the CR4 regis­ter (when parallel microinterfaceselected).

STLC5432

TQFP44 (10 x 10)

ORDERING NUMBER: STLC5432Q

PIN CONNECTION (Topview)

P0

LI1

VT

P1

GNDA

GNDD

SA/RESET

DIN
A/D0
A/D1
A/D2
A/D3

INT

RCLI

BRDI

DOUT

LI2

1
2
3
4
5
6
7
8
9
10
11

RCLO

BRDO

AS/ALE

XTAL1

3940414344 42

1716151312 14 22212018 19

XTAL2

VCCD2

DPI

VCCD1

PRELIMINARY DATA

VCCA

CS

LO1

LO2

34353638 37

33

BXDI

32

AL0

31

AL1

30

A/D7

29

A/D6

28

A/D5

27

A/D4

26

R/W/WR

25

LFSX

24

LFSR

23

LCLK

HCR

LCR

DS/RD

D93TL043D

BXDO

July 1996

1/46

STLC5432

PIN DESCRIPTION

Name Pin Type Function

Positive power supply inputs for the digital (V

VCCD1
VCCD2

VCCA

GNDD
GNDA

LI1
LI2

18
17
34

1

44

40
42

VT 41 O Positive power supply output for fixing reference voltage to the receive transformer.

L01
L02

36
37

XTAL1 15 I The master clock input which requires either a parallel resonance crystal to be tied

XTAL2 16 O The output of the crystal oscillator, which should be connected to one end of the

HCR 19 O High clock received, bit clock. When the device has recovered the clock from the

LCR 20 O Low clock received, frame clock. When the device has recovered the clock from the

BRDO

RCLO

BRDI
RCLI

12
14

10

9

BXDO 22 O Binary TransmitData Output, 2048kbit/s oroutput clock at 64kHz.

BXDI 33 I This binary signal can replace BXD internal signal to be encoded if SELEX bit (CR1

DOUT 11 O Data Output. 30 B+D primary access data received from the line.Data can be shifted

DIN 3 I Data Input : 30B+D primary access data to transmit tothe line.Data can be shifted in

I
I

microprocessor interface signals (V

I

connected together.

). They must be +5 Volts and must be directly

CCD2

) and analog (V

CCD1

) sections and for

CCA

IINegative power supply pins which must be connected together close to the device. All

digital and analog signals are referred to thesepins, which are normally at the system
ground.

I

Receive HDB3 signal differential inputs from the line transformer.

I

Typical value is 2.375V

OOTransmit HDB3 signal differential outputs to the line transformer.When used with an

appropriate transformer, the linesignal conforms to the outputspecifications in CCITT
with a nominal pulse amplitude of 3 volts for a 120Ω load on line side.

between this pin and XTAL2, or a clock input from a stable source. This clock does
not need to be synchronized to the system clock.
Crystal specifications = 32764 kHz ± 50 ppm parallel resonant; RS ≤ 20Ω loaded with
33pF to GND each side.

crystal if used.

HDB3 signal, HCR signal is synchronized to the remote circuit. The HCR frequency is
either 8192kHz if 8MCR bit of CR1 Register is put to 1 or 4096 kHz if 8MCR is set to

0.

HDB3 signal, LCR signal is synchronized to the remote entity.
The LCR frequency is 8 kHz if 8KCR bit is set to 1, or 4 kHz if 8KCR bit is set to 0.
When the remote clock is not recovered, HCR and LCR frequency are synchronized
to master clock (16384 kHz).
HCR and LCR can be used by the system inTerminal Mode.These two clocks can be
used by the transmit function of the device.

OOBinary Receive Data Output, 2048 kbit/s or 64kbit/s.

Receive Clock output, 2048 kHz or 64kHz.
After decoding, Binary Data and clock associated are provided for different
applications.

IIBinary Receive Data Input. 2048 kbit/s.

Receive Clock Input 2048 kHz.

Before encoding Binary Data is provided to different applications (Optical Interface for
instance). Local clock is associated to thisdata.

Register) is set to 1.

out from the tristate outputDOUT at the LCLK frequency on the rising edges during
all the time slots,except Time Slot Zero inaccordance withTSOE bit (CR1Register).
NB : If parallel micro-interface is selected, DOUT is at high impedance after Reset.
DOUT is at low impedance after writing CR4 register.

at the LCLK frequency on the falling edges during all the time slots,except Time Slot
Zero, in accordance with TSOE bit (CR1 Register).

2/46

STLC5432

PIN DESCRIPTION(continued)

Name Pin Type Function

LCLK 23 I Local Clock : this clock input determines the data shift rate on the two digital

LFSR 24 I Local Frame Synchronization for the Receiver. This clock input defines the start of the

LFSX 25 I Local Frame Synchronizationfor the Transmitter. This clock input defines the start of

AL0,

AL1

32
31

multiplexes. Thisclock frequencycan be indifferently2048, 4096, 8192or 16384kHz.
Data Out and Data In rate is always 2048 kbit/s when Serial Interface microprocessor:
an internal automatic mechanism divides by two the frequency if 4096 kHz.

frame on the digital multiplex Data (pin DOUT). This clock frequency can be
indifferently 8 kHz or a submultiple of 8 kHz.

the frame on the digital multiplex Data (pin DIN). This clock frequency can be
indifferently 8 kHz or a submultiple of 8 kHz.
If submultiple of 8 kHz, LFSX defines the start of even frame on DIN.The TSO of this
even frame will contain the Frame Alignment Signal(FAS) on the line.

OOAlarm 0 Output, alarm 1 Output. These pins are opendrain outputs which are

normally in high impedance state.

AL1 AL0 Alarm definitions

Z Z Frame or Multiframerecovered,
0Volt Z Frame or Multiframe recovered,
Z 0Volt Frame and Multiframe lost, AIS
0Volt 0Volt Frame and Multiframe lost, AIS

DPI 38 I DPI input: The internal DPLL is synchronizedeither by the signalapplied on DPI input

SA/RESET 2 I Stand Alone : When this pin is connected to 5 Volts, the device works without

P0, P1 39, 43 I Processorinterface. These two input pins define the microprocessor interface

AS/ALE 13 I Address Strobe/Address Latch Enable. Input

CS 35 I Chip Select.A high level on this input selects the PRCD for a read write operation.

R/W/WR 26 I Read/Write/Write Data. Input.

DS/RD 21 I Data Strobe/Read Data. Input.

A/D0toA/D7 4 to 7;

27 to 30

INT 8 O Interrupt Request. Thesignal is activated low when the PRCD requestsan interrupt. It

(if DPIS bit of CR5 register is =0) orby the 2MHz clock recovered from the line.

microprocessor. The configuration is given by the values per default of programmable
registers. BRDI and BXDI must not be used.

RESET: When this pin is put to 5 Volts during 100 ns at least every programmable
register is reset (value per default). When this pin is set at zero Volt, the type of
microprocessor is selected by P0, P1 pins.

chosen.

I/O

Address/Data 0 to 7. Input-Output.

is an open drain output.

P1 P0 Microprocessor Interface

----------------------------------------------------------------------------------­0 0 Serial MicroprocessorInterface
0 1 ST9 MicroprocessorInterface
1 0 Multiplexed Motorola processor interface
1 1 Multiplexed Intel processorinterface

A bit received is 0.
A bit received is 1
Alarm Indication Signal is detected.
Alarm Indication Signal is not detected.

3/46

STLC5432

BLOCK DIAGRAM

BRDO BRDI

µP

ELASTIC

MEMORY

BRD

LCLK

PROGRAMMABLE

INTERFACE

REGISTERS

4

LOOPBACK

2

LOOPBACK

3

LOOPBACK

BXD

LFSR

DOUT

64 BYTES

SYNCHRONIZATION

AB

DIN

LFSX

D

MULTIFRAME

GENERATION

64KHz

CLOCK

D93TL044F

BXDI BXDO

4/46

RCLO

Q=32764KHz

LCRHCR

DPLL

HDB3/BIN

DECODER

RD-

RD+

DATA

CLOCK

RECOVERY

A

From A, B or DIN

PSEUDO

RANDOM

SEQUENCE

PSEUDO

RANDOM

SEQUENCE

1

LOOPBACK

2Mb/s

S2/T2

INTERFACE

To D or DOUT

GENERATOR

ANALYZER

BIN/HDB3

ENCODER

ALARM

SIGNALS

LINE

DRIVER

STLC5432

ABSOLUTE MAXIMUM RATINGS

Symbol Parameter Value Unit

V

to GND Supply Voltage to Ground 7 V

CC

V

I

I

LO1,IOL2

I

C

T

stg

T

L

THERMAL DATA

Symbol Parameter Value Unit

R

thj-amb

Voltage at any digital or analog input VCC+1 to GND-1 V
Current at LO1 and LO2

100 mA

±

Current at any digital or analog input ±30 mA
Storage temperature range -65 to +150 °C
Lead Temperature (soldering, 10s) +300 °C

Thermal Resistance Junction to ambient Max. 50 °C/W

ELECTRICALCHARACTERISTICS (VCC=5V±5%, T
fied at V

CC

= 5V,T

=25°C; all signalare referencedto GND,unlessotherwise specified.)

amb

= 0 to 70°C; Typical characteristicsare speci-

amb

Symbol Parameter Test Condition Min. Typ. Max. Unit

DIGITAL INTERFACE

Vil Input Low Voltage All digital inputs 0.8 V

Vih Input High Voltage All digital inputs 2.2 V

Vilx Input Low Voltage XTAL1 input 0.5 V

Vihx Input High Voltage XTAL1 input V

Vol Output Low Voltage I

= 7mA for pins AL0, AL1,

L

-0.5 V

CC

0.4

INT, DOUT, HCR, LCR.

0.4

Voh Output High Voltage I

All other digital outputs:
I

= 1mA

L

= 7mA for pins AL0, AL1,

L

2.4
INT, DOUT, HCR, LCR.
All other digital outputs:
I

= 1mA

L

2.4

Iil Input Low Current Any digital input, Gnd < Vin < Vil 10

Iih Input High Current Any digital input, Gnd < Vin <

V

CC

Ioz Output Currentin High

Impedance (tri-state)

All digital tri-state I/Os without
internal pull-up or pull-down

10 µA

10

resistor.

LINE INTERFACE FEATURES

Zin Differential Input Resistance DC measurement between LI1

200 K
and LI2 with the equalizer not
connected

Vin Rx sensitivity Relative to LI1/LI2 pins with

0.6 Vpk

fixed detection threshold

Vpk75 Transmit amplitude 75Ω at transformer secondary 2.14 2.37 2.60 Vpk

Vpk120 Transmit Amplitude 120Ω at transformer secondary 2.7 3 3.30 Vpk

Sym Pulses Symetry 75Ω or 120Ω at transformer

5%

secondary

Zero Zero level % nominal amplitude 10 %

Pwdth Tx pulses width at 50% of peak amplitude 219 244 269 ns

Zout Differential Output Resistance 1 Ω

MASTERCLOCK

MCLK MCLK Frequency 32.764 MHz

MCLK Frequency tolerance –50 50 ppm

JITTER PERFORMANCES(for jitter transfer function and admissible jitter please report to the corresponding
characteristics plotted in following page).

Intrinsic jitter Filter 20Hz - 100KHz 0.125 UI
Intrinsic jitter Filter 700Hz - 100KHz 0.12 UI

V
V

V
V

A

µ

A

µ

Ω

5/46

STLC5432

ELECTRICALCHARACTERISTICS (continued)

Symbol Parameter Test Condition Min. Typ. Max. Unit

POWER CONSUMPTION

Icc75 Active Current(including line

current)

Icc120 Active Current(including line

current)

TRANSFORMER SPECIFICATION FOR75Ω

L:M:N: Turns ratioes 1.57:1:1

RL L Windings Resistance 0.23

RMN M and N winding resistances 0.11 Ω

LL Inductance of winding L F = 100KHz, Vrms = 100mV 2 mH
Ls Leakage inductange of a

winding, the other being short
circuited

Ck Inter winding capacitance F = 100KHz, Vrms = 100mV 15 pF

TRANSFORMER SPECIFICATION FOR120Ω

L:M:N: Turns ratioes 2:1:1

RL L Windings Resistance 0.2

RMN M and N winding resistances 0.1

LL Inductance of winding L F = 100KHz, Vrms = 100mV 2 mH
Ls Leakageinductange ofawinding,

theother beingshortcircuited

Ck Inter winding capacitance F = 100KHz, Vrms = 100mV 15 pF

XTALL SPECIFICATIONS

Co Motional capacitance 0.2 pF

Cc Shunt capacitance 6 pF
Lo Inductance 4.718 mH
Rs Serial resistance 15

CL Load (corresponding to two

33pF capacitors connected to
XTAL1 and XTAL2 pins on the
application schematic)

DYNAMIC CHARACTERISTICS

tpd LCLK high to DOUT valid

LCLK high to BXDO valid
XTAL1 high to HCR high or low

tpdz LCLK high to DOUT HZ 150pF; 7mA 50 ns

td HCR high to LCR high or low

RCLOhighto BDROhighorlow
ts All data inputs to clock low 10 ns
th Clock low to alldata inputs 10 ns

random output (50% of ones) 40 mA

random output (50% of ones) 40 mA

F = 100KHz, Vrms = 100V 0.3 µH

F = 100KHz, Vrms = 100mV 0.2 µH

20 pF

150pF; 7mA
50pF; 1mA
150pF; 7mA

150pF; 7mA
50pF; 1mA

–20 20 ns

50 ns

Ω

Ω
Ω

Ω

6/46

Figure 1: ReceiverDiagram

STLC5432

RCLODPILCRHCR

BRDO BRDI

1

DATA

64Kb/s

LP3

SIG

A

1

1

HDB3/BIN

DECODER

64 x 8

SELER

DOUT

1

B

MEMORY

RDS

-1

n

2

GENERATOR

A

B

-1

n

SAV

2

SGV

RXRD

ANALYZER

BIN/HDB3

DIAGRAM

TRANSMITTER

ENCODER

DIN

PULSE

SINGLE

D93TL046C

DATA

CLOCK

RECOVERY

1

DPLL

DPIS

1

ASP

1

LP1

A

S2/T2

2Mb/s

INTERFACE

ALARM

1

AIS

A

7/46

STLC5432

INTRODUCTION

This single chip CMOS Device interfaces the
physical multiplex of the application to the physi­cal CEPT transmissionlink at 2048kb/s.

STLC5432 contains analog and digital functions
to implement line interface function and frame
synchronization. It meets pulse shape and jitter
specifications in accordance with CCITT Recom­mendations and CEPTstandards.

FUNCTIONAL DESCRIPTION

1. LINEINTERFACE

1.1 Receiver
The receive input signal should be derived via a

transformer of the same type used for the trans­mit direction. The suggested transformer is the
VAC L4097-X004 or equivalent for the 75 ohms
case and the VAC 4097-X012 or equivalent for
the 120 ohms case. The electrical models of the
transformers are summarized in the following ta­ble :

Loads

(Ω)

75 1.57 :1:1 ≤0.3 ≤15 ≥2 0.11 0.23

120 2:1:1 ≤0.2 ≤15 ≥2 0.10 0.20

Ls

n

(µH)Ck(pF)Lh(mH)

Rcul

(Ω)

Rculll

(Ω)

with:

n: Windingratioes
Ls: Leakageinductance

Figure 2: TransmitterDiagram

Ck: Interwinding capacitance
Lh: Principalinductanceof

windings

RcuI and RcuIII : DC resistancesof

windingI and III.

Wiring between the transformer and the circuit
should respect the application schematic given in
annex.(see fig4).

The internalfixed thresholdis set to 200 mV over
the common mode voltage VCM (VCM = 2.375 V
nominal) to insure the specified transmission
range with a good noise immunity.

Two options are provided for special applications
requiringimproved transmissionranges:

AUTO-ADAPTATIVETHRESHOLD:
Using the configuration register CR4 (AVT), a
peak amplitude detectorcircuit is connected to
the received signaland after digital processing,
an adaptative threshold value equal to 3/8 of
the peak value is obtainedat the output of a D
to A converterand used for data detection.

AUTOMATIC EQUALIZER: connecting two ex­ternalcapacitorsof100pFin seriesbetweenthe
transformerandthe circuitsinputs,and usingthe
configuration register CR4 (EQV), the circuit will
selectautomatically a pre-compensationfilter for
long line configuration (see application sche­maticon figure3 and4 givenin annex).

8/46

BIN/HDB3

ENCODER

1

SELEX

BXDI BXDO

RD RX

1

LP2

64KHz

CLOCK

1 SIG

TM

DOUT

SGV

n

-1

2

GENERATOR

LP4

CRC4

1

1

RDS

1

D

1

SIG

ADAPTOR: WHEN

DATA IN CLOCK IS

64KHz, DATA

CLOCK AT 2048KHz

BXDI

TS

GENERATOR

TSO

1

AT

OUT

DIN

D93TL045B

STLC5432

Using bothoptions allow the reception of a signal
attenuatedup to 12dBat 1024kHz.

The Clock recovery is performed by a first PLL
that guaranties the CCITT I431 requirements for
the allowedJitter, see Figure 23, this clock, RCL,
is usedinternallyandas local clock.
A second DPLL starting from this RCL clock at­tenuate the Jitter,to fulfil the CCITT I431, see fig­ure 8, this DPLL generate HCR, bit clock, and
LCR frame clock, practically without Jitter.

1.2 Transmitter
The line driver outputs are designed to drive the

suitable transformer mentioned in the previous
section. The transformerresults in a signal ampli­tude of 3 voltson the linewhich meet G.703 pulse
shape for a 120 ohm load (2.37 volt for a 75
ohms load).

A special test mode is provided to check the
pulse template according to the CCITT mask by
using the configurationregister CR3 (ASP).

When the ALS command is valid, consecutive
logical ”ones” are transmittedon theline.

When APS command is valid, consecutive 1, 0,

1... 1, 0,1, 0... are transmitted on the line.

2 CODING

2.1 HDB3/BINDECODING
The two constituents of the data signal are de-

coded and the binary Receive Data Signal (BRD)
is processedbythe next functions.

2.2 BIN/HDB3ENCODING
The binary transmit data signal (BXD) is encoded.

The entire data stream, including all the time
slots, is scanned for an occurence of four con­secutive zeros.

Such occurence is replaced by the appropriate
HDB3 code.

3. BINARYINPUT-OUTPUT

STLC5432 can directly interface binary data
stream by means of the 6 dedicatedpins:
BRDO, RCLO,BRDI, RCLI,BXDOand BXDI.
This allows the use of STLC5432also for particu­lar cases as for optical fiber or for different pur­poses. The functions of these 6 pins are defined
by the SIGbit (SIGR register).

3.1 SIG = 0
When the bit SIG = 0 the binary data are ex-

changed at 2048KHzand the 6 extrapins are de­fined hereafter.

3.1.1 Extrapinsfor receive data
The BRDOand RCLO output pins deliver respec-

tively BRD binary receive data at 2048kb/s and
the remoteclock recovered at 2048kHz.

Two BRDI and RCLI input pinscan receive exter­nal binary receive data at 2048kb/s and the re­ceiveclockassociated at 2048kHz.

The SELERcommand replaces BRD internal sig­nal with BRDI signal.

3.1.2 Extrapins for transmitdata
The transmit binary data output pin BXDO deliv-

ers transmitbinary data BXD.
Input pin BXDI can receive external binary trans-

mit data.
The SELEXcommand replaces BXD internal sig-

nal with BXDIsignal.

3.2 SIG = 1
When SIG = 1, a signaling channel at 64 kb/s is

implemented.

3.2.1 Extrapins for Receivedata
BRDO and RCLO output pins deliver respectively

receive data at 64kb/s selected by an internal
Time Slot Assigner and the receive clock associ­ated at 64kHz. In this case, BRDI and RCLI are
not used.

3.2.2 Extrapins for TransmitData
Output BXDO delivers the 64kHz clock for an ex-

ternal application. This external entity delivers
data at 64kb/son the rise edge of the clock.

Input BXDIshifts data at 64 kb/s on the fall edge
of the 64kHzclock.

The same Time Slot Assigner is used by transmit­ter and receiver(See SIGR Register).

4 LOOPBACK

4.1 LOOPBACK1
When LP1 Command is valid (LP1 bit high, see

CRC3 register), output data signal replaces input
data signal. Then, the recoveryclock functionpro­vides the local clock. The loopbackis transparent
if AIS is at 0. If AISX is at 1, consecutive logical
”ones”are transmittedon theline.

4.2 LOOPBACK2
LP2 Command (LP2 bit high, CR3 register) re-

places BXD and XCLK signals (respectively Bi­nary Transmit Data and transmit clock) with BRD
and RCLK (respectively Binary Receive data and
its clock recovered).

4.3 LOOPBACK3
LP3 Command (LP3 bit high, CR3 register) re-

places BRD and RCLK (respectively Binary Re­ceive Data and its clock recovered) with BXD and

9/46

STLC5432

XCLK (respectively Transmit Data and its clock
associated). Frame and multiframe generated by
the transmitter of the circuitare processed by the
receiver of the circuit, without encoding and de­coding.

4.4 LOOPBACK4
LP4 Command replaces Data in with Data out

near of DIN and DOUT pins (See LP4R register).

5 FRAME ALIGNMENT

Time slot 0 is used for the synchronization
(G.706). At softwareReset Frame and Multiframe
are lost and a new research of FASand MFAS is
launched.

5.1 LOSS OF FRAMEALIGNMENT
Frame alignment will be assumed to have been

lost :

– eitherwhen three consecutiveincorrect frame

alignmentsignals have been received,

– or when bit 2 in time slot 0 in odd frames has

been received with an error, i.e. at0, on three
consecutiveoccasions,

– or when 915 errored CRC blocks out of 1000

have been detected.

5.2 FRAME ALIGNMENT RECOVERY
Frame alignment will be assumed recovered

when the followingsequence is detected:

– Detection of the correct Frame AlignmentSig-

nal, FAS
– detectionof bit 2 of 32nd byte after FAS,at 1.
– detectionof the correct Frame Alignment sig-

nal in the 64th byte after the first FAS de-

tected.

5.3 MULTIFRAME ALIGNMENTRECOVERY
Multiframe Alignment will be assumed recovered

when at least two valid multiframe alignment sig­nals MFAShave been detectedwithin 8 ms.

Table 1: CRC4 Multiframe StructureG.704

Sub

Multiframe

I

II

FAS: Frame AlignmentSignal in each even Time Slot.
MFAS: Multi Frame Alignment Signal 0 0 1 0 1 1
E1–E2: CRC4 error Indication bits
C1 to C4: Cyclic Redundancy Check 4 (CRC4) bits
A: Remote Alarm Indication
Sa4 to Sa8: Five bits in each odd Time Slot
Sa61 to Sa64: ETSI bits

Frame

0C10011011
1 0 1 A Sa4 Sa5 Sa61 Sa7 Sa8
2C2 F A S
3 0 1 A Sa4 Sa5 Sa62 Sa7 Sa8
4C3 F A S
5 1 1 A Sa4 Sa5 Sa63 Sa7 Sa8
6C4 F A S
7 0 1 A Sa4 Sa5 Sa64 Sa7 Sa8
8C1 F A S

9 1 1 A Sa4 Sa5 Sa61 Sa7 Sa8
10 C2 F A S
11 1 1 A Sa4 Sa5 Sa62 Sa7 Sa8
12 C3 F A S
13 E1 1 A Sa4 Sa5 Sa63 Sa7 Sa8
14 C4 F A S
15 E2 1 A Sa4 Sa5 Sa64 Sa7 Sa8

12345678

TIME SLOT ZERO BIT NUMBERS

10/46

STLC5432

5.3.1 Typical case
Remote entity transmits Frame Alignment Signal

(FAS) and MultiframeAlignment Signal(MFAS).
As soon as lost of Frame Alignment is occured

(LOF = 1), the local receiver recovers FAS from
254 up to 500µs after. As soon as FAS is recov-
ered (LOF= 0), thelocal receiver recoversMFAS
from 4 up to6ms after.

5.3.2 Old ExistingEquipmentCase
Remote entity transm its Frame Alignment Signal

(FAS)withoutMultiframe AlignmentSignal(MFAS ) .
As soon as lost of Frame Alignment is occured
(LOF=1), the local receiver recovers FAS from 254
up to 500µs after. Then LOF = 0, and 400msafter
thelocalreceiverindicatesthattheMultiframeAligne­mentSignalhasnotbeenrecovered(MFNR =1).

5.3.3 ParticularCase:SpuriousFrameAlignment
Signal

Local receiver receives true FAS and true MFAS
among several spuriousFAS.

Multiframe Alignment signal (MFR=1) is recovered
from 8 to 400ms after the Frame Alignmentsignal
is recovered (LOF=0). Then, this FAS is either a
spurious one (the ”Spurious Timeslot Zero” is car­ryingFASwithoutMFAS), ortrue FAS.

Anyway, when the Multiframe Alignmenthas been
recovered (MFR=1), the good Frame Alignment
Signal is taken into account and data are loaded
intothe Frame Memoryat thegood location.
SeeFig. 13synchronizationalgorithm.

5.3.4 WorstCase

Local receiver receives true FAS and true MFAS
among several spurious FAS and several spuri­ous MFAS.

In this case, if the circuit has recovered a spuri­ous FAS and MFAS, the CRC blocks will be de­tected with an high error rate. As soon as 915 er­rored CRC block within 1000 will be detcted, the
MFAS will be assumedas spuriousanda new re­search starts at the point just after the location of
the assumed spuriousFrame Alignement Signal.

5.4 TransmitterSIDE

The Frame Alignement Signal is transmitted con­tinuously on the transmitterside, with bit 1 of TS0
at logical1.The MFASsignal is transmittedin ac­cordance with NMF bit register (CR5 Register):if
NMF is programmed to ”1” Logic, no MFAS is
transmitted; if NMF is programmed to ”0” Logic
the MFAS signal is transmittedcontinuously.

Table 2.

LOF MFR MFNR RECEIVER STATE

1 0 0 FAS or MFAShas been lost.

State: Research of FAS

0 0 0 FAS has beenrecovered.

State: Research of MFAS

0 1 0 FrameandMultiframerecovered

State: Good working.

0 0 1 Frame recovered.

State: Good working without
multiframe received from
transmitting side.

6 Interfacingwith themicroprocessor

The device can work in one of the 3 following
modes:

– Parallel microprocessor InterfaceMode
– Serial microprocessorInterfaceMode
– Withoutmicroprocessor : StandAlone Mode.
The choiceis done by means of the SA/Reset,P0
and P1 pins.

6.1 ParallelMicroprocessorInterfaceMode
The microprocessor can read (or write) the regis-

ters of the STLC5432 using the fifteen parallel In­terfacepins.

The use of TSO (Time Slot Zero) of DIN and
DOUT digital multiplex is defined by TSOE bit of
CR5 Register.

– If TSOE = 1, TSO on DIN multiplex Input is

used to transfer Sa4 to Sa8 bits to the line
and TSO on DOUT multiplexoutput isused to
transferSa4to Sa8bits fromthe line.

– If TSOE = 0, DOUT output is high impedance

during TSO, and DIN Input ignores data dur­ing TSO.

6.2 SerialMicroprocessor InterfaceMode
Fifteen parallel Interface pins are ignored, they

are tied to ground. In this mode, the time slots 0
of internal multiplexesare considered like a chan­nel used by the devices and the control entity lo­cated in the system to communicate. This chan­nel can be switched across a switching network

-or not- beforeits final destination.
The message is constituted by two bytes which
are transmitted on two consecutive Time Slots
Zero.
The bits of word are numbered 0 to 7, bit 0 is
transmittedfirst. Whenthe bit 7 ofa byte is 0,this
byte is the first word of the message.
The bit 6, of the first word, is R/W bit:
R/W = 1. Message to read a register whose ad­dress is designated by the following bits of the
word ( A 0/5).

11/46

STLC5432

R/W = 0. Message to write a register, addressed
by the bitsA0/5.
The bit 7 of following byte is 1 and the seven
D 0/6 bits are datato load into register.
To transfer one message,250µs are necessary.
Between two messages, the bits are 1 during
TS0. See fig.7 for details.

6.2.1 Reading of a register

The remote entity connected to the DIN and
DOUT multiplexes can request reading of a regis­ter if it transmits, during TSO, on DINthe address
bit A0/5,the R/Wbit at 1 and the last bit at0. The
following word, ending with 1, isnot takeninto ac­count by the device. The device returns two
words during TSOof DOUT:

–The first word begins with 0, R/W bit is put to

1, the address bits of the register are trans­mitted.

–The second word begins with 1, then seven

databits of the registerare transmitted.

6.2.2 Writing of a register

The remote entity connected to the DIN and
DOUT multiplexes can request writing, then it
transmits the first bit at 0, thesecond bit at 0 and
the register address A 0/5 during TSO of DIN.
The following word begins with 1 and seven next
bits are Data to load into register. There is no ac­knowledge after writing. The writing messages
can be transmittedconsecutively.

6.3 Stand Alone Mode

Whatever the received frequency on LCLK pin
(2.048kHz or 4.096kHz), the device automatically
fits and always works at 2.048kHz.When SA pin
is at 1, the multiframe research is automatically
launched after each lost of frame and the device
provides the following alarmson DOUTduring the
Time Slot 0:

7

F/S SKIP AR MFNR LOF B AIS LOS

LOS Lossof signal
AIS Alarm IndicationSignal
B If LOF = 1, thenB = 915

If LOF = 0, thenB = WER
LOF Loss of Frame
MFNR MultiFrame Not Recovered
AR ABit Received
SKIP Jump
F/S Fast/Slow.

Bits definitions are the same than bits definitions of
ALR, CAR1 and CAR2 Registers. These bitsrepre­sent the curre nt stateof the line; DI Nis ignoreddur­ingTime SlotZero.

7 RESET

During HardwareReset (Pin : SA/RESET):

– Alltheprogrammableregistersareconfigurated

withthe defaultvalue.

– Interrupts are not generated (INT PIN is high

impedance).

– The researchof Multiframeis alwaysactive.

AtSoftwareReset(addressing theResetregister):

– The registers are configuratedwith the default

value only.

AfterReset:

– The registers may be configurated with any

value.

8 INTERRUPT

All the bits of Alarm Registers generate an inter­rupt if they are not masked, exceptSLC (CAR2).

An alarm generates an interrupt if the mask bit
associated is 0. If a temporary event is detected
from the line. ALR Alarm Register, CAR1 and
CAR2 Complementary Alarm Registers can be
read after interruptor bypolling.

In this last case, these Alarm Registers can be
consideredlike particular statusregisters.

If a temporary event is detected from the line,
then the appropriate bit is put to one. After read­ing by the microprocessor, this bit is put to zero
until new event.

If a permanent state occurs, then the appropriate
bit is put to one. Afterreading by the microproces­sor, this bit remains at one until disappearance of
the cause.

8.1 ParallelInterfaceMode
ALR Alarm Register, CAR1 and CAR2 Comple-

mentary Alarm Registers can be read after inter­rupt or by polling.

In this last case, these Alarm Registers can be
consideredlike particular statusregisters.

INT pin is put to 0 volt. The microprocessorreads
AlarmRegister.
For example, after reading the ALR and CAR1
registersthemicroprocessorcould act as follows:

– If SCbit (clock1 second)is 1, then the micro-

processorreads fault counter registers.

– If EXT1 bit (EXTENSION1) is 1, then the mi-

croprocessor reads Complementary Alarm
Register1.

– If TSOR (or Sa6R) bit of CAR1 is 1, the mi-

croprocessorreads TSORR (or Sa6RR) Reg­ister

12/46

STLC5432

8.2 Serial InterfaceMode
When an Alarm bit isput to 1 in ALR (Alarm Reg-

ister), this bit generates automatically the trans­mission of two bytesmessage onto DOUTduring
Time slot 0 with :

– The first bit of the first byte at 0; the second

bit is at 0 and after the address bits of Alarm
Register.

– Thedataof the ALR(Alarm Register) is the sec-

ondbyte.

NB : When TSOR or Sa6R bit of the CAR1
(ComplementaryAlarm Register 1) is put to ”1”, it
generates a message in which there are address
and data of TSORR Register (if TSOR bit is not
masked), or address and data of Sa6RR register
(if Sa6R is not masked).

If the fouroccurencesto transmit a message are si­multaneous,thepriorityorderis:

Priority1 : Transmissionof Alarm

Registerdataif an alarm
has beendetected.

Priority2 : Transmissionof Register

data afterreadingmessage
fromremoteentity.

Priority3 : Transmissionof TSORR

data afterloadingof this
register.

Priority4 : Transmissionof Sa6RR

data afterloadingof this
register.

8.3 Stand AloneMode
Interruptsare notgenerated.

AL0, AL1 pins indicate the current state of three
alarms : LOF, AIS, A bit received and DOUT pin
indicates the current state of nine alarms during
time-slotzero (SeePar. 6.3).

13/46

STLC5432

Table 3: The registersand theirbits.

After

ADD

(Dec.)

Reset

(Hexa)

0 NOT USED
1 RESET 1 DUMMY REGISTER W 15
2 88 ALR 1 EXT1 AR SC LOF 915 AIS LOS R 15
3 FF AMR 1 MEXT1 MAR MSC MLOF M915 MAIS MLOS R - W 15
4 80 CAR1 1 EXT2 0 Sa6R TS0R ER CRCF WER R 15
5 FF CAMR1 1 MEXT2 Nu MSa6R MTS0R MER MCRCF MWER R- W 15
6 80 CAR2 1 PRSL PRSR MFNR MFR 0 SLC SKIP R 16
7 FF CAMR2 1 MPRSL MPRSR MMFNR MMFR Nu 1 MSKIP R - W 16
8 80 FCR1 1 F6 F5 F4 F3 F2 F1 F0 R 16

9 80 FCR2 1 F13 F12 F11 F10 F9 F8 F7 R 16
1080ECR11E6E5E4E3E2E1E0 R 16
11 80 ECR2 1 E13 E12 E11 E10 E9 E8 E7 R 16
1280PCR11P6P5P4P3P2P1P0 R 17
13 80 PCR2 1 P13 P12 P11 P10 P9 P8 P7 R 17
14 B8 ERTR 1 IT2 IT1 IT0 VT3 VT2 VT1 VT0 R - W 17
15 80 TS0RR 1 0 0 Sa4R Sa5R Sa6R Sa7R Sa8R R 17
16 9F Sa6RR 1 0 AR Sa5R Sa61R Sa62R Sa63R Sa64R R 17
17 X RES RESERVED: Avoid Addressing
18 9F TS0XR 1 WT AE Sa4X Sa5X Sa6X Sa7X Sa8X R - W 18
19 8F Sa6XR 1 WT Nu Nu Sa61X Sa62X Sa63X Sa64X R - W 18
20 X RES RESERVED: Avoid Addressing
21 90 SIGR 1 SHCR SIG STS4 STS3 STS2 STS1 STS0 R - W 18
22 80 LP4R 1 SLCR LP4 LTS4 LTS3 LTS2 LTS1 LTS0 R - W 18
23 84 CR1 1 MERA LTM 8KCR MCR1 MCR0 SELEX SELER R - W 20
24 80 CR2 1 DOHZ RDS1 RDS0 POL NR NX TM R - W 20
25 80 CR3 1 ASP Nu AISX ALS LP3 LP2 LP1 R - W 21
26 80 CR4 1 EQV AVT DEL DCP M2 M1 M0 R - W 21
27 80 CR5 1 TS0E APD NMF HCRD DPIS CENTER FROZ R - W 23
28 80 CR6 1 POLSa OSCD SaT Sa51 Sa50 Sa41 Sa40 R - W 23
29 80 CR7 1 AMI Sa81 Sa80 Sa71 Sa70 Sa61 Sa60 R - W 24
30 FF CR8 1 FILT SP Sa4P Sa5P Sa6P Sa7P Sa8P R -W 24
31 X RES RESERVED: Avoid Addressing
32 80 TCR1 1 SGV GTS5 GTS4 GTS3 GTS2 GTS1 GTS0 R - W 25
33 80 TCR2 1 SAV ATS5 ATS4 ATS3 ATS2 ATS1 ATS0 R - W 25
34 80 TCR3 1 CRCC EBC PELC PULS FASC ODTS TWI R - W 26

35 to 63 Reserved for the dietest: Avoid Addressing

Register

Name

bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

Read/

Write

Page

Nu = Notused.

14/46

STLC5432

9.1 Reset Register

70

1 Dummy Register

The software reset of the circuit is performed

This registercan be writtenor read.
When a bit of this register is set to 1, the corre-

sponding bit of the ALR register, which has the
same number, is masked and an interrupt cannot
be generatedby this bit.

when this register is addressed whatever the
value of its bits may be. Reading or writing is ir­relevant. All the programmable registers are con­figurated by the default value indicated in each
register description and the mechanism of multi­frame is launched in accordance with the proce­dure describedin the introduction.

9.2 ALR: AlarmRegister

70

1 EXT1 AR SC LOF 915 AIS LOS

After Reset = 88H

LOS Lossof Signal.

This bit is set to 1 whenten consecutive
zeros havebeendetectedbeforethe
HDB3/BINdecoder.

AIS Alarm IndicationSignal:

this bit is set to 1 in accordancewith G.775
when the incomingsignal is recived with
only two, or less, zero for two consecutive
doubleframeperiod (i.e.512 x 2bit).

915 Thisbit issetto 1 when 915 errored CRC

messageblocks have beenreceivedwithin
1 second.

LOF Loss of Frame AlignmentWord.

Whenat 1, the synchronizationis lost.

SC One second Clock.

This bit is set to one every second when
there is synchronization.The number of
faults which have been counted duringthe
previoussecond is in faultcounters FCR,
ECRand PCR.

AR A bit Received.

This bit is set to 1 whenthe bit 3of the
odd time slot zerohas been received
consecutivelytwo times at 1.

9.4 CAR1: ComplementaryAlarm Register 1

70

1 EXT2 0 Sa6R TS0R ER CRCF WER

AfterReset = 80H

WER Frame WordErrorRate.

This bit is at ”1”when the thresholdof fault
conditionhasbeenreached; this bit is at
”0” when the threshold of deactivatinghas
been reached.Thesetwo thresholdsare
indicatedby theerrorRate Threshold
Register(ERTR). The Error Rate function
is validatedwhen the synchronizationis
achieved.

CRCF CRC Frame.

After remultiframe time, this bit is at ”1”
when an eight frame blockhasbeen
receivedwith an error.

ER E Bit received.

ER bit is at ”1” during the frame 13
receivedwhen theE1 bit valueofthesame
frame13iszero.
ERbitisat ”1”duringtheframe15 received
whentheE2 bit valueof thepreviousframe
15iszero(E1 andE2 = first bitof timeslot
zeroin frames13 and15respective).

TS0R Time slot Zero Register.

Thisbitisat”1”whentheTS0RR Registerhas
been loadedin accordancewithCR8
registerand bit POLSa(CR6register).

Sa6R Sa6R Register.

This bit is put to one whenSa6RR
Registerhas beenloaded in accordance
with SaT bit (CR6 Register).

EXT2 EXTENSIONBit 2

This bit is at ”1” when one bit outof
CAR2 Registerbits hasbeen set to”1”.

EXT1 Extensionbit 1.

This bit is set to 1 whenone bit outof
CAR1Register bits isput to1.

9.5 CAMR1Complementary AlarmMask

9.3 AMR Alarm Mask Register

70

1 MEXT1 MAR MSC MLOF M915 MAIS MLOS

After Reset = FFH

Register 1

70
1 MEXT2

Nu MSaRmMTSORMERMCRCF MWER

At Reset = FFH

This registercan be reador written.

15/46

STLC5432

When a bit of this register is at ”1”, the CAR1

9.8 FCR1: Fault CounterRegister 1

Register bit which has the same number is
masked. The CAR1 bit which is masked do not
generate an interrupt.

70

1 F6F5F4F3F2F1F0

AfterReset = 80H

F0/6 7 less significantbits of theFCR counter.

9.6 CAR2:ComplementaryAlarmRegister2

70

1 PRSL PRSR MFNR MFR 0 SLC SKIP

After Reset = 80H

SKIP SKIP.

Afterframerecovery, this bit isat ”1”
when an entireframe (32words)

9.9 FCR2: Fault CounterRegister 2

70
1 F13 F12 F11 F10 F9 F8 F7

After Reset = 80H

F7/13 7 mostsignificantbitsoftheFCRcounter.

has beenignoredor hasbeen repeated
two times onto DOUT.

SLC Slow Local Clock.

This bit does not generateinterrupt.
Whenthe value of thisbit is 0, local clock
is fasterthantheremoteclock.
Whenthevalue is”1”,local clock isslower
thantheremoteclock(an entireframehas
been ignored).

MFR Multiframe recoveredwithin 400 ms.

Afterreframetime,if themultiframe is
recoveredwithin400 ms, MFR is set to ”1”.

MFNR Multiframe Not recoveredwithin 500 ms.

Afterreframetime, the circuit researches

If POL bit of CR2registeris at ”0”, the value of 14
bits fault counter is loaded into these registers
each second. If POL = 1, the registers are reset­ted after each access. (POL indicates the differ­ence between polling mode and interrupt mode,
see also CR2 register).

When the multiframe has not been recovered
within 400ms (MFNR = 1), these two registers in­dicate the number of errored bits of Frame Align­mentSignal receivedover one second period.

When the multiframe is recovered, these two reg­isters indicate the number of errored CRC blocks

receivedover onesecond period.
the multiframe during 500 milliseconds.
Afterthistime, ifthe multiframehas not
been recovered,MFNR is set at”1”. Then
the circuitis activatedwith the frame
recoveryonly, andthe AX bit(bit 3 ofthe
oddTimeSlot Zerotransmitted)is set at”0”.

PRSR PseudoRandom SequenceRecovered.

Whenthe PRSanalyzeris validated(SAV
= 1), PRSR bit is set at ”1” ifthesynchro­nizationis performed.

9.10 ECR1:E Bit CounterRegister 1

70

1 E6E5E4E3E2E1E0

AfterReset = 80H

E 0/6 7 lesssignificant bits of ECR counter

PRSL PseudoRandomSequenceLost.

PRSL, thisbit is set to ”1” when PCR1/2
(PRSCounter Register)hasreached2

14

9.11 ECR2:E Bit CounterRegister 2

detectedfaults.

70

1 E13 E12 E11 E10 E9 E8 E7

9.7 CAMR2: ComplementaryAlarmMask
Register2

AfterReset = 80H

E 7/13 7 most significantbits of the ECRcounter

70

1 MPRSL MPRSR MMFNR MMFR Nu 1 MSKIP

After Reset = FFH

This registercanbe read or written.
Bits: MMFNR, MMFR andMSKIP maskrespectively
bitMFNR,MFR andSKIPwhentheyareat”1”.

.
ECR1 and ECR2 are two registers associated to

ECR counter. Each second, the value of the
counteris loaded intothese register(POL = 0).

When the multiframe is recovered, these two reg­isters indicate the number of errored E bits re­ceivedover1 secondperiod.

16/46

STLC5432

9.12 PCR1: PRS Counter Register1

70
1 P6P5P4P3P2P1P0

After Reset = 80H

P0/6 7 lesssignificantbitsof thePseudoRandom

IT 0/2 Error Rate Inhibition Thresholdof WER

IT0/2 bitsgive thethresholdofdeactivating
the indicationof Alarm.Per default,WERis
setat ”0”when12 or less erroneous
FrameAlignmentWordsaredetected.
TheAlarmdeactivationrequirestheconfir­mationof theconditionforthefollowing2sec.

CounterRegister.

9.13 PCR2: PRS Counter Register2

70
1 P13 P12 P11 P10 P9 P8 P7

After Reset = 80H

P7/13 7mostsignificantbitsofthePseudoRandom

CounterRegister.

PCR1 and PCR2 are two registers associated to
PseudoRandomSequenceCounter.
When the PseudoRandom SequenceAnalyser is
validated, the counter indicates the number of er­roneus bits received after the synchronisation of

IT2 IT1 IT0

0
0
0

0

1
1
1
1

0
0
1

1

0
0
1
1

0
1
0

1

0
1
0
1

NB: If the threshold value of deactivatingthe indi­cation of Alarm is superior to threshold value of
activating the indication of Alarm, then the value
of deactivatingis irrelevant.

Number of erroneous

Frame Alignment words

received during2 seconds

the Pseudo Random Sequence.

8
9

10

12

14
16
20
24

9.14 ERTR: Error RateThreshold Register

70

1 IT2 IT1 IT0 VT3 VT2 VT1 VT0

After Reset = B8H

VT 0/3 Error Rate Validation Thresholdof WER.

VT0/3bits givethe thresholdof activating
theindication ofAlarm forerroneousFrame
Alignmentwords.
WERis set to ”1” only if the fault condition
isconfirmedwithinthe following2 seconds.

Number of erroneous

VT3 VT2 VT1 VT0

0

0

0

0

0

0

0

0

0

0

1

0

1

0

1

0

1

0

0

1

0

1

0

1

0

1

1

1

1

1

1

1

1

1

1

0

0

1

1

1

0

0

1

0

0

1

1

1

0

0

1

0

0

1

1

1

0

0

1

0

0

1

1

1

Frame Alignement

words received during

2 seconds

16
18
20
22
24
26
28
30

32

36
40
44
48
52
56
60

9.15TS0RR:TimeSlotZero ReceivedRegister

70

1 0 0 Sa4R Sa5R Sa6R Sa7R Sa8R

After Reset 80H

Sa4Rto Sa8R Bits 4 to 8 of theoddTime Slot

Zero(Sa4toSa8)receivedfromthe
line.Duringreframetime,thesebit
areat”1”.Sa4R toSa8R fixthe
contentofTS0 R Rinaccordancewi th
CR8Registerandbit POLSa(CR6
register)

9.16 Sa6RR:Sa6 Bits ReceiveRegister

70

1 0 AR Sa5R Sa61R Sa62R Sa63R Sa64R

After Reset = 9FH

Sa61Rto Sa64R
These four bits are received from Sa6 subchan-

nel.
When a new wordconstituted by these four bits is
detected in accordance with SaT (CR6 Regis­ters), a Sa6R interrupt is generated (a new word
can occureachmillisecond).

Sa5R.Thisbit is thesameasSa5RinTS0RRregister.
AR A bit received. It’s the same bit than the AR

bit of ALR register (see 9.2).

17/46

STLC5432

9.18 TS0XR: Time Slot Zerotransmit Register

STS0/4 SignallingTime Slot 0/4:

these five bits indicatewhich time Slot out

70

1 WT AE Sa4X Sa5X Sa6X Sa7X Sa8X

After Reset = 9FH

SIG SignallingValidated.

Sa4X to Sa8X Bits 4 to 8 ofeachodd TimeSlot

Zero to be transmittedonto theline
in accordancewith CR6and CR7

AE A bit totransmit.

AX bit to be transmittedontothe lineis given
by the logical ”or” of LOF (Loss of Frame),
WER(if thebitMERA isat 0, CR1register)
and AE (see fig 5).
AX(OddTS0Bit3)=AE + LOF+ WER NOT
MERA

WT Word to Transmit.Thisbit is readonly.

First Case FILT= 1.
AfterTS0XRwriting bymicroprocessorwith
WT=1,WTisresettedat”0”afterthree
consecutivetransmissionsofSa4Xto
Sa8Xbitsontotheline.

SecondCaseFILT = 0.
AfterTSOXR writingbymicroprocessorwith
WT=1,WTisresettedat”0”afterone
transmissionof bitslocatedinTS0XRregister.

of32to transmitandtoreceiveonBRD0and
BXDI pins respectively,when SIG bit is at 1.

ReceiverSide :
WhenSIGis at ”1”,the contents of Time

Slot selectedappearon the BRDO pin at
64 kb / s and its clock as so cia t e d o
the RCLO pin at 64kHz.

WhenSIGis at ”0”, the contentsof 32Time
slots receivedappear onto BRDO pin at
2 048 kb/s and clock associatedonto
RCLO pin at 2 048 kHz.

transmitterside :
WhenSIGis at ”1”, a bit stream at 64 kb/s

on BXDI pin will be introducedinto time
Slot,selectedby STS0to STS4bits, to
the line. The bit streamon the input BXDI
pin is clocked by clockat 64KHzdelivered
by BXDO pin (BXDIpin isan input and
BXDOpin is an output).

WhenSIGis at ”0”, the bit streamat 2048
kb/sonBXDIpinwillbeintroducedinto32
Time Slotstotheline.

SHCR: Synchronizationof High Clock Received.

9.19 Sa6XR: Sa6 Bits TransmitRegister

70

1 WT Nu Nu Sa61X Sa62X Sa63X Sa64X

After Reset = 8FH

Sa61X, Sa62X,Sa63X, Sa64X
These four bits are transmitted on subchannel

Sa6 in accordancewith CR6 andCR7 Registers.
WT Word to Transmit.Thisbit is readonly.

First Case SaT =1.
AfterSa6XRwriting by microprocessor,
WT=1.WTisresettedat”0”afterthree
consecutivetransmissionsof Sa61Xto

If DPIS (CR5) = 0:
SHCR= 1, DPLL receives RCLIsignal
from RCLIpin.
SHCR= 0, DPLL receives theremoteclock
recoveredfrom theline.
If DPIS (CR5) = 1:
SHCRis not taken into account.

DPIS SHCR

0 0 line
0 1 RCLI pin
1 0 DPI pin
1 1 DPI pin

Sourceof the signal at the DPLL

input:

Sa64Xbitsonto theline.
SecondCaseSaT = ”0”.

AfterSa6XRwriting by microprocessor,
WT= 1, WTis resettedat”0” afterone
transmissionof bits located in Sa6XR

9.22 LP4R: LoopBack 4 Register

Register.

70

1 SLCR LP4 LTS4 LTS3 LTS2 LTS1 LTS0

After Reset = 80 H

9.21 SIGR: SignallingRegister

70

1 SHCR SIG STS4 STS3 STS2 STS1 STS0

LTS 0/4Loo Back time Slot 0/4:

these five bits indicatewhich time slot out
of the32 is selected for the loopback.

18/46

After Reset = 90H

STLC5432

LP4 Loopback4

Whenthis bit is at ”1”, loop back 4 is
validatedduring Time Slot selected. The
loop back is locatedbetweenDOUT and
DIN pins.The loopbackis transparent
during the TimeSlot selected.DOUT
alwaysdelivers the contents of each Time
Slot.

SLCR Synchronizationof Low Clock Received

Relevantif LTM(CR1) = 0.

SLCR= 1, LCR output signal willbe syn­chronizedonce when MFR bit(or MFNR
bit) will go to ”1”. After synchronizing,the
falling edgeof LCR signal is in accord­ance withthe 6th bit of time slot 1 seen
at the input of the circuit.(LI1 pin or LI2
pin).The inputsignalis assumedwithout
jitter.
SLCR= 0, LCR output signal is free. The
LCRfrequencyis a submultipleof HCR
frequency.

DELAY BETWEEN INPUT SIGNAL (LI1 OR LI2) AND OUTPUT SIGNAL (LCR) AT 8KHz AFTER
SYNCHRONIZING (whenSLCR =1, LP4RRegister Bit)

19/46

STLC5432

9.23 CR1: Configuration Register 1

70

1 MERA LTM 8KCR MCR1 MCR0 SELEXSELER

After Reset = 84H

SELER Selectionof anexternalsignal side

receiver.
WhenSELER=1,the internal binary data
signalanditsclockassociatedarereplaced
by the externalbinary data signal and its
clock associated(respectivelyBRDI and
RCLI).

SELEX Selection of an external signal side

transmitter.
WhenSELEX= 1,the internal
binarydata signalis replacedby the
externaldata signal BXDI.

MCR0/1 HCR Frequency

HCR pin deliversa square wave

9.24 CR2: Configuration Register2

70

1 DOHZ RDS1 RDS0 POL NR NX TM

AfterReset = 80H

TM TransparentMode.

Forthetransmitter, whenthis bitis at 1,the
bitstreamreceivedonDIN pinis introduced
directly into theBinaryHDB3 encoder.
In thiscase, FSX(Frame Synchronization
Signal) fromthe pinis not used by the
transmitterandTimeSlot 0isnotknownbythe
transmitter.Thelogicalresultisthesameifthe
bit streamis introducedonto BXDI pin at
2048 kb/s.

For the receiver,when TMisat ”1”, every
bit receivedfromHDB3-BIN decoderis
connectedontoDOUT through the Elastic
Memory.Thesynchronizationis researched
andindicatedby thedifferentalarmregisters

MCR1 MCR0 HCR Frequency in kHz

0 0 2048
0 1 4096
1 0 8192
11

8KCR 8kHz ClockReceived

8KCR= 1

LCRpin delivers a squarewaveat
8kHz (Lowclockreceived)

8KCR0 = 0

LCRpindeliversasquarewaveat4kHz

LTM LineTermination Mode

WhenLTMis at ”1”, the jitter filter is not
validated.HCR andLCR pinsdeliver
signalsat a submultiplefrequency of the
frequencyapplied to XTAL1pin.
HCR frequencyis in accordancewith
MCR 0/ 1andLCRfrequencyisin accordance
with 8KCR.

WhenLTMis at ”0”, jitter filteris validated
andMCR andLCRpinsdelivercloksissued
fromDPLL in accordancewith MCR0/1
and 8KCR.

MERA MaskError rate

MERA= 0

WERbit (ErrorRateoverthreshold)
is taken into account to transmitA
bit and to force to 1 theDOUTpin.

MERA= 1

WERbit is ignoredby A bit trans­missionand DOUTpin.

NX PRBSTypeto betransmitted.

NR PRBStype received.

POL Fault Counter RegisterPolling.

butDOUT pindeliversthe received bit
streamwithouttakingintoaccounttheresult
ofthesynchronization.
BRDO andRCLOpinsprovidethebitstream
received fromthedecoder.

Whenthe generatorof PseudoRandom
BinarySequencyis validated(SGV=1):
if NX = 0, thelengthof sequenceis 2*15-1
bits
if NX = 1, thelengthof sequenceis 2*11-1
bits.

Whenthe Analyzerof PseudoRandom
BinarySequenceis validated(SAV = 1):
If NR = 0, thelengthof sequence received
is 2*15-1bits (O.151)
If NR = 1, thelengthof sequence received
is 2*11-1bits (O.152)

POL= 1

FCR1 and FCR2 registersor ECR1
andECR2registersorPCR1and
PCR2 registers are read by the
microprocessor(PollingMode).
FirstFCR1, orECR1,orPRC1,is
readthenFCR2, or ECR2,or PRC2,
mandatory.Thecontentsofa pair of
register sindi c atethenumberoffaults
occuredfromthelastreading of this
pairofregister.

POL=0

Thetwopairsofregistersindicate
thenumberoffaultsoccuredduring
thesecondwhichispassedjust
beforeInterruptSC.

20/46

STLC5432

RDS0/1Receive DataSelectBit 0/1

Whenthe PRSanalyseris validated
SAV= 1 (TCR2), Sequenceis checkedby
the analyserduring theTime Slot(s)
selectedbyTCR2.

RDS1 RDS0 Source

0 0 Sequencecomes from

Memory input.

0 1 Sequencecomes from

memory Output.

1 0 Sequencecomes from

DataInput (DINpin).Instead

ofsequence,”1” are

transmittedontotheline.

1 1 SequencecomesfromData

Input(DINpin).Sequenceis

transmittedontotheline.

Whenthe PRSgeneratoris validated,

ALS Alarm Line Signal to be transmitted.

AISX AlarmIndication signal.

ASP Alternate Single Pulse

9.26 CR4 ConfigurationRegister 4

data stream comingfrom thedecoder
HDB3-BIN,just beforeframe memoryinput.

Whenthis bit is at 1, AISor APS are
transmittedonto the line.

If ALS is at ”1”, and AISX is at ”1”:
AlarmIndicationsignal (All 1s) is transmit­ted onto the line.

If ALS is at ”1” and AISX is at ’0”:
Auxiliarypattern (0-1-0-1-0-1...)is transmit­ted onto the line.

IfASP= 1 TheL01 andL02outputsdeliver
pulseevery3.9microseconds.Ontheline,
onewillbeposi ti ve,thenextnegat iveandsoon.

SGV= 1 (TCR1 register),Sequenceis
transmittedbythegeneratorduring theTime
Slot(s)selected by TCR1.

RDS1 RDS0 Destination

0 X Sequence is transmitted

onto the line. Loopback 1

or 3 can be validated.

1 X Sequence is transmitted on

Data Out (DOUT pin).

DOHZ DOUT High Impedance

DOHZ= 1, DOUT pin is high impedance
DOHZ= 0, DOUT pin is in accordancewith
TS0Ebit of CR5 register.

70

1 EQV AVT DEL DCP M2 M1 M0

AfterReset = 80H

The first three bits of thisregister, M 0/2,must not
be changed by themicroprocessor if the serialµP
is selected, they can be programmedonly in par­allel interface mode. If Serial interface or Stand
Alone mode is chosen, then Multiplexes are at 2
048kb/s and local clock frequency may be either
2 048 kHz or 4 096 kHz.

NB : If parallel micro interface is selected, DOUT
will be valid afterwriting CR4 Register.

M 0/2 Multiplex DIN andMultiplexDOUT

9.25 CR3 Configuration Register 3

70

1 ASP Nu AISX ALS LP3 LP2 LP1

After Reset = 80H

LP1 Loop Back 1

Thisloopbackisthenearestto thelineside
pins.If LP1= 1 incomi ngdataarereplac edb y
outgoingdata.
IfAIS X= 0, loopbackistrans parent(outgoing
data is transmitted)
IfAIS X= 1, AlarmIndicationSi gnalis trans m i t ted.

DCP DoubleClock Pulse

LP2 Loop Back 2

Loopbacklocated between the HDB3/BIN
decoderoutputandtheBIN/HDB3encoder
input.Loop back2 is alwaystransparent.
If LP2 = 1 Data received from the line are
returnedto the line.

LP3 Loop Back 3

If LP3 = 1 Frames and Multiframesgenera-

DEL Delayed mode.

M2 = 1

Multiplexesareat8 192kb/s.Each
multiplexincludes128 Time Slots.
M0and M1 indicatetheTime Slots
selectedby thedevice.

M2 = 0 and M1 = 1

Multiplexesareat4 096kb/s.Each
multiplexincludes 64 Time Slots.
M0indicatestheTime Slotsselected
bythedevice.

M2 = M1 = 0

Multiplexesareat2 048kb/s.Each
multiplexincludes32 TimeSlots.

Whenthisbit is at ”1”, localclockfrequency
value is twice the data rate value.
Data In are shifted on the second falling
edge of the local clock (LCLK).
Whenthisbit is at ”0”, localclockfrequency
and data ratevalue have samevalue.
Datain areshiftedon thefalling edgeof the
local clock.

ted by the emitterare connectedinstead of

21/46

STLC5432

When DEL is at ”0”, Bit 0 of TS0
is indicatedby the risingedge of Frame
synchronizationsignal.

WhenAVT= 0,theadaptivefunctionis not
validated;receiving is performed if the
attenuationof the signalis lessthan6 dB.

WhenDEL is at ”1”, Bit 0 ofTS0 is delayed;
the rising edgeof FrameSynchronization
indicatesthe bitlocatedjust before Bit 0
TimeSlot0.

EQV EqualizerValidation.

WhenEQVisat ”1” internalequalizeris
validated (external capacitorsare required
at theLI1 and LI2 inputs).

AVT AdaptativeVoltage Threshold Validation.

WhenAVTis at 1, the adaptivevoltage
thresholdis validated.

WhenEQVisat 0, the equalizer is never
operating(external capacitorsarenot
required).

TABLE OF DIFFERENTLOCAL MULTIPLEX(with Parallel microprocessorinterfaceonly)

CONFIGURATION BITS Local Clock Multiplexes DIN DOUT

M2 M1 M0 DCP LCLK inkHz Data Rate in Kb/s Number of Time

0
0

0
0

0
0

0
0

1
1

1
1

0
0

0
0

1
1

0
1

0
1

0
1

2048
4096

4096
8192

4096
8192

2048 1 X32 TSn

4096 2 X32

Slots (TS)

accordance with

device 0 ≤ n ≤ 31

Time Slot in

the TSn of the

TS2n

TS2n+ 1

1
1

1
1

1
1

1
1

0
0

0
0

1
1

1
1

0
0

1
1

0
0

1
1

0
1

0
1

0
1

0
1

8192

16384

8192

16384

8192

16384

8192

16384

8192 4 X32

TS4n

TS4n+ 1

TS4n+ 2

TS4n+ 3

Ex : M2 = 1, M1 = 1, M0 = 0, each Multiplex includes 128 Time Slots, the data processed by the de­vice during the internal time Slot 3 are the dataconnectedto multiplexes during the external time slot
14 = 4X 3 + 2.

22/46

STLC5432

9.27 CR5 Configuration Register 5

70

1 TS0E APD NMF HCRD DPIS CENTER FROZ

After Reset = 80H

FROZ Frozen DPLL.

FROZ= 1, the DPLLisimmediatelyfrozen.
Id est: DPLLretainsits phaseand its
frequencywhile FROZ is at ”1”.

If the sinchronisationis lostor ifthe error
rate is over the programmedthreshold, the
DOUTpin is set at ”1”.
The bits 4 to 8of theincomingtime Slot
Zero(DINpin) aretransmittedontotheline
in accordancewithCR6 andCR7Registers.
Bits 1 to 3 are ignored.
TS0E= 0.

CENTER Crystal OscillatorRference.

CENTER= 1, DPLL is synchronisedby the
CrystalOscillator.
CENTER= 0, DPLL is synchronisedby the

- When ODD = 0, the contentsof
TimeSlot 1 to 31 are relativeto

the contents of even fr ame

receivedfromtheline.

DOUT is high impedanceduring
the time Slot Zero. Incomingbits
on DIN pin are ignored during
Time Slot Zero.

clock recoveredfrom the line or by the
signal appliedtoDPLL INPUT PIN (DPI)
in accordancewith DPIS.

DPIS DPLL Input Selection.

DPIS= 1, internalDPLLinputreceives the
signal appliedtoDPLL INPUT PIN (DPI)
DPIS= 0, internalDPLLinputreceives the
signal recoveredfrom the line.

HCRD HCRDisabled.

HCRD= 1, HCR pin is high impedance
HCRD= 0, HCR pin is low impedance.

NMF No Multiframe.

NMF = 1 the multiframe is not transmitted,
only theFrame AlignementSignal (FAS)
istransmitted onthe lineduringthetimeslot 0.
The receiveris notconcerned by this bit.
NMF = 0 the multiframe (MFAS)is trans­mittedwith the CRC4, theFrame Aligne-

9.28 CR6 ConfigurationRegister 6

70

1 POLSa OSCD SaT Sa51 Sa50 Sa41 Sa40

AfterReset = 80H

Sa40/Sa41

Sa41 Sa40

0 0 Bit Sa4X of TS0XR

0 1 Bit Sa4X of DIN

1 0 Reserved Code: Do not use
1 1 Reserved Code: Do not use

ForSubchannelSa4

in Transmission,

the source is:

Register

received during TS0

For Subchannel
Sa4 in Reception,
the destination is:

TS0RR Register

receives Bit Sa4R

and DOUT pin

delivers Bit Sa4R.

mentSignal (FAS)is transmitted in accord­ance withG.704.

APD Alarm Patternon DOUT.

Whenthis bit is ”1”, DOUT Pin delivers
AuxiliaryPattern: (0-1-0-1-0-1...).

TS0E DOUT enabledduring TimeSlot Zero.

In serialmicroprocessormode,this bitis
not significant:in this caseTimeSlot Zero
is used to exchangedata betweenthe
deviceand theremote serialinterface
microprocessor.
In parallel microprocessormode,TS0Ebit
is taken into account:
TS0E=1.

Sa4Rto Sa8Rbits of the TS0RR
RegisteraretransmittedontoDOUT
during the time SlotZero.The bits
1 to 3 ofthis same time Slot Zero

Sa50/Sa51

Sa51 Sa50

0 0 Bit Sa5X of TS0XR

0 1 Bit Sa5X of DIN

1 0 Reserved Code: Do not use
1 1 Reserved Code: Do not use

ForSubchannelSa5

in Transmission,

the source is:

Register

received during TS0

For Subchannel
Sa5 in Reception,
the destination is:

TS0RR Register

receives Bit Sa5R

and DOUT pin

delivers Bit Sa5R.

SaT SameBits Threetimes.

SaT = 1: if a newvaluefor the Sa5R,
Sa61R,Sa62R,Sa63Rand Sa64Rbitshas
beenreceivedthree timesidentical,these
bitsareloadedintoSa6RRregisteranda
Sa6Rinterruptis generated.

are ODD,SKIP, SLC.

- WhenODD = 1, the contentsof
Time Slot1 to31 arerelative tothe
contentsof oddframe received
fromthe line.

SaT=0: eachmillisecond theSa5R,Sa61R,
Sa62R,Sa63RandSa64Rbits areloaded
intoSa6RRregister anda Sa6Rinterruptis
generated.

23/46

STLC5432

Transmitterside:
SaT fixs the number of consencutive
transmissionsof Sa61 to Sa64 bits onto
theline beforeresettingWT (Sa6XRregister).
See definitionof WTbit in chapter9.19

OSCD Oscillator Disabled

OSCD= 1, The clock pulseappliedto
XTAL1 inputpincomesfrom an external
generator.Theinternaloscillatorisdisabled
to reduce powerconsumption.
XTAL2pinhas tobe left open.

OSCD= 0, The two pins of a crystalare
connectedto XTAL1pinandXTAL2pinin
accordancewith the application schematic
andtheinternaloscillatoris enabled.

POLSa = 1: Eachbit ofTS0RRregisteris reset

aftera readingcyclefrommicroprocessor
exceptifthe conditionto setthe bitat ”1”is
stillpresent.

POLSa = 0: Each bit of TS0RR Registeris always

resetaftera readingcyclefrom microproces­sor.(seealsoSPbitof CR8 Register).

Sa7PtoSa4P Samedefinitionas Sa8P
SP Single Polarity

accountif SP =1.
Sa8P=1, Sa8Rbit (of TS0RR Register)is

set at ”1”, in accordancewith FILT,
whenSa8 bitreceivedfromthe line
goes from”0” to ”1”.

Sa8P=0, Sa8Rbit (of TS0RR Register)is

set at ”1”, in accordancewith FILT,
whenSa8 bitreceivedfromthe line
goes from”1” to ”0”.

SP =1, Sa8P to Sa4P andPOLSa(CR6

Register)bits aretaken into
account. Sa8to Sa4 (changing
state)receivedfrom the lineare
stored into TS0RRRegister in
accordancewith FILT. When
TS0RR Registeris readby the
microprocessor,TS0RR is put to 0
in accordancewithPOLSa bit (CR6
register).

SP = 0, Sa8P to Sa4Pand POLSabits are

not taken into account.
Sa8 to Sa4 bits received from the

9.29 CR7 Configuration Register 7

70

1 AMI Sa81 Sa80 Sa71 Sa70 Sa61 Sa60

After Reset = 80H

Sa60/Sa61

FILT FILTERING

Receiverside:
FILT = 1 and SP = 1,

lineare storedintoTS0RRRegister
in accordancewithFILT. When
TS0RR Registeris readby the
microprocessor,TS0RR keepsits
contents.

Sa8Rto Sa4R bits of TS0RR

Sa61 Sa60

0 0 Bit Sa6X ofTS0XR
0 1 Bit Sa6X of DIN

1 0 Contents of Sa6XR

1 1 Reserved Code: Do not use

ForSubchannel Sa6

in Transmission,

the source is:

Register

received during TS0

Register

For Subchannel

Sa6 in Reception,

the destination is:

Sa60 and Sa61 are

not taken into

account: TS0RR
Register receives Bit
Sa6R and DOUT pin

delivers Bit Sa6R

Sa6RR Register

Registerare set at ”1”respectively
if a newstate has been received
three timesconsecutivelyfrom
eachchannelSa8toSa4proce ssed
separatelyone byone. A TS0R
interruptis generated.

FILT = 0 and SP = 1,

Sa8Rto Sa4R bits of TS0RR
Registeraresetat”1”respectivelyif
a new state has been received
twice consecutivelyfrom each
channelSa8 to Sa4 processed
separatelyone byone. A TS0R

Sa70/Sa71:samedefinitionas Sa40/Sa41.
Sa80/Sa81:samedefinitionas Sa40/Sa41.

FILT = 1 and SP = 0,

AMI Alternate Mark Inversion.

AMI = 0, select HDB3 codeon the line.
AMI = 1, select AMI code on the line.

9.30 CR8 Configuration Register 8

70

1 FILT SP Sa4P Sa5P Sa6P Sa7P Sa8P

After Reset = FFH

Sa8P Sa8 Bit Polarity.This bit istaken into

FILT = 0 and SP = 0,

Transmitterside:
See TS0XRregister definition chapter9.18.

interruptis generated.
Sa8 to Sa4 bits received from the

lineand processedindependently
arestored intoTS0RRRegister
if one new bit has been received
three timesidenticallyat least. A
TS0R interruptis generated.

Sa8 to Sa4 bits received from the
lineare storedintoTS0RRRegister
each 250ms withoutprocessing.A
TS0R interruptis generated.

24/46

STLC5432

9.32 TCR1: Test Configuration Register1

70

1 SGV GTS5 GTS4 GTS3 GTS2 GTS1 GTS0

After Reset = 80H

SGV SequenceGeneratorValidated.

Sequence(PRBS) providedby theinternal
generator(see Table).

WhenSGVis at ”1”,the generatorprovides
PseudoRandom Binary Sequence in
accordancewithNX bit.WhenSGVis at 0,
the generatoris not validated.

GTS0 to GTS5 Time Slot associated to generator.

These 6 bits indicate TimeSlot(s)
selectedtotransmit the Pseudo
Random Binary

GTS5 GTS4 GTS3 GTS2 GTS1 GTS0

000000AlltheTime Slots except TS0
0 X X X X 1 All the Time Slots including TS0
100000Notuse
100001TS1
100010TS2

↓↓↓↓↓↓↓

111110TS30
111111TS31

Time Slot(s) selected to transmit

PRBS

9.33 TCR2: Test Configuration Register2

checksthe sequence.

SAV SequenceAnalyzerValidated.

70

1 SAV ATS5 ATS4 ATS3 ATS2 ATS1 ATS0

After Reset = 80H

ATS0 to ATS5 TimeSlot associatedto Analyzer.

These 6 bits indicate TimeSlot(s)
selectedtoreceive the Pseudo
Random Binary

WhenSAVis at ”1”, the analyzeris
validatedandthecounter ECR1-ECR2
(14 bits)is associatedto analyzer.The
length of PRBS is in accordancewith NR
bit. Afterthe sequenceisrecoveredby the
analyzer. PRSR is set at ”1”
(ComplementryAlarm
Register);theassociatedcounterindicates
the number of faults received.

Sequence(PRBS). The internal analyzer

ATS5 ATS4 ATS3 ATS2 GTS1 GTS0 Time Slot(s) selected to receive PRBS

0 0 0 0 0 0 All theTime Slots except TS0
0 X X X X 1 All theTime Slots including TS0
1 0 0 0 0 0 Not use
100001TS1
100010TS2

↓↓↓↓↓↓↓

1 1 1 1 1 0 TS30
1 1 1 1 1 1 TS31

25/46

STLC5432

9.34 TCR3 Test Configuration Register3

70

1 CRCC EBC PELC PULS FASC ODTS TWI

After Reset = 80H

TWI TSOcorruptedTWICE.

IfFASC=1andTWI=1, Time Slot0 selected
by ODTSis corruptedtwiceonly.
If FASC=1and TWI=0,TimeSlot0 selected
by ODTSis corruptedthreetimes only.

PELC Pulses transmittedontheline are corupted

ODTS OddTime Slot 0

If FASC=1andODTS=1, Odd Time Slot
zerois transmittedwith Bit 2 at ”0”.
If FASC=1andODTS=0, Even Time Slot

EBC E BitCorrupted.

Zerois transmittedwith Bit 2 at ”1”.

FASC FrameAlignment Signal Corrupted.

In accordancewith ODTS and TWI.
IfFASC= 1 ,Time Slot0transmittediscorr u p ted.
Aftertransmitting twiceor threetimes

CRCC CRC4 corrupted

consecutively,FASCchangesfrom”1”to ”0”.

PULS PULSE

frame 0 and frame 1. If PELC=1 and
PULS=0,nopulsesaretransmittedduring
16time-bit(7,8microseconds).

Secondcase : SGV= 1 (TCR2Register)
PULSE is ignored;if PELCchanges ”0” to
”1”, one pseudorandomsequencebit
transmittediscorrupted.Aftertransmitting
corruptedbit,PELCchanges”1”to”0”.

in accordancewith PULSand SGV (TCR2
Register).After transmittingonce time,
PELCchanges from”1” to ”0”.

If EBC=1,E bit of the next frame 13 and E
bit of the next frame 15 will be transmitted
at ”0”.Aftertransmittingoncetime,EBC
changesfrom”1”to ”0”.

WhenCRCC is at ”1”, CRC4 transmitted
into multiframeis continuouslycorrupted.

First case: SGV = 0 (TCR2 Register)
If PELC=1and PULS=1,512 consecutive
pulsesare transmittedon theline during

26/46

Figure 3: Connectionswith and without InternalEqualizer.

33pF 33pF32768MHz

STLC5432

(*)

0V 0V

100pF

XTAL1 XTAL2

LI1

60Ω

Zc=120Ω

60Ω

VT

LI2

100nF 10µF

0V

(*)

15Ω

STLC5432

100pF

LO1

Zc=120Ω

15Ω

LO2

(*) To be inserted for the internal Equalizer

Figure 4: STLC5432LineInterface Configurations(CEPT 120Ω or 75Ω)

VCCD1
VCCD2
VCCA

100nF 10µF
GNDD
GNDA

7mA max

AL1

AL0

D93TL048C

+5

0V

+5

TX

RX

LO1

LO2

LI1

V

LI2

Z = 120Ω

Z=75Ω

AUTOMATIC EQUALIZER

CONFIGURATION

15Ω

15Ω

60Ω

T

60Ω

0.1µF10µF

1:2

1:1

120Ω

120Ω

LO1

LO2

LI1

V

LI2

15Ω

15Ω

60Ω

T

60Ω

0.1µF10µF

1 :1.57

2 :1.57

75Ω

75Ω

LO1

LO2

LI1

V

LI2

15Ω

120Ω

or

75Ω

CONFIG

15Ω

100pF

60Ω

T

60Ω

100pF

0.1µF10µF

120Ω

or

75Ω

CONFIG

D93TL070A

27/46

STLC5432

Figure 5: Main Alarm Processing

LINE STATE REGISTERS

RECEIVING

ALARMS

DETECTED

LOS

AIS

915

LOF

AR

WER

ALARMS

TRANSMITTED

ODD TS0

BIT

3

Ax

or

Figure 6: DIN and DOUT During Time slot 0.

SA pin: 0V SA pin: 5V

Serial

Interface

P0 + P1 = 0

During

Time Slot 0:

IF TSOE = 0
During Time Slot
Dout pin is High Z.

Parallel Interface: P0 + P1 # 0 Stand Alone

(CR5)

0:

and

(TSOXR)

AE Bit

MERA
(CR1)

ALR

ALARMS

REGISTER

Bit 0

Bit 1

Bit 2

Bit 3

Bit 5

D93TL050B

CAR1

COMPLEM.

ALARM

REGISTER

Bit 0

28/46

Dout

pin

delivers

messages

and

Din

pin

receives

messages

IF TSOE =
During Time Slot
Dout pin delivers consecutively:

ODD = 1The contents of31 Time Slots is related
odd framereceived from the line.

ODD = 0The contents of31 Time Slots is related
even frame received from the line. (See Figure

Din pin receives eight bits:

1

0:

ODD SKIP SLC Sa4R Sa5R Sa6R Sa7R Sa8R

X X X Sa4E Sa5E Sa6E Sa7E Sa8E

6a).

to

to

During Time Slot
Dout pin delivers eight alarms

SLC SKIP AR MFNR LOF B AIS LOS

Din pin is ignored during Time Slot 0

0:

D93TL051E

Figure 6a: DOUT during Timeslot 0 (Bits 1 to 3)when TS0E = 1 (CR5)

Without skip

Odd frame n - 1 Even frame n Odd frame n + 1 Even frame n + 2

STLC5432

ODD = 1

SKIP = 0

SLC = X

ODD = 0
SKIP = 0

SLC = X

With skip and loss of Even framen

Odd frame n - 1 Odd frame n + 1 Even frame n + 2 Odd frame n + 3

ODD = 1

SKIP = 0

SLC = X

ODD = 1
SKIP = 1
SLC =1

With skip and duplicationof Oddframe n

Even frame n- 1 Odd frame n Odd frame n Even frame n+ 1

ODD = 0
SKIP = 0
SLC = X

ODD = 1
SKIP = 0

SLC = X

ODD = 1
SKIP = 0

SLC = X

ODD = 0
SKIP = 0
SLC =1

ODD = 1
SKIP = 1

SLC = 0

ODD = 0

SKIP = 0

SLC = X

ODD = 1
SKIP = 0
SLC = 1

ODD = 0
SKIP = 0
SLC = 0

29/46

STLC5432

Figure 7: DIN/DOUTmultiplex during Time Slot 0 - Serial Microprocessor InterfaceMode.

05162734BIT NUMBER

A ADDRESS REGISTER

D DATA

TWO CONSECUTIVEWRITE CYCLES

TSO

DIN

A0/5

ADA

125µs 125µs

READ CYCLE IDLE or WRITECYCLES NEW READ CYCLE

DIN

A

A

0

1RA20A3A4

D

D

1

D

21D3D4

IDLE

0

11111111

THE BITS ARE TRANSMITTED TO MULTIPLEX IN ORDER, BIT 1 FIRST

TSO

D0/6

A

R/W

5

D

D

5

6

0

100

TSO
A0/5

00

125µs

WRITE CYCLE 250µs

1111111110A0/5 00 11111111A0/5 10A0/5

2nd WRITE CYCLE

D0/6 1

D

D93TL053A

DOUT

30/46

125µs n x125µs

INTERRUPT MESSAGE

ALARM

REGISTER

ADDRESS

250µs

D0/6 110A0/5

ALARM

REGISTER

DATA

A0/5 1 0 11111111

REGISTER

ADDRESS

READ CYCLE

250µs

IDLE

1

REGISTER

DATA

D93TL052A

Figure 8: Jitter TransferCharacteristic (CCITTI431)

Gain

(dB)

x
0

y

STLC5432

20dB/dec

f

a

f

b

f

c

D94TL134

Carrier frequency (logarithmic scale)

YXf

–19.5dB 0.5dB 10Hz 40Hz 400Hz 100kHz

Figure 9:

Level 1 - Level 2 Process withParallelInterfaceµP.

DOUT

2Mb/s

a

TS0 Z

TS16

LEVEL 1

S2/T2

PRCD

DIN

TS16

5451

HDLC

f

b

TS0

5451

HDLC

f

c

TS0

TS16 Z

LEVEL 2

f

SYSTEM

d

f

d

PARALLEL

INTERFACE

ST9

µP

64Kb/s

LAP D POINT TO POINT

SIGNALLING

D93TL055A

31/46

STLC5432

Figure 10: PrimaryRate ControllerDevice PRCD - TEmodewith serial Microprocessor

XTAL

32764KHz

Figure 11:

XTAL1 XTAL2

2Mb/s

INTERFACE

S2/T2

RECEIVER

EMITTER

PRCD

LTM=0 (ConfigurationRegister1)

FourSTLC5432 in LT Mode

MASTER CLOCK

32764KHz

XTAL1

STLC5432

XTAL1

STLC5432

MEMORY

STLC5432

HCR LCR

DOUT 0

LCLK

LFSX/R

DOUT 1

LCLK

LFSX/R

DIN

DIN

HCR LCR

LFSR

DOUT

LCLK

LFSX

DIN

8MHz

8KHz

8Mb/s

FRAME

SIGNAL

SYSTEM

SWITCHING

NETWORK

8Mb/s

4KHz 4096KHz

NETWORK

µP

D93TL056C

BIT CLOCK

32/46

XTAL1

STLC5432

XTAL1

STLC5432

DOUT 2

LCLK

LFSX/R

DIN

DOUT 3

LCLK

LFSX/R

DIN

LTM=1 (ConfigurationRegister1)

D93TL057C

STLC5432

Figure 12:

ETSINT1 Option 2

DIN

CRC4

GENERATOR

MULTIFRAME

FRAME &

Bits: A, Sa 4, 7 & 8

CRC4

GENERATOR

EBIT

MESSAGE

STLC5432

Sa 5, Sa 61 to Sa 64

SIDE

NETWORK

CRC4

CHECK

RECEIVER

CRC4

FRAME &

DOUT

ALIGNMENT

MULTIFRAME

LOF

Bit: E, LOS,

Bits: A, Sa 4 to Sa 8

D93TL058A

SLOTS

1to31

TIME

DOUT

LOF

Sa 4 to Sa 8

Bits: E, LOS,

CRC4

ALIGNMENT

MULTIFRAME

FRAME &

LOOPBACK 1

STLC5432

CRC4

CHECK

T

SLOTS

TIME

EMITTER

EBIT

CRC4

GENERATOR

1to31

DIN

CRC4

FRAME &

MESSAGE

Sa 61 to Sa 64

GENERATOR

MULTIFRAME

P

µ

ST9

REFERENCE

33/46

STLC5432

Figure 13:

SynchronizationAlgorithm

LOF =

1

FRAME

RESEARCH

FRAME

YES

0

LOF =

VALIDATED.

RESEARCH

FRAME

STARTS.

DOUT DELIVERS ”ALL

NO

TIMER OUT 400ms

MULTIFRAME

ALIGNMENT RECOVERY

LOSS OF

FRAME

Ax = 1;Ex = 0

ALIGNMENT

RECOVERY

DOUT IS

Ax = 0;Ex = 0

MULTI

1s”

NO NO

FRAME

ALIGNMENT

LOST

YESYES

YES

MFR = 1

FCR 1/2 COUNTER

VALIDATED TO COUNT

CRC4 BLOCKS

ECR 1/2 COUNTER

VALIDATED TO COUNT

E BIT

CRC4

RECEIVED FALSE

ALIGNMENT

RECEIVED

FALSE

RECEIVED

AT ”0”

915

BLOCK

NO

FRAME

LOST

YES YES

IS

IS

NO

TIME

OUT

400ms

EXPIRED

YES

MFNR = 1

FCR 1/2 COUNTER

VALIDATED TO COUNT

OF FRAME

SIGNAL

ALIGNMENT

RECEIVED

FALSE

FRAME

ALIGNMENT

LOST

NO

IS

BITS

NO

D93TL059B

34/46

STLC5432

Figure 14:

LOF

MFR

MFNR

ThreeCases of Synchronization.

TYPICAL CASE

500µs max 6ms max

OLD EXISTINGEQUIPMENT CASE

LOF

500µs max

MFR

MFNR

PARTICULAR CASE: SPURIOUS FAS

LOF

500µs max 8ms min - 400ms max

MFR

MFNR

400ms max

D93TL060B

35/46

STLC5432

Figure 15:

PseudoRandom SequenceAnalyzer Algorithm.

START

SAV =1

YES

PRS

DURING ALL THE

TIME SLOTS

YES

NO

NO

MFNR + MFR

=1

YES

NO

NO

LOF = 1

SAV SEQUENCE ANALYZER VALIDATED
LOF LOSS OFFRAME
MFR MULTIFRAME RECOVERED
MFNR MULTIFRAME NOT RECOVERED
PRSR PSEUDO RANDOM

SEQUENCE RECOVERED

D93TL061A

YES

PSEUDO RANDOM

SEQUENCE RESEARCH

PRS

RECOVERED

YES

PRSR

INTERRUPT

NO

36/46

Figure 16: TransmitterSide Timing

STLC5432

SIG = 0 DATA RATE AT 2048Kb/s

LCLK

(CLOCK)

tpd

BXDO

(DATA)

BXDI

(DATA)

SIG = 1 DATA RATE AT 64Kb/s

BXDO

(CLOCK)

BXDI

(DATA)

488ns

t

H

ts

15.6µs

t

H

ts

D93TL062B

Figure 16a: TransmitterSide: Delayon BXD0 pin

Example applied to DIN pin withData Rate at 2048Kb/s

LFSX

LCLK

DIN

BXDO

BXDO output has 2 LCLK pulse of delay from DIN input

BIT 254 BIT 255 BIT 0 BIT 1 BIT 2

BIT 253 BIT 254 BIT 255 BIT 0 BIT 1

D96TL254

37/46

STLC5432

Figure 17: ReceiverSide Timing

RCLO

(CLOCK)

BRDO

(DATA)

RCLI

(CLOCK)

BRDI

(DATA)

td

td

T1/2

T

T1/2

T’

T’1/2

t

H

ts

T’1/2

D93TL063B

SIG = 0 T = 488ns±61
SIG = 1 T = 15.6µs±61

T’ = 488ns±61 (RCLI e BRDI not used)

(2048Kb/s)

(64Kb/s)

Figure 18: HCR and LCR versus configurationbits.

DPI

RCLI

RECOVERED

CLOCK

FROM THE LINE

RCLO

SHCR

DPIS

CENTER

FROZEN

1

1

DPLL

3

2,4 & 8M

LTM

3

XTAL2

Q=32764KHz

XTAL1

DIVIDER

3

2,4 & 8M

1

38/46

MCR0/1

8KCR

SELECT

2

DIVIDER

2,4 &8MHz

4 & 8KHz

HCR

LCR

D95TL232A

Figure 18a: High Clockand LowClock in LTand TE Mode

t=30.5ns

XTAL1

LT MODE ONLY

{

HCR

LCR

tpd

td td td td

LTM =1 LT MODE HCRAND LCR ARE GENERATED BY CLOCK APPLIED TOXTAL1 PIN. JITTER FILTER IS NOT VALIDATED
LTM =0 LE MODE HCRAND LCR CLOCK ARE RECOVERED FROM THE LINEVIA JITTER FILTER

THCR

THCR/2 THCR/2

8MCR THCR

1

(8MHz)

(4MHz)

122ns

0

244ns

TLCR TLCR

8KCR TLCR

1

(8MHz)

0

(4KHz)

STLC5432

tpd

TL

125µs

250µs

D93TL064C

Figure 19:

DoubleClock Pulse Timing.

LCLK

t

H

LFSX
LFSR

DOUT

DIN

DCP = 1

DOUBLE CLOCK PULSE
T = 244ns MULTIPLEX AT 2Mb/s

T = 122ns MULTIPLEX AT 4Mb/s
T = 61ns MULTIPLEX AT 8Mb/s

ts

T

BIT 0; TS 0

T

tpd tpdz

t

H

ts

D93TL065A

39/46

STLC5432

Figure 20: SingleClock Delayed Mode.

LCLK

LFSX
LFSR

DOUT

DIN

BIT n

T

t

H

ts

tpd tpdz

t

ts

H

DCP = 0

DEL = 0 NOT DELAYED MODE

DEL = 1 DELAYED MODE

Figure 21: MultiplexDiagram

LCLK

DOUT 0

DOUT 1

DOUT 2

SINGLE PULSE
T = 488ns MULTIPLEX AT
T = 244ns MULTIPLEX AT

2Mb/s
4Mb/s

T = 122ns MULTIPLEX AT 8Mb/s

BIT n IS THE FIRST BIT OF THE FRAME (125µ
BIT 0 TIME SLOT ZERO (LIKE GCI)

BIT n IS THE LAST BIT OF THE FRAME (125µs)

D93TL066A

s)

40/46

DOUT 3

3.9µs

D93TL067

EX: FOURST5432 OUTPUTS WHEN CONNECTED TOTHE SAME MULTIPLEX AT 8Mb/s

Figure 22: CCITTG703HDB3 Pulse Template

20%

10%

V=100%

10%

20%

50%

STLC5432

269ns

(244 + 25)

194ns IDEAL PULSE

(244 - 50)

244ns

Figure 23:

219ns

10%

0%

10%

D93TL068

(244 - 25)

20%

488ns

(244 +244)

AllowedJitter at the TE and LT Inputs (CCITT I431)

A

0

A

1

PEAK TO PEAK JITTER

AMPLITUDE (UI)

A

2

0

f

f

0

1

JITTER FREQUENCY (LOGARITHMIC SCALE)

f

2

10%

10%

CCITT 32540

20dB/DECADE SLOPE

f

3

f

4

D93TL069A

A

0

A

1

A

2

f

0

f

1

f

2

f

3

f

4

20.5 IU 1.0 0.2 IU 12 x10-6Hz 20Hz 3.6kHz 18kHz 100kHz

41/46

STLC5432

MultiplexedMotorola-like µP bustiming. (P0= 0V; P1= 5V)

t

WAS

AS

t

WDS

t

ASDS

DS

R/W

t

RWS

t

RWH

t

CSS

t

CSH

CS

AD0/7

Signal name Corresponding pin

CS CS (35)

AD0/7

AS/ALE (13)AS
DS/RD (21)DS
R/W/WR (26)R/W

A/D0 to

A/D7

( 4 ........30)

t

AAStAAH

ADDRESS

VALID

t

DV

D93TL071B

READ DATA

VALID

t

DWS

WRITE DATA

VALID

t

DF

t

DWH

AD0/7 READ

CYCLE

WRITE

AD0/7

CYCLE

Symbol Parameter Min. Max. Unit

t

WAS

t

WDS

t

ASDS

t

RWS

t

RWH

t

CSS

t

CSH

t

AAS

t

AAH

AS Pulse Width 30 ns
DS Pulse Width 110 ns
AS low to DS high 10 ns
R/W to DS setup 20 ns
R/W hold after DS 10 ns
CS to DS setup 20 ns
CS hold after DS 10 ns
Address to AS setup 20 ns
Address hold after AS 10 ns

READ CYCLE

Symbol Parameter Min. Max. Unit

t

DV

t

DF

Data Valid after DS 80 ns
Output Flat Delay 25 ns

WRITE CYCLE

Symbol Parameter Min. Max. Unit

Data to DS setup 35 ns
Data Hold after DS 10 ns

42/46

t

DWS

t

DWH

STLC5432

MultiplexedST9-like

AS

DS

R/W

CS

AD0/7

Signal name Corresponding pin

CS CS (35)

AD0/7

P bus timing.

µ

t

WAS

AS/ALE (13)AS
DS/RD (21)DS
R/W/WR (26)R/W

A/D7

A/D0 to

( 4 ........30)

(P0= 5V; P1 = 0V)

t

ASDS

t

RWS

t

CSS

t

AAStAAH

ADDRESS

VALID

t

DV

D93TL072B

t

WDS

READ DATA

VALID

t

DWS

WRITE DATA

VALID

t

DF

t

t

DWN

RWH

t

CSH

AD0/7 READ

CYCLE

WRITE

AD0/7

CYCLE

Symbol Parameter Min. Max. Unit

t

WAS

t

WDS

t

ASDS

t

RWS

t

RWH

t

CSS

t

CSH

t

AAS

t

AAH

AS Pulse Width 30 ns
DS Pulse Width 110 ns
AS high to DS low 10 ns
R/W to DS setup 20 ns
R/W hold after DS 10 ns
CS to DS setup 20 ns
CS hold after DS 10 ns
Address to AS setup 20 ns
Address hold after AS 10 ns

READ CYCLE

Symbol Parameter Min. Max. Unit

t

DV

t

DF

Data Valid after DS 80 ns
Output Flat Delay 25 ns

WRITE CYCLE

Symbol Parameter Min. Max. Unit

t

DWS

t

DWH

Data to DS setup 35 ns
Data Hold after DS 10 ns

43/46

STLC5432

MultiplexedIntel-like µP bus timing. (P0= 5V; P1= 5V)

READ CYCLE

t

WA

ALE

t

RR

CS.RD

t

t

LA

AL

ADDR DATA

t

RD

t

DF

Signal name Corresponding pin

AS/ALE (13)ALE
CS (35) & DS/RD(21)CS.RD
CS (35) & R/W/WR(26)CS.WR

A/D7

AD0/7

t

RI

A/D0 to

( 4 ........30)

WRITE CYCLE

t

WW

t

WI

CS.WR

tDWt

WD

AD0/7

DATA DATA

D93TL073B

READ CYCLE (Multiplexed Intel Mode)

Symbol Parameter Min. Max. Unit

Address Hold After ALE 10 ns
Address to ALE Setup 20 ns
Data Delay from RD 80 ns
RD Pulse Width 110 ns
Output Float Delay 25 ns
RD Control Interval 70 ns
ALE Pulse Width 30 ns
CS to RD or WR set-up t
CS hold after RD or WRt

CSS

CSH

20 ns
10 ns

t
t

t
t
t

t

LA

t

AL
RD
RR

t

DF

t

RI

WA
CSS
AAH

WRITE CYCLE(Multiplexed Intel Mode)

Symbol Parameter Min. Max. Unit

WR Pulse Width 60 ns
Data Setup to WR 35 ns
Data Hold after WR 10 ns
WR Control Interval 70 ns

44/46

t

t
t

WW

DW

WD

t

WI

TQFP44 (10 x 10) PACKAGEMECHANICAL DATA

STLC5432

DIM.

mm inch

MIN. TYP. MAX. MIN. TYP. MAX.

A 1.60 0.063
A1 0.05 0.15 0.002 0.006
A2 1.35 1.40 1.45 0.053 0.055 0.057

B 0.30 0.37 0.45 0.012 0.014 0.018

C 0.09 0.20 0.004 0.008

D 12.00 0.472
D1 10.00 0.394
D3 8.00 0.315

e 0.80 0.031

E 12.00 0.472
E1 10.00 0.394
E3 8.00 0.315

L 0.45 0.60 0.75 0.018 0.024 0.030

D

D1

2333

34

B

44

1

e

TQFP44

22

E3D3E1

12

11

E

L1

L

0.10mm
.004

Seating Plane

B

K

A

A2

A1

C

45/46

STLC5432

Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the
consequences of use of such information nor for any infringement of patents or other rightsof third parties which may result from its use. No
license is granted by implication or otherwise under any patent or patentrights of SGS-THOMSONMicroelectronics. Specification mentioned
in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied.
SGS-THOMSON Microelectronics products arenotauthorized for useas criticalcomponents in lifesupport devicesor systemswithoutexpress
written approval of SGS-THOMSON Microelectronics.

 1996SGS-THOMSON Microelectronics – Printed inItaly – AllRights Reserved

SGS-THOMSON Microelectronics GROUP OF COMPANIES

Australia - Brazil- Canada- China - France - Germany - HongKong - Italy- Japan -Korea - Malaysia- Malta - Morocco - The Netherlands -

Singapore - Spain - Sweden - Switzerland- Taiwan - Thailand - UnitedKingdom - U.S.A.

46/46