Datasheet STLC5048 Datasheet (SGS Thomson Microelectronics)

FOUR CHANNEL CODEC AND FILTER

■

FULLY PROGRAMMABL E MONOLITHIC 4
CHANNEL CODEC/FILTER

■

SINGLE +3.3 V SUPPL Y

■

A/m LAW PROGRAMMABLE

■

LINEAR CODING (16 BITS) OPTION

■

PCM HIGHWAY FORMAT AUTOMATICALLY
DETECTED:1.536 or 1.544 MHz2.048, 4.096,
8192 MHz

■

TWO PCM PORTS AVAILABLE

■

TX GAIN PROGRAMMING: 33dB RANGE;
<0.01dB STEP

■

RX GAIN PROGRAMMING:42dB RANGE;
<0.01dB STEP

■

PROGRAMMABLE SLIC INPUT IMPEDANCE

■

PROGRAMMAB LE TRANSHYBRI D BALANCE
FILTER

■

PROGRAMMABLE EQUALIZATION
(FREQUENCY RESPONSE)

■

PROGRAMMABLE TIME SLOT ASSIGNMENT

■

DIGITAL AND ANALOG LOOPBACKS

■

SLIC CONTROL PORTSTATIC (16 I/Os)
DYNAMIC (12 I/Os + 4 CS)

■

BUILT-IN TEST MODE WITH TONE
GENERATION , MC U ACC ESS TO PCM DATA

■

64 TQFP (10X10mm) PACKAGE

■

PROGRAMMABLE SLIC LINE CURRENT
LIMITATION

■

PROGRAM M A BL E S LIC OF F- HOOK
DETECTION THRESHOLD

DESCRIPTION

The STLC5048 is a monolithic fully programmable 4
channel CODEC and filter. It operates with a single
+3.3V supply.

The analog interface is based on a receive output

STLC5048

FULLY PROGR AMM A B LE

TQFP64 (10x10mm)

ORDERING NUM BER: STLC 5048

buffer driving the SLIC RX input and on an amplifier
input stage normally driven by the SLIC TX output.
Due to the single supply voltage a midsupply refer­ence level is generated internally by the device and
all analog signals are referred to this level (AGND).
The PCM interface uses one common 8KHz frame
sync. pulse for transmi t and r eceive dir ection. The bit
clock is automatically detected between four stan­dards: 1.563/1.544MHz, 2.048MHz, 4.096MHz,
8192MHz.

Two PCM port are provided: the channels can be
connected to port A or/and B.

Device programmability is achieved by means of
several registers and commands allowing to set the
different parameters like TX/RX gains, line imped­ance, transhybrid balance, equalization (frequency
response), encoding law (A/
independent channels power up/down, loopbacks,
PCM bits offset.

The STLC5048 can be programmed via serial inter­face running up to 8 MHz. One interrupt output pin is
also provided.

A GUI interface is also available to emulate and pro­gram the coefficients for impedance synthesis, echo
cancelling and channel filtering.

µ

), time slot assignment,

January 2003

1/45

STLC5048

BLOCK DIAGRAM

ANALOG FRONT END

VFRO0

VFX10

VFRO1

VFX11

VFRO2

VFX12

VFRO3

VFX13

VCC VEE

D/A

CH0

GR0

A/D

CH0

GX0

D/A

CH1

GR1

A/D

CH1

GX1

D/A

CH2

GR2

A/D

CH2

GX2

D/A

CH3

GR3

A/D

CH3

GX3

VDD VSS SUB CAP M1 M0

DIGITAL PROCESSOR

16

16

A/U LAW

ENCODER

8

PLL

BLOCK

8

BIAS

GENER.

SLIC
THR

A/U LAW

DECODER

INTERPOLAT.
DECIMATORS

KD FILTERS

to analog FE

DATA INTERFACE

SHAPPIRE

MACRO

CONTROLLER

CONFIG.

REGISTERS

INTERFACE

CONTROL INTERFACE

SERIAL

INTERFACE

FS

PCM

COEFF BUS

SLIC

INTERFACE

MCLK
DRA
DRB
DXA
DXB
TSXA
TSXB

IO11
IO10
IO9
IO8
IO7
IO6
IO5
IO4
IO3
IO2
IO1
IO0
CS3
CS2
CS1
CS0
INT

CCLK
CI
CO
CS

ITH ILIM VBG

D00TL467

ABSOLUTE MAXIMUM RATINGS

Symbol Parameter Value Unit

V

CC

V

DD

VD

VAin Analog Input Pin Voltage(

T

STG

T

LEAD

VCC to V
VDD to V
Digital Input Pin Voltage 5.5 V

IN

EE

SS

V

DD=VCC

; VEE=V

)V

SUB

4.6 V

4.6 V

+ 0.5;

CC

V

EE

Storage Temperature Range -65 to +150 °C
Lead Temperature (soldering, 10s) 300 °C

- 0.5 V

OPERATING RANGE

Symbol Parameter Value Unit

V

CC

, V

T

OP

Supply Voltage 3.3 +/- 5% V

DD

Operating Temperature Range -40 to +85 °C

THERMAL DATA

Symbol Parameter Value Unit

2/45

R

th j-amb

Thermal Resistance Junction-Ambient 70 °C/W

STLC5048

y

PIN CONNECTION

(Top view)

1

N.C.

2

N.C.

3

INT

4

CS

5

CO

6

CI

VSS
VDD
DRA

DXA

FS
DXB
DRB

7
8
9

10

12
13
14

15
16

CCLK

TSXA

MCLK

IO7

IO6

N.C.

RES.

60

61

62

63

64

17 18 19 20 21

IO9

IO10

IO11

IO8

59 58 57 56 5455 53 52 51 50 49

22 23 24 25 26

VCC4M1VEE4

CS2_

CS3_

VEE2

271128 29 30 31 32

VEE3

VBG

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33

VFRO3
ILIM
VFXI3
VCC3
VCC2
VFXI2
VFRO2
SUB
CAP
VFRO1
VFXI1
VCC1
VCC0
VFXI0
ITH
VFRO0

PIN DESCRIPTION

I/O DEFINITION

N.C.

TSXB_

IO0

IO1

IO2

IO3

IO4

IO5

VCC5

VEE5

M0

CS0_

CS1_

VEE1

VEE0

RES

D94TL150

Type Definition

AI Analog Input

AO Analog Output

ODO Open Drain Output

DI Digital Input

DO Digital Output

DIO Digital Input / Output
DTO Digital Tristate Output
DPS Digital Power Supply
APS Analog Power

Suppl

3/45

STLC5048

PIN DESCRIPTION

(continued)

ANALOG PIN DESCRIPTION

No. Name Type Description

33 VFRO0 AO Receive analog amplifier output channel 0. PCM data received on

the programmed Time Slot on DR input is decoded and appears at
this output.

39 VFRO1 AO Receive analog amplifier output channel 1. PCM data received on

the programmed Time Slot on DR input is decoded and appears at
this output.

42 VFRO2 AO Receive analog amplifier output channel 2. PCM data received on

the programmed Time Slot on DR input is decoded and appears at
this output.

48 VFRO3 AO Receive analog amplifier output channel 3. PCM data received on

the programmed Time Slot on DR input is decoded and appears at

this output.
35 VFXI0 AI TX Input Amplifier channel 0. Typ 1MΩ input impedance
38 VFXI1 AI TX Input Amplifier channel 1. Typ 1MΩ input impedance
43 VFXI2 AI TX Input Amplifier channel 2. Typ 1MΩ input impedance
46 VFXI3 AI TX Input Amplifier channel 3. Typ 1MΩ input impedance
40 CAP AGND Voltage filter pin: a 100nF capacitor must be connected

between ground and this pin.
34 ITH AO SLIC Off Hook detection threshold.
47 ILIM AO SLIC line current limitation.
49 VBG AI SLIC VBG reference for DC characterisrics programmability.

NOT CONNECTED

2, 18, 63, 1 N.C. Not Connected, must be left open

32, 64 RES Reserved pins, must be connected to ground

POWER SUPPLY PIN DESCRIPTION

25,36,
37,44,

45,56

26,30,
31,50,

51,55

9 VDD DPS Digital Power supply 3.3V, require 100nF decoupling capacitor to

8 VSS DPS Digital Ground.

41 SUB DPS Substrate connection. Must be shorted together with VEE and VSS

VCC0..5 APS Total 6 pins: 3.3V analog power supplies, should be shorted together,

require 100nF decoupling capacitor to VEE.

VEE0..5 APS Total 6 pins: analog ground, should be shorted together.

VSS.

pins.

4/45

STLC5048

PIN DESCRIPTION

(continued)

DIGITAL PIN DESC RIPTION

No. Name Type Description

27
54

14 FS DI Frame Sync. Pulse. A pulse or a square waveform with an 8kHz

13 MCLK DI Master Clock Input.

12 TSXA ODO Transmit Time Slot (open drain output, 3.2mA). Normally it is floating

M0
M1

DI Mode Select.

M1 M0 Mode select

0 0 Reset Status
1 0 Normal Operation
0 1 Not Allowed
1 1 Not Allowed

repetition rate is applied to this pin to define the start of the receive
and transmit frame. Effective start of the frame can be then shifted of
up to 7 clock pulses independently in receive and transmit directions
by proper programming of the PCMSH register.

Four possible frequencies can be used:

1.536/1.544 MHz; 2.048 MHz; 4.096 MHz; 8.192 MHz.
The device automatically detect the frequency applied.
This signal is also used as bit clock and it is used to shift data into
and out of the DRA/B and DXA/B pins.

in high impedance state except when a time slot is active on the DXA
output. In this case TSXA output pulls low to enable the backplane
line driver.

11 DXA DTO Transmit PCM interface A. It remains in high impedance state except

during the assigned time slots during which the PCM data byte is
shifted out on the rising edge of MCLK.

10 DRA DI Receive PCM interface A. It remains inactive except during the

assigned receive time slots during which the PCM data byte is shifted
in on the falling edge of MCLK.

24 IO5 DIO General control I/O pin #5. Can be programmed as input or output via

DIR register. Depending on content of CONF register can be a static
input/output or a dynamic input/output synchronised with the CSn

output signals controlling the SLICs.
62 IO6 DIO General control I/O pin #6. (see IO5 description).
61 IO7 DIO General control I/O pin #7. (see IO5 description).
60 IO8 DIO General control I/O pin #8. (see IO5 description).
59 IO9 DIO General control I/O pin #9. (see IO5 description).
58 IO10 DIO General control I/O pin #10. (see IO5 description).
57 IO11 DIO General control I/O pin #11. (see IO5 description).
19 IO0 DIO General control I/O pin #0. (see IO5 description).
20 IO1 DIO General control I/O pin #1. (see IO5 description).
21 IO2 DIO General control I/O pin #2. (see IO5 description).
22 IO3 DIO General control I/O pin #3. (see IO5 description).
23 IO4 DIO General control I/O pin #4. (see IO5 description).

5/45

STLC5048

PIN DESCRIPTION

(continued)

DIGITAL PIN DESCRIPTION (continued

No. Name Type Description

28 CS0 DIO Slic CS control #0. Depending on CONF reg. content can be a CS

29 CS1 DIO Slic CS control #1, (see CS0 description).
53 CS2 DIO Slic CS control #2, (see CS0 description).
52 CS3 DIO Slic CS control #3, (see CS0 description).

4 CS DI Chip Select Input, when this pin is low control information can be

7 CCLK DI Clock of Serial Control Bus. This clock shifts serial control information

6 CI DI Control Data Input of Serial Control Bus.

output for SLIC #0 or a static I/O.

When configured as CS output it is automatically generated by the

CODEC with a repetition time of 31.25ms. In this mode also the

IO0..11 are synchronised and carry proper data in and out

synchronous with CS.

When configured as static I/O, the direction is defined by CSDIR

register content.

written to or read from the device via the CI and CO pins.

into or out of CI or CO when CS input is low depending on the current

instruction. CCLK may be asynchronous with the other system

clocks.

Control data is shifted in the device when CS is low and clocked by

CCLK. Depending on the addressed register different numbers of

consecutive bytes can be loaded.

5 CO DI Control Data Output of Serial Control Bus.

Control data is shifted out the device when CS is low and clocked by

CCLK. Depending on the addressed register different numbers of

consecutive bytes can be shifted out.

3 INT ODO Interrupt output (open drain), goes low when a data change has been

detected in the I/O pins or another interrupt source is active. One

mask register allows to mask any I/O pin. Interrupt is reset when the I/

O register is read.
17 TSXB ODO Transmit Time Slot (open drain output, 3.2mA). Normally it is floating

in high impedance state except when a time slot is active on the DXB

output. In this case TSXB output pulls low to enable the backplane

line driver.
15 DXB DTO Transmit PCM interface B. It remains in high impedance state except

during the assigned time slots during which the PCM data byte is

shifted out on the rising edge of MCLK.
16 DRB DI Receive PCM interface B. It remains inactive except during the

assigned receive time slots during which the PCM data byte is shifted

in on the falling edge of MCLK.

6/45

STLC5048

FUNCTIONAL DESCRIPTION

The STLC5048 i s a fully p rogrammabl e device wi th embedd ed ROM and RAM. The ROM is used to contain t he defau lt
state coefficients for the pro gramm able filters, whi le t he RAM is used to load the desired coeffi cient values.

POWER ON INITIALIZATION
When power is first applied it is recommended to reset the device (M1=M0=0) in order to set all the internal reg-

isters to the reset value (see register description); this means also power down mode for all the four channels
and SW reset bit (RES) set in the CONF register.
When the RES bit is set, the only instructi ons allowed are the one that dis able this bit and the REACOM instruc­tion: all other instructions are ignored. It is not possible to disable the RES bit and write the other bits of the
CONF register with the same instruction.
Of course, RESET mode can be programmed also by writing the RES bit of the CONF register.
See appendix C for the power up sequence.

During RESET condition all the I/On and CSn pins are set as inputs, DX is in high impedance and all VFROn
are set to AGND. After the reset all registers are loaded with the reset value.

It means that the PCM interface and all the VFRO outputs ar e configured as descri bed in the Power Down State,
while no transmit or receive time slot are set.

Then, filters and gain blocks are configured with the coefficient defined in the Default State.

POWER DOWN STATE
Each of the four channel may be put into power down mode by setting the appropriate bit in the CONF register .

In this mode the eventual programmed D X channel i s s et in high im pedance while the VFRO outputs are forced
to AGND. When all the channels are set in Power Down mode the device enters the Power Down state: all the
blocks related to the data processing are turned off, while the RAM is On or Off according to the PDR bit value
in the COMEN register.

Figure 1. Block Diagram of a single channel.

** *

A/muDR VFRO

A/muDX HPX X GX

* PROGRAMMABLE BLOCKS

HPR R GR

**

RX

LPR D/A

*** *

B Z KD KA

*

LPX

A/D

TX

VFXI

D00TL468

7/45

STLC5048

FUNCTIONAL DESCRIPTION (continued)

RINGING STATE
This state can be used during the ringing phase in order to transmit a low frequency ringing signal (25-50 Hz).

In order to obtain a 1 Vrms ringing signal at VFRO output a digital signal DR equal to -0.78dBm0 must be pro­vided.

This state means B, Z, X, K D and KA bloc ks equal to open c ircuits and the R bloc k configured in order to obtain
the maximum gain at the frequency of 25-50 Hz. During the ringing state if the TX time slot is enabled the idle
PCM code is forced to DX.

To switch to this state, a bit (FR0..3) in the COEFST register must be set for every channel.
The programmed values for the previous blocks become active only when the FR and FD bits are reset.
If both FR and FD bits of a channel are set, the selected coefficient will be those of the Ringing State.

IMPEDANCE SYNTHESYS
The impedance synthesis is performed by fully digital filters (Z and KD) and by an analog path (KA).
The Z, KD and KA filters report to the receive path the feedback signal coming from the transmit path. The co-

efficients of the Z, KD and KA filters are programmed via the ZFC, KD and AFE_CFF commands respectively.

ECHO CA NCELING
The trans-hybrid balance is performed by the digital programmable filter B.
The B filter reports to the transmit path the signal coming from the receive path. The coefficient of the B filter

are programmed via the BFC command.

Figure 2. Trans m i t pat h.

TXG

VFXI

1MΩ

AGND

Σ∆

CONV.

for TXG=0dB; GX=0dB (FF)
61mVms => 0dBm0

GXO A/µGX

D00TL469

DX

TRANSMIT PATH
The transmit section input consist of the input amplifier, the A/D converter, the equalization filter X, the gain

block GX, the encoder and the channel filters (LPX and HPX).
The input amplifier is provided of a programmable gain with a typical input impedance of 1M

Ω

. The amplifier

gain can be programmed with two different values (0dB, +3.52dB) by means of the TXG Register.
VFXI input must be AC coupled to the signal; the voltage swing allow ed is 1.4Vpp when the pre amplifier gai n is

set to 0dB and 0.93Vpp when the gain is 3.52dB; higher levels must be reduced through proper dividers.
Following the input amplifier the signal is converted into digital domain and a X filter block is programmed to

equalise together with the HPX and LPX filters the frequency response. The coefficients of the X filter are pro­grammed via the XFC command.

A gain block (GX) allows to set the transmit level in a 30dB range, with steps <0.01dB. This block can be pro­grammed via the GTX command.

8/45

STLC5048

FUNCTIONAL DESCRIPTION (continued)

The needed TX gain can be set by proper programming of the GX block in combination with the TX amplifier.
Setting GTX=00h, the transmitted signal is muted and an idle PCM signal is generated on DX.
Concerning the CODING function, A/m law can be selected writing the CONF register (bit 5 AMU). In addition,

via the CONF register (bit 6 LIN) the coding law can be set to linear mode (16 bits). In this case the signal sent
on the DX will take two adjacent PCM channels, proper care has to be take n in the time slot sel ection pr ogram­ming (DXTS register).

The intrinsec non programmable gain GX0 set the TX path gain to 22.07dB. The absolute gain level (see elec­trical characteristics) refers to this intrinsec gain.

RECEIVE PATH
The receive path of the STLC5048 consists of the decoder section, the gain block GR, the R filter, the channel

filters (LPR, HPR) the D/A converter and the output amplifier.
Concerning the DECODING function, A/m law can be selected writing the CONF register (bit 5 AMU). In addition

via the CONF register (bit 6 LIN) the coding law can be set to linear mode (16 bits).
In this case the signal received on the DR input will take two adjacent PCM channels, proper care has to be

taken in the time slot selection programming (DRTS register).
The gain block GR is controlled by the GRX command allowing 30dB gain range in 0.01dB steps.
The R filter together the channel filters (LPR and HPR) performs the line equalization. The coefficients of the R

filter are programmed via the RFC command.
The signal is converted in the analog domain and amplified by the RX amplifier that can be programmed with

four different values (mute, 0dB, -6dB and -12dB) by means of RXG register.

Figure 3. Receive path.

RXG

DR

GROA/µ GR

D00TL470

Σ∆

CONV.

for RXG=0dB; GR=0dB
0dBm0 => -3dBm/

600Ω

VFRO

VFRO output, referred to AGND must be AC coupled to the load, r eferred to V SS, to prevent a DC cur rent flow.
In order to get the best noise performances it is recommended to keep GRX value as close as possible to the

maximum (FFh) setting properly the additional attenuation by means of RXG.
The intrinsec non programmable gain GR0 set the RX path gain to -3.15dB. The absolute gain level (see elec-

trical characteristics) refers to this intrinsec gain.

PCM INTERFAC E
The STLC5048 dedicates eight pins to the interface with the PCM highways.
MCLK represents the bit clock and is also used by the device as a source for the clock of the internal PLL.
Five possible frequencies can be used: 1.536/1.544MHz (24 channels PCM frame); 2048MHz (32 channels

PCM frame); 4.096MHz (64 channels PCM frame); 8.192MHz (128 channels PCM frame). The operating fre-

9/45

STLC5048

quency is automatical ly detected by the device the fi rst time both MCLK and FS are applied and becomes acti ve
after the second FS period. MCLK synchronises both the transmit data (DXA/B) and the receive data (DRA/B).

The Frame Sync. signal FS is the common time base for all the four channels.
Transmit and Receive programmable Time-Slots are framed by an internal sync. signal that can be coincident

with FS or delayed of 1 or 7 MCLK cycles depending on the programming of PCMSH register.
Two PCM ports are available: every channel can be connected to a different PCM port by means of PCMCOM

register.
DXA/B represents the transmit PCM interface. It remains in high impedance state except during the assigned

time slots during which the PCM data byte is shifted out on the rising/falling edge of MCLK according to the TE
bit of PCMCOM register. The four channels can be shifted out in any possible timeslot as defined by the DXTS
registers. The assigned Time Slot (Transmit and Receiv e) takes pl ace in the 8 MCLK cy cles follow ing the ris ing
edge of FS.

The data can be shifted out on port A and/or B according to PCMCOM register.
If one CODEC is set i n P ower Down by software programming the cor respondin g time slot is s et in High Imped-

ance. When linear coding mode is selected by CONF register programming the output channel will need two
consecutive time slots (see register description).

DRA/B represents the receive PCM interface. It remains inactive except during the assigned time slots during
which the PCM data byte is shifted in on the falling edge of MCLK. The four channels are shifted in any possible
time slot as defined by the DRTS registers.

If one Codec is set in Power Down by software programming the corresponding time slot is not loaded and the
VFRO output is kept at steady AGND level.

INSTRUCTION B YTE STRUCTURE

First Byte (Address or command ID) Following Bytes (Data)

7654321076543210

R/WI6 I5 I4 I3 I2 I1 I0 D7D6D5D4D3D2D1D0

R/W= 0: Write Opera tion
R/W

=1: Read Operation
I6..I0: In st ruction Ide ntifier: it ca n be a register address or a command identifier.
The numbe r of data bytes depends on the in st ruction ty pe. T he first bit of a byte is the MSB, the first byt e of an instruction is the LSB yte.

When linear coding mode is selected by CONF register programming the input channel will need two consecu­tive time slots (see register description).
The data can be shifted in from port A or B according to the PCMCOM register.
TSXA/B represents the Transmit Time Slot (open drain output, 3.2mA). Normally it is floating in high impedance
state except when a time slot is active on the DXA/B output. In this case TSXA/B output pulls low to enable the
backplane line driver. Should be strapped to VSS when not used.
Finally by means of the LOOPB register it is possible to implement a digital or analog loopback on any of the
selected channels.

MCU CONTROL I NTERFACE
The MCU serial control interface consists of 4 pins.
CCLK: Control Clock
CI: Serial Data In
CO: Serial Data Out
CS: Chip Select Input
Control instructions require at least two bytes: however two single byte instructions are also provided.

10/45

STLC5048

In the multiple byte instructions the fir st one specifies the command or the register address and the acces s type
(Read or Write).
The following bytes c ontain the data t o be loaded int o the i nternal RAM (on C I wire) or c arry out the RAM content
(on CO wire) depending on the R/W bit of t he fir st byte. CO wire is nor mally in High Impedance and goes to low
impedance only after the first byte i n case of Read operation. This al lows to us e a c ommon wir e for both CI/CO.
CS, normally High, is set Low during the tr ans missi on/reception of a byte, l asting 8 CCLK pulses. Between two
consecutive access the CS must be set high.
The CCLK can be a continuos or a gated clock.
The result of any instru ction (read/writ e oper ation), if negativ e, can generate an interrupt (maskable). The inter­rupt register (INT) contains the cause information of the generated interrupt and it is cleared every time that it
is read.

Depending on the instruction specified in the first byte, the STLC5048 waits a defined number of data bytes. If
the STLC5048 doesn't receive the data byte within a predefined period specified by means of T_OUT command,
an internal time out rejects the instruction. The time-out time is verified between two consecutive MCU interface
access (between the falling edge of the CS and the following rising edge).

This feature is us ed to verify the sy nchr onisati on of the MCU i nterf ace: however i t can be dis abled i f not de sir ed
(see T_OUT reg description). To check this synchronisati on is provided a specific register (SYNCK) that returns
always a predefined value: if the returned value is different the MCU interf ace is in out of sync state (the device
is waiting a data byte while the MCU is writing an address or vice versa). In this case, it is possible to realign it
by means of the execution of a specif ic singl e byte instr uc tion (REACOM) fr om 1 to 53 times, depending on the
instructions .

Every time an illegal operation (access to not allowed address, time-out violation or clock pulse dif ferent than 8
inside a CS active) is performed the MCU interface is put on an error state: to resume it from this state a single
REACOM instruction can be used.

Anyway after a REACOM instruction a successful SYNC instruction guarantees the correct synchronisation.
One additional wire provided to the control interface is an open drain interrupt output (INT) that goes low when

a change of status is detected on the I/O pins or other interrupt source are active (see INT register). INT is au­tomatically reset aft er reading of the register co rresp onding the c ause that has generated the inter rupt (see INT
register description).

A particular register (COMEN) allows to enable a command on different channel at the same time. Every time
a command operation is performed at least one channel must be enabled in this register.

This feature is useful when all channels must be configured in the same condition. When a command is used
to perform a read operation only one channel can be enabled at the same time.

To check the confi guration of the devi ce a check sum value is provided. This v alue is cal culated on all coefficient
parameters entered (coefficients of KD, AFE_CFF, GRX, GTX, RFC, XFC, BFC, ZFC blocks; see CKSUM reg­ister description). Two commands are required to get this value: the first one (CKSTART) starts the internal
checksum calculation, the second one (CKSUM) returns the calculated value. Between this two commands no
other operation are allowed. The checksum value is available within 400us the CKSTART command.

Coefficient checksum is defined by this algorithm:

This algorithm guarantees a fault coverage of 1 - 2

16

X

+ X12 + X5 + 1

-16

.

PROGRAMMING T HE DEVICE
After the power up, the filters and gain blocks can be pro grammed also with all the channels set in Power Down.

In this case the PDR bit of the COMEN register must be set to 0.
With the proper setting of the COMEN register, the commands can be applied to more than one channel at the
same time.
To read the coefficient values loaded in the RAM, only one channel per time must be enabled in the COMEN
register.

11/45

STLC5048

SLIC CONTROL INTERFACE
The device provides 12 I/O pins plus 4 CS signals. The interface can work in dynamic or static mode: it can be

selected by means of STA bit of the CONF register.

■

Dynamic Mode: the I/O pins are configured as input or output by means of DIR register. The CS signals
are used to select the different SLIC interface. In this case the I/O pin can be multiplexed. The data
loaded from SLIC #n via I/O pins configured as input can be read in the DATAn register. The data written
in a DATAn register will be loaded on the I/O pins configured as output wh en the Csn signal will be
active.

■

Static Mode: The CS signal can be us ed a s I/O pins. They can be configured as input or output I/O by
means of DATA1 register. The data corresponding to the CS signal can be read or written by means of
DATA2 register. All data related to the other I/O pins can be read or written by means of DATA0 register.

DC SLIC PROGRAMMA BILITY
Three additional pins are used to select the On-Hook/Off-Hook detection threshold and the line card limitation

of the STLC3080 SLIC. This two values are programmed by ILIM and ITH registers. The programmation of
these two registers must be done before the filter coefficients download.

The VBG input pin must be connected to the IREF pin of the STLC3080.
When the L3235N is used in kit with STLC5048 the ILIM, ITH and VBG pin must be not connected.

BUILT IN TEST
By means of TONEG register it is possible to inject a tone of var iable frequency (25Hz, 1 and 3KHz) and 0dBm0

amplitude into the receiv e path, replacing any signal coming from the PCM inter face. This test can be performed
on every channel.

Setting the proper bit of the PCMCOM register is also possible to read/write the PCM data coming from the
transmit path via the MCU interface (PCMRD/PCMWD registers). This feature can be enabled only on one
channel per time.

These two features can be used to test the line interface operation.

REGISTER ADDRESSES

Addr Nam e Description

00h DIR-L I/O Direction (bit 7-0)
01h DIR-H I/O Direction (bit 11-8)
02h DATA0-L I/O Data ch#0 (bit 7-0)
03h DATA0-H I/O Data ch #0 (bit 11-8)
04h DATA1-L I/O Data ch#1 (bit 7-0)
05h DATA1-H I/O Data ch #1 (bit 11-8)
06h DATA2-L I/O Data ch#2 (bit 7-0)
07h DATA2-H I/O Data ch #2 (bit 11-8)
08h DATA3-L I/O Data ch#3 (bit 7-0)
09h DATA3-H I/O Data ch #3 (bit 11-8)
0Ah PCHK-A Persistency Check Time for input A
0Bh PCHK-B Persistency Check Time for input B
10h INT Interrupt regist er

12/45

STLC5048

REGISTER ADDRESSES

11h DMASK-L Int. Mask I/O Port (03h)
12h DMASK-H Int. Mask I/O Port (04h)

Addr Name Description

13h IMASK Interrupt Mask reg.
14h ALARM Alarm register
20h CONF Configuration register
21h COMEN Command Enable reg.
23h SYNCCK Synchronous Check reg.
25h CTRLACK DSP status register
26h CKSUM-L Cheksum register L
27h CKSUM-H Cheksum register H
2Ah LOOPB Loopback register

2Bh TXG Transmit preamp. Gain
2Ch RXG Receive preamp. Gain
2Dh ILIM SLIC line current lim.
2Eh ITH SLIC Off-Hook threshold

50h PCMSH PCM Shift register

51h PCMCOM PCMCOM register

52h DXTS0 Transmit Timeslot ch #0

53h DXTS1 Transmit Timeslot ch #1

54h DXTS2 Transmit Timeslot ch #2

55h DXTS3 Transmit Timeslot ch #3

56h DRTS0 Receive Timeslot ch #0

57h DRTS1 Receive Timeslot ch #1

58h DRTS2 Receive Timeslot ch #2

59h DRTS3 Receive Timeslot ch #3
5Ah PCMWD -L P CMW Data regist er
5Bh PCMWD -H PCMW Data register
5Ch PCMRD-L P CMR Data regist er
5Dh PCMRD -H PCMR Data register
5Eh PCMCTRL PCM Control register

60h TONEG Tone Generation reg.

61h COEFST Coefficient State reg.

70h SWRID Software rev. ID code

71h HWRID Silicon revision ID code

(continued)

13/45

STLC5048

REGISTER DESCRIPTION
I/O Direction Register (DIR)

Addr=00h; Reset Value=00h
Addr=01h; Reset Value=X0h

BIt7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

R/W0000000

IO

7

IO

6

IO

5

IO

4

IO

3

IO

2

IO

1

IO

0

BIt7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

R/W0000001

IO

11

IO100IO

9

IO

8

IO11..0=0 I/O pin 11..0 is an input, data on the I/O input is written in DATAn register bit 11..0.
IO11..0=1 I/O pin 11..0 is an output, data contained in DATAn register bit 11..0 is transferred to the I/O output.

I/O Data Register channel #0 (DATA0)

Addr=02h; Reset Value=00h
Addr=03h; Reset Value=X0h
If bit 4 of CONF register (STA)=0 Dynamic I/O mode:

BIt7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

R/W0000010

D0

7

BIt7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

R/W0000011

D0

6

D0

5

D0

4

D0

3

D0

2

D0

1

D0

0

D0

11

D0

10

D0

9

D0

8

When CS0 is active D011..0 are transferred to the corresponding I/O pins configured as outputs (see DIR reg­ister). For the I/O pins configured as inputs the corresponding D011..0 will be written by the values applied to
those pins while CS0 is low.

If bit 4 of CONF register (STA)=1 Static I/O mode:

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

R/W0000010
DS

7

DS

6

DS

5

DS

4

DS

3

DS

2

DS

1

DS

0

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

R/W0000011

DS

11

DS

10

DS

9

DS

8

DS11..0 are transferred to the corr espondin g I/O pins configur ed as outpu ts (see DIR register ). For the I/O pins
configured as inputs the corresponding DS11..0 will be written by the values applied to those pins.

14/45

STLC5048

I/O Data Register channel #1 (DATA1)

Addr=04h; Reset Value=00h
Addr=05h; Reset Value=X0h

If bit 4 of CONF register (STA)=0 Dynamic I/O mode:

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

R/W0000100

D1

7

D1

6

D1

5

D1

4

D1

3

D1

2

D1

1

D1

0

BIt7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

R/W0000101

When CS1

D1

11

D1

10

is active D111..0 are transferred to the corresponding I/O pins configured as outputs (see DIR reg-

D1

9

D1

8

ister). For the I/O pins configured as inputs the corresponding D111..0 will be written by the values applied to
those pins while CS1

is low.
If bit 4 of CONF register (STA)=1 Static I/O mode:
In static mode CS pin s are used as addi tiona l I/O pin s. The CIO0..3 bi ts are used t o define t he direct ion of t hese pins.

BIt7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

R/W0000100

CIO

3

CIO

2

CIO

1

CIO

0

CIO0..3=0 The CS0..3 is a static input, DATA is written in DATA2 register bits 0..3.
CIO0..3=1 The CS0..3

is a static output, DATA is taken from DATA2 register bits 0..3.

I/O Data Register channel #2 (DATA2)

Addr=06h; Reset Value=00h
Addr=07h; Reset Value=X0h

If bit 4 of CONF register (STA)=0 Dynamic I/O mode:

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

R/W0000110

D2

7

D2

6

D2

5

D2

4

D2

3

D2

2

D2

1

D2

0

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

R/W000011 1

When CS2

D2

11

D2

10

is active D211..0 are transferred to the corresponding I/O pins configured as outputs (see DIR reg-

D2

9

D2

8

ister). For the I/O pins configured as inputs the corresponding D211..0 will be written by the values applied to
those pins while CS2

is low.

15/45

STLC5048

If bit 4 of CONF register (STA)=1 Static I/O mode:

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

R/W0000110

CD

3

CD

2

CD0..3 are transferred to the corresponding CS pin if configured as static output (see register DATA1). For the
CS pins configured as sta tic i nputs the corresponding CD0..3 will be w ritten by the val ues appl ied to those pins.

I/O Data Register channel #3 (DATA3)

Addr=08h; Reset Value=00h
Addr=09h; Reset Value=X0h

Used only if bit 4 of CONF register (STA)=0; Dynamic I/O mode:

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

R/W0001000

CD

1

CD

0

D3

7

D3

6

D3

5

D3

4

D3

3

D3

2

D3

1

D3

0

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

R/W0001001

When CS3

D3

11

is active D311..0 are transferred to the corresponding I/O pins configured as outputs (see DIR reg-

D3

10

D3

9

D3

8

ister). For the I/O pins configured as inputs the corresponding D311..0 will be written by the values applied to
those pins while CS3

is low.
If bit4 of CONF register (STA) = 1

Static I/O mode:
D3

=1: The corresponding CSn cannot generate interrupt.

3..0

D3

=0: The correspondin g I/O (programmed as input) can generate inter rupt if a change of stat us is detected .

3..0

Persistency Check Register (PCHK-A/B)

Addr=0Ah; Reset Value=00h
Addr=0Bh; Reset Value=00h

Two input signal per channel, labelled A and B, are submitted to persistency check.
In dynamic mode (STA=0), A and B inputs of the four channels, are sampled on the multiplexed lines IO0 (pin

13) and IO1 (pin 14).
In static mode (S TA=1) persi stency check is per formed o n four pairs of lines , assi gned to eac h channel accor d-

ing to the table:

16/45

CHAN # Input A Input B

0IO
1IO
2IO
3IO

(pin 19) IO1 (pin 14)

0

(pin 17) IO5 (pin 18)

4

(pin 48) IO7 (pin 47)

6

(pin 44) IO11 (pin 43)

10

STLC5048

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

R/W0001010

TA7 TA6 TA5 TA4 TA3 TA2 TA1 TA0

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

R/W0001011
TB7 TB6 TB5 TB4 TB3 TB2 TB1 TB0

TA7..0 and TB7..0, contents of PCHKA and PCHKB registers, define the minimum duration of input A and B to
generate interrupt; spurious transitions shorter than the programmed value are ignored.

The time width can be calculated according to the formula:
Time - Width A = (TA7..0)*64µs
Time - Width B = (TB7..0)*64µs
If PCHKA/B is programmed to 00h the persistency check is not performed and any detected transition will gen-

erate interrupt.
All the inputs, with or without persistency check, are sampled with a repetition rate of 32µs.

Interrupt Register (INT)

Addr=10h; Reset Value=00h
Read Only

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

10010000

ITV IPCM ICKF ID3 ID2 ID1 ID0

In dynamic I/O configuration the ID3..0 bits latch the interrupt request from the r elated channel (SLIC). A ny sin­gle bit IDn is cleared after reading related I/O regis ter or by setting MCn bit High (i.e. when channel n is disabled
to generate interrupt).

In static I/O configuration ID0 and ID2 bits latch the interrupt request from I/O11..0 and CS3..0 respectively:
ID0: is set High when the interrupt is requested from any the I/O11..0 lines.
ID2: is set High when the interrupt is requested from any the CS3..0 (configured as I/O).
ID0 and ID2 are cleared after reading related I/O register.
ID1 and ID3 are don’t care.
ITV = 1: If the interrupt has been generated by time-out violation on the MCU serial interface.
IPCM = 1: When transmit PCM data reading/writing test is enabled an interrupt is generated every time valid

data are available (R RD bit set to 1 ) or must be written (WRD bit set to 1). The i nterr upt is cleared afte r reading/
writing the data in the PCMRD/PCMWD register via the MCU interface.

ICKF = 1: If the interrupt has been generated by a clock failure on PCM port (MCLK).

The INT register is cleared after reading operation only if signals (alarm cause) are inactive.

17/45

STLC5048

Interrupt Mask Register for I/O port (DMASK)

Addr=11h; Reset Value=FFh
Addr=12h; Reset Value=XFh

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

R/W0010001

MD

7

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

R/W0010010

MD
MD

=1: The corresponding I/O doesn’t generate interrupt.

11..0

=0: The corresponding I/O (programmed as input) generate interrupt if a change of status is detected.

11..0

MD

6

MD

5

MD

4

MD

MD

11

3

MD

MD

2

10

MD

MD

1

9

MD

MD

0

8

Input lines with persistency check generate interrupt if the changed status remains stable longer than the time
programmed in the persistency check register PCHKA/B. Line without persistency check generate an immedi­ate interrupt request.

Mask register has no effect on those pins configured as outputs, those pins will not generate interrupt.

Interrupt Mask Register for Interrupt (IMASK)

Addr=13h; Reset Value=FFh

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

R/W0010011

x MTV MPCM MCF MC3 MC2 MC1 MC0

For dynamic I/O configuration, MCn bits are the disable/enable interrupt related to the channel n.
MC3..0=1: Any I/O lin e of the rel ated channel #n is disabled to gen erat e interrupt independently of DMASK setting.
MC3..0=0: Any I/O line of the r elated channel #n is enabled to generate interrupt depending on DMASK s etting.
For static I/O configurati on, MCn bits are the inter rupt mas k bits related to CSn that are c onfigur ed as I/O lines.
MC0=1: The corresponding I/O cannot generate interrupt independently of DMASK setting.
MC0=0: The co rresponding I/O can generate in terrupt if a change of status is detected depending of DMASK setting.
MC2=1: The corresponding I/O cannot generate interrupt independently of DATA3_L setting (bit 3..0).
MC2=0: The corresponding I/O can generate interrupt if a change of status is detected depending of DATA3_L

setting (bit 3..0).
MC3 and MC1 bit are not used in static mode.

Input lines with persistency check generate interrupt if the changed status remains stable longer than the time
programmed in the persistency check register PCHKA/B. Line without persistency check generate an immedi­ate interrupt request.
Mask register has no effect on those pins configured as outputs, those pins will not generate interrupt

MCF=1: The corresponding alarm bit (CKF) doesn’t generate interrupt.
MCF=0: The corresponding alarm bit (CKF) can generate interrupt.
MTV=1: The corresponding alarm bit (TV) doesn’t generate interrupt.
MTV=0: The corresponding alarm bit (TV) can generate interrupt.
MPCM =1 : The IPCM interrupt is masked (generation disabled).
MPCM =0 : The IPCM interrupt is enabled (generation enabled).

18/45

STLC5048

Alarm Register (ALARM)

Addr=14h; Reset Value=01h
Read Only

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

10010100
0000000POR

POR=0: No Power On Reset is detected during operation.
POR=1: A Power On Reset is detected during operation.
The ALARM register is cleared after reading operation only if signals (alarm cause) are inactive.

Configuration Register (CONF)

Addr=20h; Reset Value=BFh

BIt7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

R/W0100000

RES LIN AMU STA PD3 PD2 PD1 PD0

RES=0 Normal Operation
RES=1 D evice Reset: I/0n and Csn are all inputs, DX is H.I. (equivalent to Hw reset).

µ

LIN=0 A or
LIN=1 Linear encoding (16 bits), two’s complement.
AMU=0
AMU=1 A law selection (even bits inverted)
STA=0 CS0

time.
STA=1I/O are static, CS0 to CS3 are configured as generic static I/O
PD3..0=0 Codec 3..0 is active
PD3..0=1 Codec 3..0 is in Power Down. When one codec is in Power Down the corresponding VFRO output is

set to AGND and the corresponding transmit time slot on DX is set in H.I.

law PCM encoding

µ

law selection (all bits inverted)

to CS3 scan the four SLICs connected to the I/O control port, each CS has a 31.25µs repetition

Command Enable register (COMEN)

Addr=21h; Reset Value=80h

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

R/W0100001

PDR 0 0 0 E

3

E

2

E

1

E

0

The En bits enable a c ommand on one or more c hannels. All enabled channels wil l recei ve the enter ed data. At
least one channel must be enabled before every command.

E0..3=0: commands disabled on the corresponding channel 0..3
E0..3=1: commands enabled on the corresponding channel 0..3
PDR = 0: RAM is enabled also in Power Down.
PDR = 1: RAM is disabled in Power Down. In this way it’s possible to reduce the power consumption in Power

Down.

19/45

STLC5048

Synchronous Check register (SYNCK)

Addr=23h; Reset Value=E4h
Read Only

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

10100011
11100100

This register contains a fixed code (E4h) that can be read to check the synchronisation of the MCU interface.

DSP Status Register (CTRLACK)

Addr=25h; Reset Value=01h
Read Only

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

1010010 1
0 0 0 0 0 0 INIT CKEND

CKEND bit is 0 while the checksum calculation is performed: in the other time is always set to 1.
INIT bit becomes active (INIT = 1) after the DSP initialization. Normally it requires 70 us after the reset to be set to 1.

Checksum register (CKSUM)

Addr=26h; Reset Value=00h
Addr=27h; Reset Value=00h
Read Only

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

10100110

CK

7

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

10100111

CK

15

CK

CK

6

14

CK

CK

5

13

CK

CK

12

4

CK

CK

3

11

CK

CK

10

2

CK

CK

1

9

CK

CK

0

8

The cheksum value is calculated every time the CKSTART instruction is performed and the result is available
after a proper delay (max 400

µ

s).
This register contains the c heksum value calc ulated on the contents of the fol lowing coefficient ( each of 16 bits):
ZERO
KDF0_0 KDF0_1 KDF0_2 KDF1_0 KDF1_1 KDF1_2 KDF2_0 KDF2_1 KDF2_2 KDF3_0 KDF3_1 KDF3_2

AFE_CFF GRX0 GTX0 RFC0_0 ...... RFC0_16 XFC0_0 ...... XFC0_16 BFC0_0 ...... BFC0_25

ZFC0_0 ...... ZFC0_4 GRX1 GTX1 RFC1_0 ...... RFC1_16 XFC1_0 ...... XFC1_16 BFC1_0 ......BFC1_25

ZFC1_0 ...... ZFC1_4 GRX2 GTX2 RFC2_0 ......RFC2_16 XFC2_0 ...... XFC2_16 BFC2_0 ...... BFC2_25

ZFC2_0 ...... ZFC2_4 GRX3 GTX3 RFC3_0 ...... RFC3_16 XFC3_0 ...... XFC3_16 BFC3_0 ...... BFC3_25

ZFC3_0 ......ZFC3_4

20/45

STLC5048

Loopback Register (LOOPB)

Addr=2Ah; Reset Value=00h

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

R/W1011010
DL3 DL2 DL1 DL0 AL3 AL2 AL11 AL0

DL3..0=0: Normal Operation
DL3..0=1: Codec #3..0 is set in Digital Loopback mode, this means that the receive PCM signal applied to the
programmed Receive Time Slot is transferred to the programmed Transmit Time Slot.

AL3..0=0: Normal Operation
AL3..0=1: Codec #3..0 is set in Analog Loopback mode, this means that the VFRO signal is transferred to the
VFXI input internally into the Codec.

When loopbacks are enabled the signal appears also at the corresponding VFRO output. It is possible to have
no signal on the VFRO output programming the GRX command to 00h in case of digital loopback.

Transmit Preamplifier Gain Register (TXG)

Addr=2Bh; Reset Value=00h

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

R/W0101011

TG3 TG2 TG1 TG0

TG3..0=0: Transmit preamplifier gain ch. 3..0 = 0dB
TG3..0=1: Transmit preamplifier gain ch. 3..0 = 3.52dB
Overall transmit gain depends on combination of TXG and GTXn registers.

Receive Amplifier Gain Register (RXG)

Addr=2Ch; Reset Value=00h

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

R/W0101100

R3

1

=0,Rn1=0: Receive amp. gain ch #n = mute

Rn

0

Rn

=1,Rn1=0: Receive amp. gain ch #n = -12dB

0

=0,Rn1=1: Receive amp. gain ch #n = -6dB

Rn

0

Rn

=1,Rn1=1: Receive amp. gain ch #n = 0dB

0

R3

0

R2

1

R2

0

R1

1

R1

0

R0

1

R0

0

Overall receive gain depends on the receive amplifier gain (R3..0) setting in RXG reg. and digital gain (GRXn
reg. setting).

21/45

STLC5048

SLIC Line Current Limit reg (ILIM)

Addr=2Dh; Reset Value=00h

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

R/W0101101

0 0 0 D4D3D2D1D0

D4..0 = 0: Programmed value is 53
D4..0 = 1: Programmed value is 2
The step is 1.6 mA

This register allows to program a line current limitation from 2 to 53mA wi th a step equal to 1.6mA. These val ues
can be obtained using an external 15KOhm resistor in kit with STLC3080.

SLIC Off-Hook threshold register (ITH)

Addr=2Eh; Reset Value=00h

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

R/W0101110

0 0 0 EnD3D2D1D0

D3..0 = 0: Programmed value is 16 mA
D3..0 = 1: Programmed value is 1 mA

The step is equal to 1 mA.
En = 1 The DC SLIC programmability block is enabled (ITH and ILIM)
En = 0 The DC SLIC programmability block is disabled (ITH and ILIM)
This register allows to program a threshold value from 1 to 16 mA with a step equal to 1mA. These values can

be obtained using an external 12.5KOhm resistor in kit with STLC3080.

PCM Shift Register (PCMSH)

Addr=50h; Reset Value=00h

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

R/W1010000

XS2 XS1 XS0 RS2 RS1 RS0

XS2..0:Effective start of the TX frame is the programmed values of cl ock pulses (0 to 7) after the FS rising edge.
RS2..0:Effective start of the R X frame is the pr ogrammed values of cl ock pulses ( 0 to 7) after the FS rising edge.

PCM Command register (PCMCOM)

Addr=51h; Reset Value=00h

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

R/W1010001

RR WR PC1 PC0 TE RPAB TPB TPA

22/45

STLC5048

TPA/B = These two bits are used to enable the DX outputs of the por t A or /and B. Accor ding to the combi nation
of these two bits the enabled port will be as follows:

TPB TPA Description

0 0 Both Ports disabled
0 1 Port A enabled
1 0 Port B enabled
1 1 Both ports enabled

RPAB = 0: Port A enabled (DRA input selected)
RPAB = 1: Port B enabled (DRB input selected)
TE = 0: Transmit PCM data change on rising edge of MCLK
TE = 1: Transmit PCM data change on falling edge of MCLK
PC1-PC0 = Selection of the channel for the PCM access data via MCU.

PC0 PC1 Description

0 0 Channel #0 selected
1 0 Channel #1 selected
0 1 Channel #2 selected
1 1 Channel #3 selected

WR = 1: Setting this bit , receive PCM data writing via MCU (after A/µ decoding) is enabl ed on selec ted c hannel
and IPCM interrupt is generated every time FS signal becomes active, together to the set of the WRD bit in the
PCMCTRL register.

A data byte must be written every 125µs, if data is not replaced the old value is inserted again but the PMW bit
is set to 1 in the PCMCTRL register.

RR = 1: Setting this bit, transmi t PCM data reading (after A/µ encoding) via MCU is enabl ed on selected c hannel
and IPCM interrupt is generated every time that data are avail able, together to the set of the RRD bit in the PC­MCTRL register.
A data byte must be read every 125µS, if data is not read the new value is written in the PCM access register
but the POW bit is set to 1 in the PCMCTRL register.

Transmit Time Slot ch #0 (DXTS0)

Addr=52h; Reset Value=00h

Bit7 Bi t6 Bit5 Bit 4 Bit3 Bit2 Bit1 Bit0

R/W1010010
EN0 T06 T05 T04 T03 T02 T01 T00

EN0=0:Selected transmit time slot on DX output is in H.I.
EN0=1:Selected transmit time slot on DX output is active carrying out the PCM encoded signal of VFXI0.
T06..0:Define time slot number (0 to 127) on which PCM encoded signal of VFXI0 is carried out.
If linear mode is selected (LIN=1 of CONF register) the 16 bits will be carried out as follows: the 8 most signifi­cant bits in the programmed time slot, the 8 least significant bits in the following time slot.
Example: if T06..T00=00:

TS0 TS1

1514131211109876543210

23/45

STLC5048

Transmit Time Slot ch #1 (DXTS1)

Addr=53h; Reset Value=00h

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

R/W1010011
EN1 T16 T15 T14 T13 T12 T11 T10

EN1=0: Selected transmit time slot on DX output is in H.I.
EN1=1: Selected transmit time slot on DX output is active carrying out the PCM encoded signal of VFXI1.
T16..0: Define time slot number (0 to 127) on which PCM encoded signal of VFXI1 is carried out.
If linear mode is selected (LIN=1 of CONF register) the 16 bits will be carried out as follows: the 8 most signifi-

cant bits in the programmed time slot, the 8 least significant bits in the following time slot.
Example: if T16..T10=00:

TS0 TS1

1514131211109865437210

Transmit Time Slot ch #2 (DXTS2)

Addr=54h; Reset Value=00h

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

R/W1010100
EN2 T26 T25 T24 T23 T22 T21 T20

EN2=0: Selected transmit time slot on DX output is in H.I.
EN2=1: Selected transmit time slot on DX output is active carrying out the PCM encoded signal of VFXI2.
T26..0: Define time slot number (0 to 127) on which PCM encoded signal of VFXI2 is carried out.
If linear mode is selected (LIN=1 of CONF register) the 16 bits will be carried out as follows: the 8 most signifi-

cant bits in the programmed time slot, the 8 least significant bits in the following time slot.
Example: if T26..T20=00:

TS0 TS1

1514131211109865437210

Transmit Time Slot ch #3 (DXTS3)

Addr=55h; Reset Value=00h

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

R/W1010101
EN3 T36 T35 T34 T33 T32 T31 T30

EN3=0: Selected transmit time slot on DX output is in H.I.
EN3=1: Selected transmit time slot on DX output is active carrying out the PCM encoded signal of VFXI3.
T36..0: Define time slot number (0 to 127) on which PCM encoded signal of VFXI3 is carried out.
If linear mode is selected (LIN=1 of CONF register) the 16 bits will be carried out as follows: the 8 most signifi-

cant bits in the programmed time slot, the 8 least significant bits in the following timeslot.

24/45

STLC5048

Example: if T36..T30=00:

TS0 TS1

1514131211109865437210

Receive Time Slot ch #0 (DRTS0)

Addr=56h; Reset Value=00h

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

R/W1010110
EN0 R06 R05 R04 R03 R02 R01 R00

EN0=0: Disable reception of selected time slot.
EN0=1: Selected receive time slot on DR input is PCM decoded and transferred to VFRO0 output.
R06..0: Define receive time slot number (0 to 127) on carrying the PCM signal to be decoded and transferred

to VFRO0 output. If linear mode is selected (LIN=1 of CONF register) the 16 bits will be used as linear code as
follows: the 8 most significant bits in the programmed time slot, the 8 least significant bits in the following
timeslot.

Example: if R06..R00=00:

TS0 TS1

1514131211109865437210

Receive Time Slot ch #1 (DRTS1)

Addr=57h; Reset Value=00h

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

R/W101011 1
EN1 R16 R15 R14 R13 R12 R11 R10

EN1=0: Disable reception of selected time slot.
EN1=1: Selected receive time slot on DR input is PCM decoded and transferred to VFRO1 output.
R16..0: Define receive time slot number (0 to 127) on carrying the PCM signal to be decoded and transferred

to VFRO1 output. If linear mode is selected (LIN=1 of CONF register) the 16 bits will be used as linear code as
follows: the 8 most significant bits in the programmed time slot, the 8 least significant bits in the following time
slot.

Example: if R16..R10=00:

TS0 TS1

1514131211109865437210

Receive Time Slot ch #2 (DRTS2)

Addr=58h; Reset Value=00h

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

R/W101100 0
EN2 R26 R25 R24 R23 R22 R21 R20

25/45

STLC5048

EN2=0: Disable reception of selected time slot.
EN2=1: Selected receive time slot on DR input is PCM decoded and transferred to VFRO2 output.
R26..0: Define receive time slot number (0 to 127) on carrying the PCM signal to be decoded and transferred

to VFRO2 output.
If linear mode is selec ted (LIN=1 of CONF register) the 16 bits will be used as linear code as follows: the 8 most

significant bits in the programmed time slot, the 8 least significant bits in the following timeslot.
Example: if R26..R20=00:

TS0 TS1

1514131211109865437210

Receive Time Slot ch #3 (DRTS3)

Addr=59h; Reset Value=00h

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

R/W1011001
EN3 R36 R35 R34 R33 R32 R31 R30

EN3=0: Disable reception of selected time slot.
EN3=1: Selected receive time slot on DR input is PCM decoded and transferred to VFRO3 output.
R36..0: Define receive time slot number (0 to 127) on carrying the PCM signal to be decoded and transferred

to VFRO3 output. If linear mode is selected (LIN=1 of CONF register) the 16 bits will be used as linear code as
follows: the 8 most significant bits in the programmed time slot, the 8 least significant bits in the following
timeslot.

Example: if R36..R30=00:

TS0 TS1

1514131211109865437210

PCMW Data Register (PCMWD)

Addr=5Ah; Reset Value=00h
Addr=5Bh; Reset Value=00h

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

R/W1011010

D7 D6 D5 D4 D3 D2 D1 D0

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

R/W1011011
D15 D14 D13 D12 D11 D10 D9 D8

This register is used to write receive PCM data via the MCU interface. Writing this register the IPCM interrupt
(if generated only by writing access) is automatically cleared.

In A/µ law only the first 8 bit are used. In linear code option both registers must be used.

26/45

STLC5048

PCMR Data Regist er (PCMRD)

Addr=5Ch; Reset Value=00h
Addr=5Dh; Reset Value=00h
Read only

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

11011100

D7 D6 D5 D4 D3 D2 D1 D0

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

11011101

D15 D14 D133 D12 D11 D10 D9 D8

This register is used to read transmit PCM data via the MCU interface. Reading this registe r the IPCM interrupt
(if generated only by reading access) is automatically cleared.

In A/µ law only the first 8 bit are used. In linear code option both registers must be read, first the LSB and after
the MSB.

PCM Control Register (PCMCTRL)

Addr= 5Eh; Reset Value=00h
Read only

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

11011110

RRD WRD POW PMW

PMW = 1: Data is not written every FS while writing PCM access data is enabled.
POW = 1: Data is not read every FS while reading PCM access data is enabled.
WRD = 1: Device is waiting for PCM data insertion i n PCM W D register. The bit is reset after wr iting at least one byte.
RRD = 1: Data are available on PCMRD regis ter. The bit i s reset after r eadi ng the two bytes of the r egis ter (f irst

the LSB and after the MSB).

Tone Generation register (TONEG)

Addr=60h; Reset Value=00h

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

R/W1100000

T3

1

=0,Tn1=0: No tone is generated on ch #n

Tn

0

Tn

=1,Tn1=0: A tone with 25Hz frequency is generated on ch #n.

0

=0,Tn1=1: A tone with 1KHz frequency is generated on ch #n.

Tn

0

Tn

=1,Tn1=1: A tone with 3KHz frequency is generated on ch #n.

0

T3

0

T2

1

T2

0

T1

1

T1

0

T0

1

T0

0

This register allows the generation of a tone in the RX direction.

27/45

STLC5048

Coefficient State register (COEFST)

Addr= 61h; Reset Value=F0h

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

R/W1100001
FD3 FD2 FD1 FD0 FR3 FR2 FR1 FR0

FR0..3=1: All channel filters and gain blocks are configured as defined in the ringing state
FR0..3=0: All channel filters and gain blocks are configured as defined with the programmed value if also the

corresponding FD bit is set to 0
FD0..3=1: All channel filters and gai n blocks are configured as defined in the default state if also the correspond-

ing FR bit is set to 0
FD0..3=0: All channel filters and gain blocks are configured as defined with the programmed value if also the

corresponding FR bit is set to 0

Software Revision ID Code (SWRID)

Addr=70h; Read only.

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

11110000
00010100

This register contains the DSP Software revision Code identifier.

Hardware Revision ID C ode (HWRID)

Addr=71h; Read only.

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

11110001
00000001

This register contains the Silicon revision Code identifier.

SINGLE BYTE INS TRUCTION

Name Description ID

REACOM Realignment comm and 28h
CKSTART Start Checksum 29h

Realignment Command (REACOM)

This single instruction is used to realign the MCU interface in case of out of synchronisation. This instruction
must be executed Nmax+1 times to be successfull.

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

00101000

28/45

STLC5048

Start Checksum Calculation (CKSTART)

This single i nstruction is used to start the checksum calcu lat ion of the enetered data used to configure the device.

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

00101001

COMMAND LIST

Name Description ID

BLKEN Block enable 22h
KDF KD Filter 30h
AFECFF AFE KA Coefficient (*) 31h
T_OUT Timeout value (*) 32h
GRX Receive Gain 40h
GTX Transmit Gain 41h
RFC R Filter Coefficient 42h
XFC X Filter Coefficient 43h
BFC B Filter Coefficient 44h
ZFC Z Filter Coefficient 45h

(*) For this t wo commands the bit se t in t he COMEN re gi ster are not considered.

COMMAND DESCRIPTION

Each command is transferred on every channel that has the proper bit in the COMEN register set to 1.

Block Enable command (BLKEN)

Reset Value=00h
The command is used to enable/disable the B, Z, R and X blocks

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

R/W0100010

XE RE ZE BE

BE=1: The B block is equal to an open circuit
BE=0: The B block is configured as defined in the Ringing state or with the programmed value
ZE=1: The Z block is equal to an open circuit
ZE=0: The Z block is configured as defined in the Ringing state or with the programmed value
RE=1: The R block is equal to a short circuit
RE=0: The R block is configured as defined in the Ringing state or with the programmed value
XE=1: The X block is equal to a short circuit
XE=0: The X block is configured as defined in the Ringing state or with the programmed value

29/45

STLC5048

KD Filter (KDF)

The register is used to set the 3 coefficients (each of 16 bits) of the KD filter of the channel #n.

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

R/W0110000

.
..

AFE Coefficient (AFE_CFF)

Reset value = AA00h

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

R/W0110001

KA31 KA30 KA21 KA20 KA11 KA10 KA01 KA00

TTX

KAn0, KAn1 = KA coefficient for Ch #n
According to the value of each couple of bits, the KA block is set in the following condition:
KAn1 KAn0
0 X KA block disabled
1 0 KA set for low gain
1 1 KA set for high gain
When the application involves also the metering pulse signal the AFE of the STLC5048 must be adapted in or-

der to manage also this signal. For this purpose is provided the TTX bit.
TTX = 0: the current application is not using the metering pulse signal
TTX = 1: the current application is using the metering pulse signal

Timeout value (T_OUT)

Reset Value=FFFFh

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

R/W0110010

T7 T6 T5 T4 T3 T2 T1 T0

T15 T14 T13 T12 T11 T10 T9 T8

Reset value = Maximum value = FFFFh (2048 us)
To disable this function the T0 bit must be set to 0.
To enable this function the T0 bit must be set to 1; the time-out value is set by means of T<15..1> bits.
Time_out = (T_OUT[15:1]*62.5 + 31.24)ns
The minimum step is 62.5 ns.

30/45

STLC5048

Receive Gain (GRX)

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

R/W1000000

00h: Stop any received signal to reach the VFRO0 analog output. In order to open the impedance synthesis
feedback it’s necessary to mute the RX analog amplifier, as well.

>00h: Digital gain is inserted in the RX path equal to:
20Log[prog.value/32768]
The prog. value must be espressed in 16 bits signed format: maximum prog. value is equal to 7FFFh.

Transmit Gain (GTX)

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

R/W1000001

00h: Stop any transmit signal, null level is transmitted in the corresponding timeslot on DX output.
>00h: Digital gain is inserted in the TX path equal to:
20Log[prog.value/32768]
The prog. value must be espressed in 16 bits signed format: maximum prog. value is equal to 7FFFh.

R Filter Coefficient (RFC)

The register is used to set the 17 coefficients (each of 16 bits) of the R filter of the channel #n.

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

R/W1000010

.
.

X Filter Coefficient (XFC)

The register is used to set the 17 coefficients (each of 16 bits) of the X filter of the channel #n.

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

R/W1000011

.
.

31/45

STLC5048

B Filter Coefficient (BFC)

The register is used to set the 26 coefficients (each of 16 bits) of the B filter of the channel #n.

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

R/W1000100

.
.

Z Filter Coefficient (ZFC)

The register is used to set the 5 coefficients (each of 16 bits) of the Z filter of the channel #n.

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

R/W1000101

.
.

32/45

STLC5048

ELECTRICAL CHARACTERISTCS

Typical value are for 25°C and nominal supply voltage. Minimum and maximum values are guaranteed over the
temperature 0-70°C range by producti on testing and supply voltage range s hown in the Operating Ranges. Per­formances over -40 +85°C range are guaranteed by product characterisation unless otherwise specified.

Symbol Parameter Test Condition Min. Typ. Max. Unit

DIGITAL INTERFACE

Vil Input Voltage Low DI pins 0 0.2Vdd V

Vih Input Voltage High DI pins 0.8Vdd 5.5 V

Iil Input Current Low DI pins -10 10 µA
Iih Input Current High DI pins -10 10 µA
Ci Input Capa citanc e (all dig. inp.) 5 pF

Vol Output Voltage Low DX, TSX pins Iol=3.2mA (other pins Iol=1mA) 0 0.4 V

Voh Output Voltage High DX pin Ioh=-3.2mA (other pins Iol=1mA)

Note: all di gi t al i nput are 5V tol erant.

ANALOG INTERFACE

RIX Transmit Input Amplifier Input

ROR Receive Output Impedance 1 Ω

POWER DISSIPATION

Idd(pd) Power down Current 10 15 mA

Idd(act) Active Current 55 70 mA

PCM INTERFACE TIMING

f(MCLK) Master Clock Frequency 1.536

Twmh Period of MCLK high 38 ns

Twml Period of MCLK low 38 ns

Trm MCLK rise time 10 ns
Tfm MCLK fall time 10 ns

Thbf Hold Time MCLK Low to FSX/R

Tsfb
Tdmd
Tdmz Delay Time from MCLK(8) Low to

Tdfd Delay Time, FSX High to Data

Tdmt Delay Time, from MCLK and FSX

Tzmt Delay time from MCLK(8) low to

Tsdm
Thdm Hold time, MCLK Low to DR

Impedance (VFXI)

High or Low
Setup time FSX/R High to MCLK Low
Delay Time, MCLK High to Data Valid

Data Output disabled

Valid if FSX rises later than MCLK
rising edge

both high to TSX Low

TSX disabled
Setup time, DR Valid to MCLK Low

invalid

0.85Vdd

1MΩ

1.544

2.048

4.096

8.192

10 ns

10 ns

15 40 ns

15 40 ns

5ns
5ns

Vdd V

MHz

15 ns

15 ns

20 ns

33/45

STLC5048

ELECTRICAL CHARACTERISTCS
Figure 4.

MCLK

T

HBF

T

SFB

FSX

T

DMD

DX

T

DMT

TSX

T

T

HBF

FSR

DR

12345678910

T

HBF

T

DFD

T

DMT

SFB

T

T

SDM

HBF

(continued)

T

HDM

T

FM

T

ZMT

T

WMH

T

WML

T

RM

12345670

T

ZMT

12345670

D94TL157

SERIAL CONTROL PORT TIMING

Symbol Parameter Test Condition Min. Typ. Max. Unit

fcclk Frequency of CCLK 8 MHz

twch Period of CCLK High Measured from VIH to VIH 40 ns

twcl Period of CCLK Low Measured from VIL to VIL 40 ns

trc Rise time of CCLK Measured from VIL to VIH 20 ns

tfc Fall time of CCLK Measured from VIH to VIL 20 ns
thcs Hold time, CCLK low to CS low 10 ns
thsc Hold time, CCLK low to CS high 10 ns
tssc Setup time, CS transition to CCLK

10 ns

Low

tdsd

Delay time, CS low to CO data valid

20 ns
tcso CS off time 5 us
tsdc

Setup time, CI. Data in to CCLK low

10 ns
thcd Hold time, CCLK low to CI invalid 10 ns
tdcd Delay time, CCLK low to CO Data

30 ns

Out Valid

tddz Delay Time, CS or CCLK9 high to

CO high impedance

Pull up resistor = 1KOhm
Cload = 30pF

30 ns

34/45

STLC5048

ELECTRICAL CHARACTERISTCS

(continued)

Figure 5.

t

RC

CCLK

CS

CI

CO

t

HCS

12345678

t

SSC

SLIC CONTROL INTERFACE TIMING (dynamic configuration)

Symbol Parameter Test Condition Min. Typ. Max. Unit

Tcs Chip Select repetition rate 31.25 µ
tcsw Chip select pulse width 3.9 µ
tdcsl Data out valid to CS low 1.95 ns

t

t

SDC

FC

t

HSC

t

HCD

12345670

D00TL471

t

SCS

t

CSO

t

WCH

t

WCL

t

DSD

t

DCD

1234567

s
s

tscsh Data out held after CS high 1.95 ns
tscsh Set up time Data in to CS high 50 ns
thcsh Hold time data in to CS high 10 ns

Figure 6. SLIC Control port timing

t

t

DIV

OUT
CH0

DII

t

DON

OUT
CH1

31.25µs (32KHz)

OUT
CH2

OUT

CH3

OUT
CH0

OUT
CH1

CS1

CS2

CS3

CS4

IO

(OUT)

t

DOA

IO

(IN)

IN

CH0

IN

CH1

IN

CH2

IN

CH3

IN

CH0

IN

CH1

D99TL460

35/45

STLC5048

ELECTRICAL CHARACTERISTICS

(continued)

TRANSMIT TRAN SFER CHARACTERISTIC S

(all tests are performed in absolute gain condition (TXG = GTXn = 0dB) unless otherwise specified).

Symbol Parameter Test Condition Min. Typ. Max. Unit

Absolute level at 0 dBm0 are:

60 mVrms

TXG = 0dB, GTXn = 0dB

GXA Transmit gain Absolute accuracy -0.15 0.15 dB

GXAG Transmit gain variation with programmed

-0.2 0.2 dB

gain (within 3 dB from max dig. level)

GFX Gain variation with frequency (relati ve to

gain at 1004Hz); 0dBm0 input signal

50 Hz
60Hz
200Hz
300-3000Hz
3400Hz
4000Hz
4600Hz and above

-1.8

-0.15

-0.7

-20

-20
0

0.15
0

-14.0

-32.0

GAXT Gain variation with temperature -0.10 0.10 dB

GAXE Gain variation with Supplies +/- 5%

-0.05 0.05 dB

0dBm0 Input Signal

GTX Gain Tracking with Tone (1004Hz Mu

Law, 820Hz A Law)

(1)

GSX = 3 to -40dBm0
GSX = -40 to -50dBm0
GSX = -50 to -55dBm0

-0.2

-0.4

-1.2

0.2

0.4

1.2

QDX Quantization Distortion with Tone

(1004Hz Mu Law, 820Hz ALaw)

VFXI = +3dbm0
VFXI = 0 to -30dBm0
VFXI = -40 dBm0
VFXI = -50 to -55 dBm0

NCT Transmit Noise C Message Weighted

33
36
30
15

12

dBrnCo

(Mu and A Law)

NPT Transmit Noise Psophometric Weighted

(2)

DAX

@ 0dBr, Zadm=600Ohm
Absolute Delay

(3)

B = 0, Z = 0, X = R = 1 462 587 µS

-68 dBm0 p

DPXM Single Frequency Distortion

(Mu Law 0dBm0 Sinewave @ 1004Hz) -46

DPXA Single Frequency Distortion

(A Law 0dBm0 Sinewave @ 820Hz) -46

GSPX Out of Band Spurious Noise 61mVrms at VFXI

-39 dBm0

4200Hz to 72kHz

dB

dB

dB

dB

dB

(1) VFXI=106mVrms, TXG=+3.52dB, GTX=-8.308dB (levels and gain condition eqivalent to 0dBr with Zadm = 600 Ohm on the application)
(2) TXG=+3.52dB, GTX=-8.308dB (gain conditi on eqivalen t t o 0dB r with Zadm = 60 0 Ohm on the appli cation)

(3) The max value includes 125µsec for th e t ime slot synchronization

36/45

STLC5048

ELECTRICAL CHARACTERISTICS

(continued)

RECEIVE TRANSFER CHARACTERISTICS

(all tests are performed in absolute gain condition (RXG = GRXn = 0dB) unless otherwise specified).

Symbol Parameter Test Condition Min. Typ. Max. Unit

Absolute levels at 0 dBm0 are:

547 mVrms

RXG = 0dB, GRXn = 0dB

GRA Transmit gain Absolute accuracy -0.15 0.15 dB

GRAG Receive Gain Variation with

-0.2 0.2 dB
programmed gain (within 3 dB from max
dig. level)

GFR Gain variation with frequency (relative to

gain at 1004Hz); 0dBm0 input signal

Below 200Hz
200Hz
300-3000Hz
3400Hz
4000Hz

-0.25

-0.15

-0.7

0.115

0.15

0.15
0

-14

GART Gain variation with temperature 0 to 70 °C -0.10 0.10 dB

GARE Gain variation with

-0.05 0.05 dB
Vcc=Vdd= 3.3V +/- 5%
0dBm0 Input Signal

GTR Gain Tracking with Tone (1004Hz Mu

Law, 820Hz ALaw)

DR = 3 to -40dBm0
DR = -40 to -50dBm0
DR = -50 to -55dBm0

-0.2

-0.4

-1.2

0.2

0.4

1.2

QDR Quantization Distortion with Tone

(1004Hz Mu Law, 820Hz ALaw)

DR = 3 dBm0
DR = 0 to -30dBm0
DR = -40 dBm0
DR = -50 to -55dBm0

NCR Receive Noise C Message Weighted

33
36
30
15

811

dBrnCo

(Mu Law)

NPR Receive Noise Psophometric Weighted

-79 dBm0p

(A Law)

DAR

Absolute Delay

(2)

B = Z = 0, X = R = 1 325 450 µs

DPR1 Single Frequency Distortion

(0dBm0 Sinewave @ 1004Hz) -46

GSPR

Out of band spourious Noise

0dBm0 DTMF tone at DR -60 dB
0dBm0 180 to 3600Hz

-43 dB

Sinewave at DR

OBN

Out of Band Noise

(1)

Integral measure
from 3.4 to 128kHz

= GRX = 0dB

G

TX

G

= 0dB; GRX = -7dB

TX

Spectral measure

-48

-51

dBm
dBm

-70 dBm
from 3.4 to 200kHz
in B/W = 30Hz

(1) Values rel ated to the application including the external filter o n RX. The maesure is referr ed to the signal replicas .
(2) As note 3 a t page 36

dB

dB

dB

dB

37/45

STLC5048

ELECTRICAL CHARACTERISTCS

(continued)

SUPPLY REJECTION AND CROSSTALK

Symbol Parameter Test Condition Min. Typ. M ax. Unit

PSRR Power Supply Rejection Ratio

0 to 70°C 42 65 dB

1KHz, 50mVrms

CTX-R Transmit to Receive Crosstalk (Input

-76 dB

signal 200Hz to 3450Hz at 0dBm0)

CTR-X Receive to Transmit Crosstalk (Input

-76 dB

signal 200Hz to 3450Hz at 0dBm0)

CT-ICH Inter Channel Crosstalk, TX and RX

-78 dB

direction.
Input 200 to 3450 Hz at 0dBm0 at VFXI
of one channel; all other VFXI inputs
and all DR inputs receive idle signal.
Output is measured at DX of the 3 idle
channels.

Input of 200 to 3450 Hz at 0dBm0 PCM
at DR on ione channel. All other DR
inputs and all VFXI inputs receive idle
signal. Output is measured at VFRO of
the 3 idle channels

Figure 7. Group Delay Distortion Mask

Rx direction

Tx direction

Delay

(µs)
600

500

400

300

200

100

Delay

(µs)

600

500

400

300

200

100

Rx

0

500 1000 1500 2500 3000 f(Hz)

2000

Tx

D02TL523

D02TL524

38/45

0

500 1000 1500 2500 3000 f(Hz)

2000

APPENDIX A

STLC5048 absolute gains in kit with L3235N/STLC3080

Figure 8. STLC5048 in kit with STLC3080 AC application diagram.

STLC5048

DR

GRX

ECO

CANCELING

CHANNEL

FILTER

+

Z

SYNTHESIS

VFRO

RX

2

STLC5048

R

TIP

1

-1
RING

R

P

Zadm

Iline

P

S

CAC ILTF

RDC

Iline/100

DX

GTX

+

CHANNEL

FILTER

VFXI

TX

D00TL472

RS

1

R

8200Ω

Figure 9. STLC5048 in kit with L3235N AC application diagram.

R

DR

DX

GRX

GTX

STLC5048

ECO

CANCELING

+

CHANNEL

FILTER

CHANNEL

FILTER

+

Z

SYNTHESIS

VFRO

VFXI

RX

TX

D00TL473

1

2

-1

RPC

1

R

S

4100Ω

TIP

RING

CAC IL

R

P

Zadm

Iline

P

Iline/50

In Fig.8 is shown the application diagram of the STLC5048 in kit with the STLC3080 SLIC. The figure is related
to the AC path as the STLC5048 doesn't perform any DC processing.

The only DC feature performed by STLC5048 is the Off-Hook and Limitation Threshold programmability.
The same application diagram for the AC processing can be applied to the kit with the L3235N (as shown in Fig.

9): the only differences are the following:
The scaling factor of the Iline is 50
Rs value is 4.1 Kohm.
The imoedance synthesis is fully performed by STLC5048; th e L3235N SLIC (or the STLC3080) us ed i n ki t w ith

the STLC5048 just splits the AC/DC component of Iline, scales it and traduces it into a voltage via RS.
As shown in Fig. 3, the scaled current is converted into a voltage through the external resistor Rs = 4100 Ohm

(8200 Ohm for the STLC3080): this value is fixed (i.e. independent on the administration): the attenuation be­tween VLINE and VFXI is dependent on the administration.

Considering the TX gain we can proceed as follows for the gain calculation:
TXG = 0dB
GX = 0dB

39/45

STLC5048

(As reported in the absolute gain levels with 61Vrms at VFXI and GX=0dB, the DX output is 0dBm0).
For instance let's calculate which TX gain to program if +4.2dBr @ 600 Ohm is to be set:
VLINE = 0dBm @ 600Ohm

VFXI

VLINE

------------------ -

600

1

------

⋅⋅=

4100

50

In case of STLC3080 the scaling factor is 100 (instead of 50) while the Rs value is 8200 (instead of 4100) so
the result is the same.

FXI

VLINE

------------------ -

600

⋅⋅=

1

--------- -

100

8200

Refering to the formula (1), to have DX equal to 4.2dB with VLINE=0dBm GX must be set to GX = 4.2 - 4.78 =

-0.58dB.

Figure 10. Absolute gain in TX path.

1/100 for

STLC3080

GX TXG

VFXI

R

S

4100Ω

STLC5048 L3235N

(8200 for

STLC3080)

1/50DX

VLINE

Iline

Zadm

40/45

VFXI = (-Iline/50)*4100 for L3235N
VFXI = (-Iline/100)*8200 for STLC3080

D00TL474

APPENDIX B

STLC5048 Application Diagrams

Figure 11. STLC5048 plus L3235N/L324 kit application diagram

STLC5048

CC

V

GND

V100

10µF

82Ω

82Ω

10µF

5

7

0.1µF0.1µF

L3234

2

63

1

4

VA

GND

4.7µF

VRING

CC

CC

V

0.1µF

CS

CS

ZB

ZS=4100Ω

DD

V

0.1µF

VDDV

CC

V

CAC

29

10

7

SS

6

100nF

CAC

100µF

IL

12

RX

VFRO0

D1

18

2.2KΩ

TIP

20Ω

P2

R

1N4007

40Ω

TIP

38

1M

10nF

PROTECTION

OVERVOLTAGE

RT

1MΩ

D2

1N4007

P1

R

11

ZA

ZAC

150Ω

10nF

SUB

RING

40Ω

RING

40

43

20Ω

P2

R

P1

R

VREG

44

L3235N

9

TX

OH

CTX 100nF

IO0

VFXI0

TEXT

MJE350

BASE

22

31

RNG

IO1

RF

39K

CF

390nF

CR

4.7µF

9.1K

RLIM

to 35K

BAT

V

VPOL

LIM

REF

20

241435

32

GDK

IO4

3

BGND

GKF

13

CC

V

IO11

RTF

34

25

27

28

SBY

PUNEG

IO2

IO3

BAT

AGND V

CVSS CVB

17239

SS

V

IO12(CS0)

IO13(CS1)

RR

51K

39K

RGF

CGF

390nF

0.1µF0.1µF

CVCC

IO14(CS2)

IO15(CS3)

V

0.1µF

VFRO1

VFXI1

BAT

SS

V

CC

V

VFRO2

VFXI2

VFRO3

VFXI3

D98TL381B

TSX

STLC5048

INT

RES

CS

CO

CCLK

SERIAL

CONTROL

CI

PORTS

EE

V

GND V

DX

DR

FS

MCLK

41/45

STLC5048

Figure 12. STLC5048 plus STLC3080 ap plica tion diagram.

(5V)

CC

(3.3V) V

DD

V

BGND REL0

AGND

CC

V

DD

V

REL1

12

133729109

ZAC1

21

VREL

RELR

14

150Ω

ZAC

TIP

P2

R

RT

P1

R

TIP

39

LCP

PCD

40

1511

BAT

V

P1

R

RING

RING

38

P2

R

RS1R

RT1

28

RR

VRING

BAT

V

QEXT

BAT

V

CSRV

CREV

BGND and AGND must be

D99TL459C

shorthed together on the line card

CRT

BASE

VBAT

CVB

CSRV

34

CREV

33

SLICs

TO OTHER

REF

IREF

32

RLIM

31

RLIM

ITH

S2

RT2

VREG

27

363516

RTH

STLC3080

26 25

24

20

19

18

ZB

RS

RS

41

22

RX

MODE

44

17

TX

DET

43

D0

GDK/AL

3

6

7

1

CSOUT

CSIN

2

RES

4

5

D1

R0

R1

D2

83042 11

CKRING CRT

23

ILTF RDCCAC

TTXIN

RDC

CAC

CTTX

RTTX

RDA

42/45

(3.3V)

CC

V

CC

10nF

IO7

IO8

IO9

IO10

6160595857

IO11

100nF

VFRO0

1M10nF

IO5

IO6

62

TO OTHER SLICs

CS1

CS2

CS3

CS0

28

295353393842434846

CTX 100nF

2.2KΩ

IO0

IO1

IO2

IO3

VFXI0

33

35192021222324

IO4

VFRO1

VFXI1

TTX

SLICs

TO OTHER

VFRO2

VFXI2

VFRO3

VFXI3

Components

needed only for

metering pulse injection

ITH

0.1µF

CC

V

ILIM

EE

STLC5048

V

8941

GND V

SS

DD

V

V

DD

V

SUB

0.1µF

DXA

10

11

DRA

DXB

15

DRB

14

16

FS

MCLK

PCM

INTERFACE

13

12

27

54

3

475

6

TSX

M1

M0

INT

CI

CS

CO

CCLK

PORTS

SERIAL

CONTROL

CAP

VBG

49 34 47

40

CAP

0.1µF

STLC5048

APPENDIX C

Power Up Sequence

The DSP after an HW (M1=0) or SW reset ( CONF[7]=1) or a Power-on reset (POR) has to perform the INIT
proram. To do it at least one channel must be set in active mode.

After that, (2 FS are required), the INIT bit in the CTRLACK register is set to 1 and the RAM can be written and
read. It must be noted that to program the device the MCLK and FS signals must be applied to the device.

Following, the correct sequence that must be used in order to program the device.

Power on sequence

wait 5 FS signals for PLL locking
CONF=BF Sw Reset enabled after reset
write CONF=3F Sw Reset disabled
write CONF=30 All Channel Active
wait 2 FS signals
read CTRLACK=03 Check INIT bit =1

Before to start the coefficent download, one or more channels must be sel ected using the COMEN register. The
download can be done k eeping the devic e in Ac tive mode (at l east one channel active) or in P ower Down mode
(all channels in Power Down). If the second choice is selected, the PDR bit in the COMEN register must be set
to 0 (internal RAM active also in Power Down mode).

43/45

STLC5048

DIM.

mm inch

MIN. TYP. MAX. MIN. TYP. MAX.

A 1.60 0.063
A1 0.05 0.15 0.002 0.006
A2 1.35 1.40 1.45 0.053 0.055 0.057

B 0.18 0.23 0.28 0 .007 0.009 0.011

C 0.12 0.16 0.20 0.0047 0.0063 0.0079

D 12.00 0.472

D1 10.00 0.394
D3 7.50 0.295

e 0.50 0.0197

E 12.00 0.472
E1 10.00 0.394
E3 7.50 0.295

L 0.40 0.60 0.75 0.0157 0.0236 0.0295

L1 1.00 0.0393

K 0°(min.), 7°(max.)

OUTLINE AND

MECHANICAL DATA

TQFP64

D

D1

TQFP64

3348

32

E3D3E1

17

16

E

L1

L

0.10mm

Seating Plane

K

49

B

64

1

e

A1

B

A

A2

C

44/45

STLC5048

ESD - The STMicroelectronics Internal Quality Standards set a target of 2 KV that each pin of the device should withstand in a series of tests
based on the Hu man Bo dy Mode l (MI L-STD 88 3 Met hod 30 15) : wit h C = 100 pF; R = 1500W and perfo rmi ng 3 p ulse s for each p in v ersus
VCC and GND .

Device characterization showed that, in front of the STMicroelectronics Internaly Quality Standards, pin 25 of STLC5048 withstand at least
1000V.

The above points are not expected to represent a pratical limit for the correct device u tilization nor for its reliability in the field. Nonetheless
they must be mentionned in connection with the applicability of the different SURE 6 requirements to STLC5048.

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implic ation or otherwise under any patent or patent r i ghts of STM i croelectronics. Specificat i ons menti oned in thi s publication are s ubj ect
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics produ ct s are not
authorized for use as cri tical comp onents in lif e support dev i ces or systems wi thout exp ress written approval of STMicroe l ectronics.

The ST logo is a registered trademark of STMicroelectronics

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45/45