The SuperMESH™ series is obtained thro ugh an
extreme optimization of ST’s well established
stripbased PowerMESH™ layout. In addition to
pushing on-resistance significantly down, special
care is taken to ensure a very good dv/dt capability
for the most demanding applications. Such series
complements ST full range of high voltage MOSFET s including revolutionary MDmesh™ products.
Avalanche Current, Repetitive or Not-Repetitive
(pulse width limited by T
max)
j
Single Pulse Avalanche Energy
(starting T
= 25 °C, ID = IAR, VDD = 50 V)
j
4.5A
230mJ
Table 6: Gate-Source Zener Diode
SymbolParameterTest ConditionsMin.Typ.Max.Unit
BV
GSO
Gate-Source Breakdown
Igs=± 1mA (Open Drain)30V
Voltage
PROTECTION FEATURES OF GATE-TO-SOURCE ZENER DIODES
The built-in back-to-back Zener diodes have specifically been designed t o enhance not only t he device’s
ESD capability, but also to make them safely absorb possible voltage transients that may occasionally be
applied from gate to source. In this respect the Zener voltage is appropriate to achieve an efficient and
cost-effective intervention to p r otect the device’s integrity. These integrated Zener diodes thus avoid the
usage of external components.
2/12
Page 3
STP5NK90Z - STF5NK90Z
ELECTRICAL CHARACTERISTICS (T
=25°C UNLESS OTHERWISE SPECIFIED)
CASE
Table 7: On /Off
SymbolParameterTest ConditionsMin .Typ.Max.Unit
V
(BR)DSS
Drain-source Breakdown
ID = 1 mA, VGS = 0900V
Voltage
I
I
V
GS(th)
R
DS(on
DSS
GSS
Zero Gate Voltage
Drain Current (V
GS
= 0)
Gate-body Leaka ge
Current (V
DS
= 0)
Gate Threshold Voltage
Static Drain-source On
V
= Max Rating
DS
V
= Max Rating, TC = 125°C
DS
V
= ± 20 V± 10µA
GS
V
= VGS, ID = 100 µA3
DS
3.75
1
50
4.5V
VGS = 10 V, ID = 2.25 A22.5Ω
Resistance
Table 8: Dynamic
SymbolParameterTest ConditionsMin.Typ.Max.Unit
g
(1)Forward Transconductance VDS = 15 V , ID = 2.25 A4.8S
fs
C
OSS eq
C
C
C
t
d(on)
t
d(off)
Q
Q
Q
iss
oss
rss
t
r
t
gs
gd
f
g
Input Capacitance
Output Capacitance
Reverse Transfer
Capacitance
(3).Equivalent Outpu t
Capacitance
Turn-on Delay Time
Rise Time
Turn-off-Delay Time
Fall Time
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
= 25 V, f = 1 MHz, VGS = 01160
V
DS
105
21.5
VGS = 0 V, VDS = 0 to 720 V65.5pF
= 450 V, ID = 2.2 A,
V
DD
RG = 4.7 Ω, V
GS
(see Figure 19)
= 10 V
27
7.2
52
19
= 720 V, ID = 4.4 A,
V
DD
VGS = 10 V
(see Figure 22)
41.5
6.9
21.9
58nC
µA
µA
pF
pF
pF
ns
ns
ns
ns
nC
nC
Table 9: Source Drain Diode
SymbolParameterTest ConditionsMin.Typ.Max.Unit
I
SD
I
SDM
(1)
V
SD
t
rr
Q
rr
I
RRM
t
rr
Q
rr
I
RRM
(1) Pulsed: Pulse du rat i on = 300 µs, du ty cycle 1.5 % .
(2) Pulse width limited by safe operating area.
(3) C
oss eq.
Source-drain Current
(2)
Source-drain Current (pulsed)
Forward On Voltage
Reverse Recovery Time
Reverse Recovery Charge
Reverse Recovery Current
Reverse Recovery Time
Reverse Recovery Charge
Reverse Recovery Current
is defined as a constant equivalent capacitance giving the same charging time as C
ISD = 4.5 A, VGS = 0
= 4.5 A, di/dt = 100 A/µs
I
SD
VDD = 35V
(see Figure 20)
= 4.5 A, di/dt = 100 A/µs
I
SD
V
= 35V, Tj = 150°C
DD
(see Figure 20)
518
3.2
12.2
712
4.66
13.1
when VDS increase s from 0 to 80% V
oss
4.5
18
1.6V
A
A
ns
µC
A
ns
µC
A
DSS
3/12
.
Page 4
STP5NK90Z - STF5NK90Z
Figure 3: Safe Operating Area For TO-220
Figure 4: Safe Operating Area For TO-220FP
Figure 6: Thermal Impedance For TO-220
Figure 7: Thermal Impedance For TO-220FP
Figure 5: Output Characteristics
4/12
Figure 8: Transfer Characteristics
Page 5
STP5NK90Z - STF5NK90Z
Figure 9: Transconductance
Figure 10: Gate Charge vs Gate-source Voltage
Figure 12: Static Drain-source On Resistance
Figure 13: Capacitance Variations
Figure 11: Normalized Gate Threshold Voltage
vs Tem pera ture
Figure 14: Normal ized On R esistance vs Temperature
5/12
Page 6
STP5NK90Z - STF5NK90Z
Figure 15: S ource-Drain Forward Char acteristics
Figure 16: Normalized Breakdown Voltage vs
Temp erature
Figure 17: Avalanche Energy vs Star ting Tj
6/12
Page 7
STP5NK90Z - STF5NK90Z
Figure 18: Unclamped Inductive Load Test Circuit
Figure 19: Switching Times Test Circuit For
Resistive Load
Figure 21: Unclamped Inductive Wafeform
Figure 22: Gate Charge Test Circuit
Figure 20: Test Circuit For Inductive Load
Switching and Diode Recovery Times
7/12
Page 8
STP5NK90Z - STF5NK90Z
In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These
packages have a Lead-free second level interconnect . The category of second level interconnect is
marked on the package and on the inner box label, i n compliance with JEDEC Standard JESD97. The
maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an
ST trademark. ECOPACK specifications are available at: www.st.com
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is gra nted
by implic ati o n or ot h er wis e und er an y pat ent or pa te nt r igh ts of STMi cr oe l ect ro ni cs . Sp ec if i cat i on s ment i o ned i n th is p ub li c ati on ar e s ubj ec t
to change without not ice. This publication supersedes and replaces all information previously sup plied. STMicroelectr onics products are not
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