Datasheet STG3220 Datasheet (ST)

Low voltage high bandwidth dual SPDT switch

Features

■ Ultra low power dissipation:

–I

= 1 μA (max.) at TA = 85 °C

CC

■ Low "ON" resistance:

–R
–R

■ Wide operating voltage range:

–V

■ 4.3 V tolerant and 1.8 V compatible threshold

on digital control input at V

■ Typical bandwidth (-3 dB) at 800 MHz on all

channels

■ USB (2.0) high speed (480 Mbps) signal

switching compliant

■ Integrated fail safe function

■ Interrupt function to indicate to the processor

that the device is in dedicated port charging
mode

■ Latch-up performance exceeds 500 mA per

JESD 78, Class II

■ ESD performance exceeds JESD22:

– Dn pins: 4000-V human body model

– All other pins: 2000-V human body model

Applications

■ Mobile phones

Table 1. Device summary

= 4.8 Ω (TA = 25 ºC) at VCC = 4.3 V

ON

= 5.9 Ω (TA = 25 ºC) at VCC = 3.0 V

ON

(opr) = 1.65 V to 4.3 V

CC

= 2.3 V to 3.0 V

CC

(A114-A)

(A114-A)

STG3220

QFN10

(1.8 x 1.4 mm)

Description

The STG3220 is a high-speed CMOS low voltage
dual analog SPDT (single pole dual throw) switch
or 2:1 multiplexer/de-multiplexer switch fabricated
in silicon gate C
to operate from 1.65 V to 4.3 V, making this
device ideal for portable applications.

The SEL input is provided to control the switch.
The switch nS1 is ON (connected to common
ports Dn) when the SEL input is held high and
OFF (high impedance state exists between the
two ports) when SEL is held low; the switch nS2 is
ON (it is connected to common port Dn) when the
SEL input is held low and OFF (high impedance
state exists between the two ports) when SEL is
held high. STG3220 has an integrated fail safe
function to withstand over-voltage condition when
the device is powered off.

The STG3220 also has an interrupt pin which
sends a signal to the processor when the device
is in dedicated port charging mode. Additional key
features are fast switching speed, break-before­make-delay time and ultra low power
consumption. All inputs and outputs are equipped
with protection circuits against static discharge,
giving them ESD immunity and transient excess
voltage.

2

MOS technology. It is designed

Order code Package Packaging

STG3220QTR QFN10 (1.8 x 1.4 mm) Tape and reel

May 2009 Doc ID 15647 Rev 1 1/23

www.st.com

23

Contents STG3220

Contents

1 Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2 Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

3 Dedicated port charging detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

4 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

4.1 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

6 Test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

7 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

2/23 Doc ID 15647 Rev 1

STG3220 Pin settings





4

3



1 Pin settings

Figure 1. Pin connection (top through view)

3



).





$



6##

3%,



'.$

$



 



3

Table 2. Pin description

Pin number Symbol Name and function

1 INT Interrupt

2 VCC Positive supply voltage

3 SEL Control

4 2S1 Independent channel for switch 2

5 2S2 Independent channel for switch 2

6 D2 Common channel for switch 2

7 GND Ground (0 V)

8 D1 Common channel for switch 1

9 1S2 Independent channel for switch 1

10 1S1 Independent channel for switch 1

Doc ID 15647 Rev 1 3/23

Logic diagram STG3220

2 Logic diagram

Figure 2. Logic block diagram

1S1

D1

1S2

2S1

D2

2S2

SEL

Figure 3. Logic equivalent circuit

$N

N3

N3

3%,

!-6

Table 3. Truth table

SEL Switch nS1 Switch nS2

HONOFF

LOFF

(1)

1. High impedance.

(1)

ON

4/23 Doc ID 15647 Rev 1

STG3220 Dedicated port charging detection

3 Dedicated port charging detection

The STG3220 has a built-in dedicated port charging detection circuit to detect the condition
when the USB D+/D- lines are both in high state. When this occurs, the device sends an
interrupt signal to the processor to indicate that the connected USB device is in dedicated
port charging mode.

Figure 4. Interrupt function logic representation

INT

D1

D2

1S1
1S2

2S1
2S2

SEL

Doc ID 15647 Rev 1 5/23

Maximum rating STG3220

4 Maximum rating

Stressing the device above the rating listed in the “Absolute maximum ratings” table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the operating sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.

Table 4. Absolute maximum ratings

Symbol Parameter Value Unit

V

CC

V

V

V

I

IKC

I

IK

I

OK

I

O

I

OP

or I

I

CC

P

T

stg

T

Supply voltage -0.5 to 5.5 V

DC input voltage -0.5 to VCC + 0.5 V

I

DC control input voltage -0.5 to 5.5 V

IC

DC output voltage -0.5 to VCC + 0.5 V

O

DC input diode current on control pin (V

DC input diode current (V

< 0V) ±50 mA

SEL

< 0V) -50 mA

SEL

DC output diode current ±20 mA

DC output current ±128 mA

DC output current peak (pulse at 1ms, 10% duty cycle) ±300 mA

DC VCC or ground current ±100 mA

GND

Power dissipation at TA = 70 °C

D

(1)

Storage temperature -65 to +150 °C

Lead temperature (10 sec) 300 °C

L

1. Derate above 70 °C by 18.5 mW/°C.

4.1 Recommended operating conditions

Table 5. Recommended operating conditions

1120 mW

Symbol Parameter Value Unit

V

CC

V

V

V

T

op

dt/dv

Supply voltage 1.65 to 4.3 V

Input voltage 0 to V

I

Control input voltage 0 to 4.3 V

IC

Output voltage 0 to V

O

Operating temperature -40 to 85 °C

Input rise and fall time control
input

6/23 Doc ID 15647 Rev 1

= 1.65 V to 2.7 V 0 to 20

V

L

= 3.0 to 4.3 V 0 to 10

V

L

CC

CC

V

V

ns/V

STG3220 Electrical characteristics

5 Electrical characteristics

Table 6. DC specifications

Val ue

Symbol Parameter

V

(V)

CC

Test

conditions

= 25 °C -40 to 85 °C

A

Min Typ Max Min Max

UnitT

V

V

V

IH-INT

V

IL-INT

V

OL-INT

High level input

IH

voltage

Low level input

IL

voltage

High level input
voltage for INT

Low level input
voltage for INT

Low level output
voltage for INT

1.65 – 1.95

0.65 V

CC

––0.65VCC–

2.3 – 2.5 1.2 – – 1.2 –

2.7 – 3.0 1.3 – – 1.3 –

–

3.3 – 3.6 1.4 – – 1.4 –

4.3 1.6 – – 1.6 –

1.65 – 1.95

– – 0.25 – 0.25

2.3 – 2.5 – – 0.25 – 0.25

2.7 – 3.0 – – 0.25 – 0.25

–

3.3 – 3.6 – – 0.30 – 0.30

4.3 – – 0.40 – 0.40

4.3 – 2.4 – – 2.4 – V

4.3 – – – 0.9 – 0.9 V

4.3 I

1.8

= 4 mA – – 0.40 – 0.50 V

O

– 15.1 17.8 – –

V

V

R

PEAK

Switch ON peak
resistance

2.7 – 6.4 8.0 – –

3.0 – 5.9 7.5 – –

3.7 – 5.0 6.5 – –

= 0 V to

V

S

V

CC

= 8 mA

I

S

Ω

4.3 – 4.8 6.1 – –

= 3 V

V

3.0

ON

Switch ON
resistance

R

3.0

S

I

= 8 mA

S

= 0.4 V

V

S

IS = 8 mA

–4.25.4––

Ω

–5.77.0––

Doc ID 15647 Rev 1 7/23

Electrical characteristics STG3220

Table 6. DC specifications (continued)

Val ue

Symbol Parameter

V

(V)

CC

Test

conditions

= 25 °C -40 to 85 °C

A

Min Typ Max Min Max

UnitT

∆R

R

I

FLAT

OFF

I

IN

I

CC

ON resistance
match between

ON

channels

ON resistance
flatness

OFF state
leakage current
(Sn), (D)

Input leakage
current

Quiescent supply
current

(2)

(1)

1.8

–––––

2.7 – – – – –

3.0 – 0.1 – – –

3.7 – – – – –

VS at RON max
IS = 8 mA

Ω

4.3 – – – – –

= 0 V to

V

S

1.8

1.8

2.7 – 2.2 – – –

3.0 – 1.8 – – –

3.7 – 1.6 – – –

0.4 V
= 8 mA

I

S

VS = 0 V to
VCC

= 8 mA

I

S

–4.5–––

–9.0–––

Ω

4.3 – 1.6 – – –

4.3 V

0 to 4.3

1.65 to 4.3

= 0.3 or 4 V -20 – 20 -100 100 nA

S

= 0 to

V

SEL

4.3 V

V

SEL

GND

= VCC or

-0.2 – 0.2 -1.0 1.0 µ

-0.2 0.2 -1.0 1.0 µ

A

A

V

= 1.65 V – ±37 ±50 – ±100

Quiescent supply

I

CCLV

current for low

4.3

voltage driving

1. ΔRON = max |mSN-nSN|, where m = 1, 2 and n = 1, 2, N = 1, 2

2. Flatness is defined as the difference between the maximum and minimum value of on-resistance as measured over the
specified analog signal ranges.

SEL

= 1.80 V – ±33 ±40 – ±50

SEL

V

= 2.60 V – ±11 ±20 – ±30

SEL

8/23 Doc ID 15647 Rev 1

µAV

STG3220 Electrical characteristics

Table 7. AC characteristics (CL = 35 pf, RL: 50 Ω, TR = Tf ≤ 5 ns)

Symbol Parameter

Val ue

V

(V)

CC

Test

conditions

= 25 °C -40 to 85 °C

A

UnitT

Min Typ Max Min Max

t

PLH, tPHL

t

ON

t

OFF

t

D

Propagation
delay

Turn on time

Turn off time

Break-before­make time delay

1.65 - 1.95

–0.21– ––

2.3 - 2.7 – 0.15 – – –
–

3.0 - 3.3 – 0.14 – – –

3.6 - 4.3 – 0.13 – – –

1.65 - 1.95 V

2.3 - 2.7

3.0 - 3.3 – 15 17 – 20

= 0.8 V – 34 – – –

S

–2023–26

V

= 1.5 V

S

3.6 - 4.3 – 13 15 – 17

1.65 - 1.95 V

2.3 - 2.7

3.0 - 3.3 – 14 16 – 18

= 0.8 V – 27 – – –

S

–1922–25

V

= 1.5 V

S

3.6 - 4.3 – 11 13 – 14

1.65 - 1.95
C

= 35 pF

2.3 - 2.7 – 6 – – –

L

–10–––

RL = 50 Ω

3.0 - 3.3 – 4 – – –
= 1.5 V

V

S

3.6 - 4.3 – 3 – – –

ns

ns

ns

ns

Doc ID 15647 Rev 1 9/23

Electrical characteristics STG3220

Table 8. AC electrical characteristics (CL = 5 pF, RL = 50 Ω, TA = 25 °C)

Value

Symbol Parameter

V

(V)

CC

Test

conditions

T

= 25 °C

A

-40 to 85 °C

Unit

Min Typ Max Min Max

–3.9– – –

pC

Q Charge injection

1.65

2.3 – 4.8 – – –

3.0 – 5.2 – – –

CL = 100 pF
V

= 0 V

GEN

= 0 Ω

R

GEN

4.3 – 6.4 – – –

OIRR OFF isolation

(1)

1.65 – 4.3

Xtalk Crosstalk 1.65 – 4.3

BW -3dB bandwidth 3.0 – 4.3

C

Control pin input

IN

capacitance

Sn port

ON

capacitance
when switch is

3.3 f = 240 MHz – 6 – – –

C

enabled

Sn port

C

OFF

capacitance
when switch is

3.3 f = 240 MHz – 2 – – –

disabled

= 1V

V

S

f = 1 MHz

RMS

,

–-78– – –

Signal = 0 dBm

= 1 V

V

S

f = 10 MHz

RMS

,

–-57– – –

Signal = 0 dBm

= 1 V

V

S

f = 1 MHz

RMS

,

–-78– – –

Signal = 0 dBm

V

= 1V

S

f = 10 MHz

RMS

,

–-58– – –

Signal = 0 dBm

RL = 50 Ω
Signal = 0 dBm

V

= 0V –2–––

CC

–800– – –MHz

dB

dB

pF

1. Off isolation = 20 Log10 (VD/VS), VD = output, VS = input to off switch.

10/23 Doc ID 15647 Rev 1

STG3220 Electrical characteristics

Table 9. USB related AC electrical characteristics

Val ue

Symbol Parameter

V

CC

(V)

Tes t

conditions

= 25 °C -40 to 85 °C

A

Min Typ Max Min Max

UnitT

t

SK(0)

t

SK(P)

T

J

Channel-to­channel skew

3.0 - 3.6 C

Skew of
opposite
transition of the

3.0 - 3.6 C

same output

Total jitter 3.0 - 3.6

= 10 pF – 26 – – – ps

L

= 10 pF – 60 – – – ps

L

RL = 50 Ω

= 10 pF

C

L

= tF =

t

R

–130– – –ps

750 ps
at 480 Mbps

Doc ID 15647 Rev 1 11/23

Test circuit STG3220

6 Test circuit

Figure 5. ON resistance

I

DS

V

V

CC

S1

D

VS

S2

GND

IN

GND

CS14071

12/23 Doc ID 15647 Rev 1

STG3220 Test circuit

Figure 6. OFF leakage

V

CC

I

S(OFF)

A

V

SS

V

CC

Figure 7. OFF isolation

I

D(OFF)

D

A

V

D

S2

IN

GND

CS14081

V

CC

S1

50 Ω

V

OUT

S2

IN

GND

V

S

GND

CS00381

Doc ID 15647 Rev 1 13/23

Test circuit STG3220

Figure 8. Bandwidth

V

CC

S1

S2

IN

V

CC

Figure 9. Channel-to-channel crosstalk

GND

D

V

OUT

CS00371

14/23 Doc ID 15647 Rev 1

CS14091

STG3220 Test circuit

Figure 10. Test circuit

1. CL= 5/35 pF or equivalent (includes jig and probe capacitance)

=50Ω or equivalent

2. R

L

3. R

T=ZOUT

of pulse generator (typically 50 Ω)

Doc ID 15647 Rev 1 15/23

Test circuit STG3220

Figure 11. Break-before-make time delay

Figure 12. Switching time and charge injection

(V

= 0 V, R

GEN

= 0 Ω, RL = 1 MΩ, CL = 100 pF)

GEN

Figure 13. Turn ON, turn OFF delay time

16/23 Doc ID 15647 Rev 1

STG3220 Package mechanical data

7 Package mechanical data

In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK

®

packages, depending on their level of environmental compliance. ECOPACK®

®

is an ST trademark.

Figure 14. Package outline for QFN10 (1.8 x 1.4 x 0.5 mm) - 0.4 mm pitch

7936408 Rev.D

Doc ID 15647 Rev 1 17/23

Package mechanical data STG3220

Table 2. Mechanical data for QFN10 (1.8 x 1.4 x 0.5 mm) - 0.4 mm pitch

Symbol

Min Typ Max

A 0.45 0.50 0.55

A1 0 0.02 0.05

A3 0.127

b 0.15 0.20 0.25

D 1.75 1.80 1.85

E 1.35 1.40 1.45

e 0.40

L 0.35 0.40 0.45

Figure 15. Footprint recommendations for QFN10 (1.8 x 1.4 x 0.5 mm) - 0.4 mm pitch

Millimeters

18/23 Doc ID 15647 Rev 1

STG3220 Package mechanical data

Figure 16. Carrier tape for QFN10 (1.8 x 1.4 x 0.5 mm) - 0.4 mm pitch

Doc ID 15647 Rev 1 19/23

Package mechanical data STG3220

Figure 17. Reel information (front side) for QFN10 (1.8 x 1.4 x 0.5 mm) - 0.4 mm pitch

20/23 Doc ID 15647 Rev 1

STG3220 Package mechanical data

Figure 18. Reel information (back view) for QFN10 (1.8 x 1.4 x 0.5 mm) - 0.4 mm pitch

Doc ID 15647 Rev 1 21/23

Revision history STG3220

8 Revision history

Table 10. Document revision history

Date Revision Changes

14-May-2009 1 Initial release.

22/23 Doc ID 15647 Rev 1

STG3220

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Doc ID 15647 Rev 1 23/23