Page 1
70+70W STEREO POWER AMPLIFIER
■
MONOCHIP BRIDGE STEREO AMPLIFIER
FOR BASH
■
55+55W OUTPUT POWER @ RL = 4/8
THD = 0.5%
■
70+70W OUTPUT POWER @ RL = 4/8
THD = 10%
■
HIGH DYNAMIC PREAMPLIFIER INPUT
STAGES
■
EXTERNAL PROGRAMMABLE FEEDBACK
TYPE COMPRESSORS
■
AC COUPLED INPUT TO CLASS AB BRIDGE
OUTPUT AMPLIFIER
■
PRECISION RECTIFIERS TO DRIVE THE
DIGITAL CONVERTER
■
ON-OFF SEQUENCE/ TIMER WITH MUTE
AND STANDBY
■
PROPORTIONAL OVER POWER OUTPUT
CURRENT TO LIMIT THE DIGITAL
CONVERTER
■
ABSOLUTE POWER BRIDGE OUTPUT
®
ARCHITECTURE
Ω,
Ω,
STA550
FLEXIWATT27
TRANSISTOR POWER PROTECTION
■
ABSOLUTE OUTPUT CURRENT LIMIT
■
INTEGRATED THERMAL PROTECTION
■
POWER SUPPLY OVER VOLTAGE
PROTECTION
■
FLEXIWATT POW ER PAC KAG E WI TH 2 7 PIN
■
BASH® LICENCE REQUIRED
DESCRIPTION
The STA550 is a fully integrated power module designed to implement a BASH® amplifier when used
in conjunction with STABP01 digital processor.
BLOCK DIAGRAM
IN_PRE1
ATT_REL1
TRK_OUT
THRESH
ATT_REL2
IN_PRE2
COMPRESSOR
V/l
S1
Ict
Ict
S1
V/l
COMPRESSOR
-VSGND+VS
+
-
PEAK/2
DETECTOR
PEAK/2
DETECTOR
-
+
PWR_INP1TRK_1OUT_ PRE1
D01AU1263
CD+1
OUT1+
OUT1-
CD-1
CD+
PROT.
STBY/MUTE
CD+2
OUT2+
OUT2-
ABSOLUTE
VALUE
BLOCK
∆G
PROTECTION
PROTECTION
∆G
ABSOLUTE
VALUE
BLOCK
TRK_2OUT_ PRE2
PWR_INP2
+2
-1
OUTPUT BRIDGE
SOA
VOLTAGE
THERMAL
DETECTOR
TURN-
ON/OFF
SEQUENCE
+2
-1
OUTPUT BRIDGE CD-2
July 2003
1/16
Page 2
STA550
DESCRIPTION
(continued)
Notice that normally only one Digital Converter is needed to supply a stereo or multi-channel amplifier system,
therefore most of the functions implemented in the circuit have summing outputs
The signal circuits are bias ed by fixed negative and posi tive voltages r eferred to Ground. Instead the final stages of the output amplifiers are supplied by two external voltages that are following the audio signal . In this way
the headroom for the output transistors is kept at minimum level to obtain a high efficiency power amplifier.
The Compressor circuits, one for each channel, performs a particular transfer behavior to avoid the dynamic
restriction that an adaptive system like this requires. To have a high flexibility the attack / release time and the
threshold levels are exter nal ly progr ammable. The tracking s ignal for the ex ter nal digita l converter is generated
from the Absolute Value block that rectifies the audio signal present at the compressor output. The outputs of
these blocks are decoupled by a diode to permit an easy sum of this signal for the mult ichannel application. The
output power bridges have a dedicated input pin to perform an AC decoupling to cancel the compressor output
DC offset. The gain of the stage is equal to 4 (+12dB). A sophis ticated circuit performs the output transistor power detector that , with the digital converter, reduces the power supply voltage . Moreover, a maximum current
output limiting and the over temperature sensor have been added to protect the circuit itself. The external voltage applied to the STBY/MUTE pin forces the two amplifiers in the proper condition to guarantee a silent turnon and turn-off.
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Value Unit
+V
-V
Positive supply voltage referred to pin 13 (GND) 30 V
s
Negative supply voltage referred to pin 13 (GND) -24 V
s
V
CD+
V
CD+
V
CD-
V
CD-
V
Att_Rel1
V
Att_Rel2
V
Pwr_Imp1
V
Pwr_Imp2
V
Trk_1
V
Trk_2
V
In_pre1
V
In_pre2
V
threshold
Positive supply voltage tracking rail referred to pin 13 (GND) 22 V
Positive supply voltage operated to Vs+
Negative supply voltage referred to -Vs
Negative supply voltage tracking rail referred to pin 13 (GND) -22 V
Pin 3, 25 Negative & Positive maximum voltage referred to GND
(pin 13)
Pin 7, 21, 18, 10 Negative & Positive maximum voltage referred
to GND (pin 13)
Pin 8, 20 Negative & Positive maximum voltage referred to GND
(pin 13)
Pin 17 Negative & Positive maximum voltage referred to GND
(pin 13)
I
stb-max
V
stbymute
I
OUT
Note 1: V
Note 2: All pin s wi t h s tand ±2KV ESD but not pin 11
Pin 11 maximum input current (Internal voltage clamp at 5V) 500 µA
Pin 11 negative maximum voltage referred to GND (pin 13) -0.5 V
Output Current 7.0 A
must not be more negative than -Vs and V
CD-
(1)
(1)
must not be more positive than +V
CD+
0.3 V
-0.3 V
-0.5 to +20 V
-20 to +20 V
-0.5 to +0.5 V
-7 to +0.5 V
S
2/16
Page 3
Figure 1. Connection Diagram between STA550 and STAbp01
490
PROTECTION
+10V
10K
490
EMI BARRIER
OPTIONAL
2K
2200pF
2.67K
4.99K
6.82K
2K
1K
10V
CD+
100K
1K
499K
GATE
CURRENT_SENSE
680pF
BUFFER IN
BUFFER OUT
CLOCK
COMP
10pF
FA IN
STABP01
VREF
1V
250Hz
10
4
ERROR
3
V
FB
V+
2
5
19
20
1
AMP
+
COMP/3
DISCHARGE
(RESET)
TRANSISTOR
BUFFER
+
-
2R
+
-
R
1V
1V
CURRENT SENSE
COMPARATOR
+
R
+
-
1V
R17
18
REC_OUT
INTERNAL
CIRCUIT
+
-
FAST ATTACK
CONTROL
UVLO: 7V = on
5V = off
-
R
Q
Q
ON
16 17
ONE SHOT DUTY ACCEL
+
-
S
+
SQQ
R
PWM LATCH
ONE SHOT
--+
1V
1V
1V
SOFT SWITCH
SQR
CLKQD
RESET
SIGNAL
CLKDQ
RESET
STA550
POWER SUPPLY1
OUTPUT
GROUND1
SOFT SW RESET
DEAD TIME
POWER_VS2
OUTPUT
GROUND2
I
10V
ONE
SHOT
DELAY
SENSE
+10V
GATE
CD+
CD-
ISENSE
10V
14
13
1V
OPEN DRAIN
OUTPUT
12
11
1V
6
7
8
9
15
Q
Q
Q
1V
+
+
-
1V10V
+
+25V
95K
100pF
GND-AUDIO GND
-VS
+VS
2714
+
COMPRESSOR
S1
S1
COMPRESSOR
∆G
V/l
PEAK/2
DETECTOR
Ict
Ict
PEAK/2
DETECTOR
V/l
∆G
-
+
19 18 21
8
IN_PRE1
3
ATT_REL1
+25V
680pF
OTHER
STA575
TRK-OUT
15K
2.43K
1000pF
2.55K
TRK_OUT
THRESH
ATT_REL2
IN_PRE2
16
17
25
20
ABSOLUTE
VALUE
BLOCK
ABSOLUTE
VALUE
BLOCK
TRK_2OUT_ PRE2
PWR_INP1TRK_1OUT_ PRE1
VOLTAGE
PROTECTION
THERMAL
PROTECTION
PWR_INP2
+2
OUTPUT BRIDGE
DETECTOR
ON/OFF
SEQUENCE
+2
OUTPUT BRIDGE
SOA
TURN-
GND
137109
-1
-1
STA575
15
12
11
22
24
23
26
6
4
5
2
CD+1
OUT1+
OUT1-
CD-1
CD+
PROT.
OTHER
STA575
PROTECTION
STBY/MUTE
CD+2
OUT2+
OUT2-
CD-2
R
SENSE
PROTECTION
R
SENSE
EMI BARRIER
OPTIONAL
D02AU1391
3/16
Page 4
STA550
THERMAL DATA
Symbol Parameter Value Unit
T
Max Junction temperature 150 °C
j
R
th j_case
Thermal Resistance Junction to case .............................. ..max 1 °C/W
OPERATING RANGE
Symbol Parameter Value Unit
+V
-V
∆V
V
CD+
V
CD-
I
in_Max
V
trheshold
T
amb
I
sb_max
Positive supply voltage +20 to +30 V
s
Negative supply voltage -10 to -22 V
s
Delta positive supply voltage 5V ≤ (Vs+ - VCD+) ≤ 10V V
s+
Positive supply voltage tracking rail +3 to 17 V
Negative supply voltage tracking rail -17 to -3 V
Current at pin In_Pre1, In_Pre2, related to compressor behaviour -1 to +1 mA peak
Voltage at pin Threshold -5 to 0 V
Ambient Temperature Range 0 to 70 °C
Pin 11 maximum input current (Internal voltage clmp at 5V) 200 µA
PIN CONNECTION
4/16
OUT2+
ATT_REL2
D01AU1251
27
CD-2
-Vs
1
-V
S
CD-1
ATT-REL1
OUT1-
OUT1+
CD+1
PWR_INP1
IN_PRE1
OUT_PRE1
TRK_1
STBY/MUTE
S
+V
CD+
GND
PROTECTION
TRK_2
TRK_OUT
THRESHOLD
IN_PRE2
PWR_INP2
OUT_PRE2
CD+2
OUT2-
Page 5
PIN FUNCTION
N° Name Description
1 - Vs Negative Bias Supply
2 CD-1 Channel 1 Time varying tracking rail negative power supply
3 Att_Rel1 Attack release rate for channel 1
4 Out1+ Channel 1 speaker positive output
5 Out1- Channel 1 speaker negative output
6 CD+1 Channel 1 positive power supply
7 Pwr_Inp1 Input to channel 1 power stage
8 In_pre1 Pre-amp input for channel 1 (virtual ground)
9 Out_pre1 Output channel 1 pre-amp
10 Trk_1 Absolute value block input for channel 1
11 Stby/mute Standby/mute input voltage control
12 Protection Protection signal for STABP01 digital processor
13 Gnd Analog Ground
STA550
14 +Vs Positive Bias Supply
15 CD+ Time varying tracking rail positive power supply
16 Trk_out Reference output for STABP01 digital processor
17 Threshold Compressor threshold input
18 Trk_2 Absolute value block input for channel 2
19 Out_pre2 Output channel 2 pre-amp
20 In_pre2 Pre-amp input for channel 2 (virtual ground)
21 Pwr_Inp2 Input to channel 2 power stage
22 CD+2 Channel 2 positive power supply
23 Out2- Channel 2 speaker negative output
24 Out2+ Channel 2 speaker positive output
25 Att_Rel2 Attack release rate for channel 2
26 CD-2 Channel 2 Time varying tracking rail negative power supply
27 -Vs Negative Bias Supply
5/16
Page 6
STA550
ELECTRI CAL CH ARAC TER ISTC S
Ω
8
, external components at the nominal value f = 1KHz, Tamb = 25°C unless otherwise specified
(Test Condition: Vs+ = 26V, Vs- = -22V, V
= 17V, V
CD+
= -17V, RL =
CD-
Symbol Parameter Test Condition Min. Typ. Max. Unit
PREAMPLIFIER AND COMPRESSOR
V
out clamp
V
control
VC
Voffset Output Offset at Out_pre pin with: V
THD Distortion at Out_pre: V
Maximum Voltage at Out_pre pin 10 11 12 Vpeak
I
Audio input current 0.8 mA
in
Voltage at Attack_Release pin Attenuation = 0dB
Attenuation = 6dB
Attenuation = 26dB
Input voltage range for the
omp_
Th
compression
Input impedance of Threshold pin 100 KΩ
Z
th
= 0V; Attenuation = 0dB
CRT
V
= 0.5V; Attenuation = 6dB
CRT
V
= 9V;
Attenuation = 26dB
= 0V; Attenuation = 0dB
= 0.5V; Attenuation = 6dB
= 9V;
Attenuation = 26dB
= 0V; Attenuation = 0dB
= 0.5V; Attenuation = 6dB
= 9V;
Attenuation = 26dB
EN Noise at Out_pre pin : V
CRT
CRT
V
CRT
V
CRT
CRT
V
CRT
V
CRT
0.35
6
-5 -1 V
-10
-250
-450
0
0.5
9
0.01
10
50
60
(2)
0.65
12
10
250
450
5
5
V
V
V
mV
mV
mV
%
%
%
µV
µV
µV
Attack time current at pin
I
ct
Attack_release
1. This value is due to the thermal noise of the external resistors Rr and Ri.
TRACKING PARAMETERS
G
V
trk_out
I
trk_out
Z
Tracking reference voltage gain 13 14 15 V
trk
Tracking ref. output voltage 0 20 V
Current capability 5 6 7 mA
Input impedance (T
trk_in
)1MΩ
RK1/2
OUTPUT BRIDGE
G
G
∆G
P
Half Output bridge gain 5.5 6 6.5 dB
out
Output bridge differential gain 11 12 13 dB
ch
Output bridges gain mismatch -1 1 dB
ch
Continuous Output Power THD = 0.5%
out
THD = 10%
THD = 10%; RL= 4Ω; V
V
= -13V; VS+ = 20V; VS- = -20V
CD-
THD Total harmonic distortion of the
Po = 5W 0.01 %
output bridge
f = 20Hz to 20KHz; Po = 30W 0.1 %
CD+
= 13V;
1.5 mA
50
64
55
70
W
W
64 70 W
6/16
V
Output bridge D.C. offset 50 mV
Off
Page 7
STA550
ELECTRICAL CHARACTERISTCS
Symbol Parameter Test Condition Min. Typ. Max. Unit
EN
Noise at Output bridge pins f = 20Hz to 20KHz; Rg = 50Ω 12 µV
(continued)
Z
R
OLG
Input impedance 100 140 180 KΩ
br_in
Output power Rdson IO = 1A 200 400 mΩ
dson
Open Loop Voltage Gain 100 dB
GB Unity Gain Bandwidth 1.4 MHz
SR Slew Rate 7V/µs
PROTECTION
V
V
V
Stby voltage range 0 0.8 V
stby
Mute voltage range 1.6 3 V
mute
Play voltage range 4 5 V
play
First Over temperature threshold 130 °C
T
h1
T
Second Over temperature
h2
150 °C
threshold
Unbal.
Ground
Unbal.
Ground
UV
th
P
d_reg.
Upper Unbalancing ground
threshold
Lower Unbalancing ground
threshold
Referred to (CD
Referred to (CD+ - CD-)/2
+
- CD-)/2
Under voltage threshold |Vs+| + |Vs-| 20 V
Power dissipation threshold for
I
= 50µA; @ Vds = 10V 25 31 W
prot
5V
-5 V
system regulation
P
d_max
Switch off power dissipation
@ Vds = 10V 48 W
threshold
I
Protection current slope for Pd > Pd
prot
I
Limiting Current threshold 5.5 6 6.5 A
lct
reg
I+Vs Positive supply current Stby (Vstby/mute pin = 0V)
Mute (Vstby/mute pin = 2.5V)
Play (Vstby/mute pin = 5V no signal)
I-Vs Negative supply current Stby (Vstby/mute pin = 0V)
Mute (Vstby/mute pin = 2.5V)
Play (Vstby/mute pin = 5V no signal)
ICD+ Positive traking rail supply current Stby (Vstby/mute pin = 0V)
Mute (Vstby/mute pin = 2.5V)
Play (Vstby/mute pin = 5V no signal)
ICD- Negative traking rail supply current Stby (Vstby/mute pin = 0V)
Mute (Vstby/mute pin = 2.5V)
Play (Vstby/mute pin = 5V no signal)
400 µA/W
4
35
35
4
35
35
100
110
110
100
110
110
mA
mA
mA
mA
mA
mA
µA
mA
mA
µA
mA
mA
7/16
Page 8
STA550
FUNCTIONAL DESCRIPTION
The circuit contains all the blocks to build a stereo amplifier. Each si ngle channel is based on the Output Bridge
Power Amplifier, and its protection circuit. Moreover, the compression function and a signal rectifier are added
to complete the circuit.
The operation modes are driven by The Turn-on/off sequence block. In fact the IC can be set in three states by
the Stby/mute pin:
Standby ( V
In the Standby mode all the circuits involved in the signal path are in off condition, instead
in Mute mode the circuits are biased but the Speakers Outputs are forced to ground potential.
These voltages can be get by the external RC network connected to Stby/Mute pin.
The same block is used to force quickly the I.C. In standby mode or in mute mode when the I.C. dangerous
condition has been detected. The RC network in these cases is used to delay the Normal operation restore.
The protection of the I.C. are implemented by the Over Temperature, Unbalance Ground, Output Short circuit,
Under voltage, and output transistor Power sensing as shown in the following table:
Table 1. Protection Implementation
Fault Type Condition Protection strategy Action time Release time
Chip Over
temperature
Chip Over
temperature
Unbalancing
Ground
Short circuit Iout > 6A Standby Fast Slow, related to
Under Voltage |Vs+| + |Vs-|< 20V Standby Fast Slow, related to
Extra power
dissipation
at output transistor
Maximum power
dissipation
at output transistor
< 0.8V), Mute (1.6V < V
pin
Tj > 130 °C Mute Fast Slow Related to
Tj > 150 °C Standby Fast Slow, Related to
|Vgnd| > ((CD+) (CD-))/2 + 5V
Pd tr. >25W Reducing DIGITAL
Pd tr. > 48W Standby Fast Slow, related to
< 3V), and Play (V
pin
Standby Fast Slow, Related to
CONVERTER output
voltage.
> 4V).
pin
Related to the
DIGITAL
CONVERTER
Turn_on sequence
Turn_on sequence
Turn_on sequence
Turn_on sequence
Turn_on sequence
Related to the
DIGITAL
CONVERTER
Turn_on sequence
See the POWER PROTECTION paragraph for the details
Compression
An other important function implemented, to avoid high power dissipation and clipping distortion, is the Compression of the signal input. In fact the preamplifier stage performs a voltag e gain equal to 5, fixed by Ri and Rr
external resistor, but in case of high input signal or low power supply voltage, its gain could be reduced of 26dB.
This function is obtained with a feedback type compressor that , in practice, reduces the impedance of the external feedback network. The behavior of c ompression it's i nternally fixed but depends fr om the Audio input voltage signal level, and from the Threshold voltage applied to the Threshold pin. The attack and release time are
programmable by the external RC network connected to the Att_Rel pins.
The constraints of the circuit in the typical application are the following:
Vthreshold range = -5 to 0
Vin peak max = 8V
Vout peak max = 10V
8/16
Page 9
STA550
-
Gain without compression (G) = 5
Max Attenuation ratio = 26 dB
The following graph gives the representation of the Compressor activation status related to the Vthreshold and
the input voltage. The delimitation line between the two fields, compression or not, is expressed by the formula :
⋅
2Vthreshold
=
------------------------------------------
V
in
Where G is the preamplifier gain without compression.
In the compression region the gain of the preamplifier will be reduced
(G = 2·Vthreshold/Vin) to maintain at steady state the output voltage equal 2*|Vthreshold| .
Instead in the other region the compressor will be off (G = 5).
The delimitation line between the two fields can be related to the output voltage of the preamplifier: in this case
the formula is :
V
2Vthreshold
out
Figure 2. Compressor activation field
PEAK
V
IN
G
⋅=
8
6
COMPRESSION
4
G < 5
2
G = 5
D01AU1264
2345
1
|Vthreshold|
The relative attenuation introduced by the variable gain cell is the following :
Attenuatio n 20
log
2
-- -
5
--------------------- -
⋅=
V
in_peak
th
V
The total gain of the stage will be:
Gdb = 20log5 + Attenuation
The maximum input swing is related to the value of input resistor, to guarantee that the input current remain
under Iin_Max value (1 mA).
V
in_peak
--------------------- ->
R
i
I
in_max
9/16
Page 10
STA550
Figure 3. Compressor attenuation vs. input amplitude
Attenuation(dB)
0
-6
-12
|Vth=5|
|Vth=2.5|
-18
|Vth=1|
-24
D01AU1265
2345
1
678
|Vinpk|
ABSOLUTE VALUE BLOCK
The absolute value block rec tifies the signal after the c ompressio n to extract the c ontrol voltage for the ex ternal
digital converter. The output voltage swing is internally limited, the gain is internally fixed to 14.
The input impedance of the rectifier is very high , to allow the appropriate filtering of the audio signal before the
rectification (between Out_pre and Trk pins).
OUTPUT BRIDGE
The Output bridge amplifier makes the single-ended to Differential conversion of the Audio signal using two
power amplifiers, one i n non-inver ting configuration with gain equal to 2 and the other in inv er ting confi guration
with unity gain. To guarantee the high input impedance at the input pins, Pwr_Inp1 and Pwr_Inp2, the second
amplifier stages are driven by the output of the first stages respectively.
POWER PROTECTION
To protect the output transistors of the power bridge a power detector is implemented (fig 3).
The current flowing in the power bridge and trough the series resistor Rsense is measured reading the voltage
drop between CD+1 and CD+. In the same time the voltage drop on the relevant power (Vds) is internally measured. These two voltages are converted in current and multiplied: the resulting current , Ipd, is proportional to
the instantaneous dissipated power on the relevant output transistor. The current Ipd is compared with the reference current Ipda, if bigger (dissipated power > 25W) a current, Iprot, is supplied to the Protection pin. The
aim of the current Iprot is to reduce the reference voltage for the digital converter supplying the power stage of
the chip, and than to reduce the dissipated power. The respons e time of the system must be les s than 200
µ
Sec
to have an effective protection. As further protection, when Ipd reaches an higher threshold (when the dissipated
value is higher then 48W) the chip is shut down, forcing low the Stby/Mute pin, and the turn on sequence is
restarted.
10/16
Page 11
Figure 4. Power Protection Block Diagram
R
SENSE
CD+1
CD+
ILOAD
V/I
OC1
ILIM CURRENT COMP
STA550
TO TURN-ON/OFF
SEQUENCE
OPA
MULTIPLIER
V/I
CD-
I_PD
OUT1-OUT1+
X
OPA
IPD
IPDP
IPD
IPDA
PDP1
CURRENT COMP
IPROT
D01AU1266
TO TURN-ON/OFF
SEQUENCE
TO PROT PAD
In fig. 4 there is the power protection strategy pictur es. Under the curve of the 25W power, the chip is in nor mal
operation, over 48W the chip is forced in Standby. This las t status would be reached if the digital converter does
not respond quikly enough reducing the stress to less than 48W.
The fig.5 gives the protection current, Iprot, behavior. The current sourced by the pin Prot follows the formula:
–
⋅⋅
4
for P
< P
d
d_av_th
the I
prot
= 0
PdP
d_av_th
----------------------------------------------------------------- -
I
≡
prot
)–( 510
1.25V
Independently of the output voltage, the chip is also shut down in the folowing conditions:
When the currentthrough the sensing resistor, R
, reaches 6A (Voltage drop (CD+) - (CD+1) = 700mV).
sense
When the average junction temperature of the chip reaches 150°C.
When the ground potential differ from more than 5V from the half of the power supply voltage, ((CD+)-(CD-))/2
|
| +
Vs+
When the sum of the supply voltage
|Vs-| <20V
The output bridge is muted when the average junction temperature reaches 130°C.
11/16
Page 12
STA550
(V)
)
y
Figure 5. Power protection threshold Figure 6. Protection current behaviour
Ids (mA
Ilim = 6A
6
Standb
BucK
4
Pd_Max = 48W
Limitation
2
Normal
Pd_reg = 25W
Operation
10 20 30 40
Figure 7. Test and Application Circuit
INPUT1
R1
IN_PRE1
R5
ATT_REL1
C3
Vds
C17
R3 R9
OUT_PRE1
C5
C7
9107
8
3
Iprot(mA)
20
Iprot slope=0.4mA/W
10
D01AU1306
R7 R11
TRK_1 PWR_INP1
10
20 30 40 50 60
C1
OUT1+
4
5V
5
OUT1-
Pd(W)
R13
TRK-OUT
12/16
CD+
+V
-V
CD-
R16
C12
S
C13
S
D1
PROT
R20
R24
C14
R22
R19
R17
C10
C15
THRESH
R18
CD+1
CD+
CD+2
+V
GND
C11
-V
-V
CD-1
CD-2
TRK-OUT
PROT
THRESH
6
15
22
S
14
13
27
S
1
S
2
26
16
12
17
C2
R8R12
191821
C8
C6
STBY/
MUTE
11
OUT2+
24
23
OUT2-
25
ATT_REL2
IN_PRE2
20
OUT_PRE2TRK_2PWR_INP2
R4R10
C16
R14
C9
C4
R6
R2
D01AU1267
MUTE STBY
R15
INPUT2
Page 13
EXTER NA L COM P ON EN T S
Cct attack
Ict
Vcontrol
------------------------ -=
Name Function Value Formula
STA550
Ri
R1 = R2
Rr
R3 = R4
Cac
C1 = C2
Cct
C3 = C4
R5 = R6 Release constant time Resistor 470KΩ
R7 = R8 Resistor for tracking input voltage
R9 = R10 Resistor for tracking input voltage
R11 = R12 Resistor for tracking input voltage
C5 = C6 Capacitor for Tracking input
C7 = C8 Dc decoupling capacitor 1µF
Input resistor 10KΩ
(|G| = 5, Rr = 50KΩ)
Feedback resistor 50KΩ
(|G| = 5, Ri = 10KΩ
AC Decoupling capacitor 100nF
(fp = 16Hz,
Rac =100KΩ )
Capacitor for the attack time 2.2µF
(Tattack = 13mSec,
Vcontrol = 9V,
Ict = 1.5mA)
(t = 1 Sec. ,
Cct = 2.2 µF )
10KΩ
filter
56KΩ
filter
10KΩ
filter
1nF
voltage filter
Cac
R
i
Rr G Rr⋅=
-------------------------------- -=
2π fp Rac⋅⋅
Rct
Rr
-------=
G
---------=
Cct
1
τ
R13 Bias Resistor for Stby/Mute
function
R14 Stby/Mute constant time resistor 30KΩ
R15 Mute resistor 30KΩ
C9 Capacitor for Stby/Mute resistor 2.2µF
R16 = R17 Sensing resistor for SOA detector 120mΩ
R18 Conversion resistor for threshold
voltage
C10 = C11 Power supply filter capacitor 100nF
R22 = R24 Centering resistor 400 Ω , 1W
C12 = C13 Tracking rail power supply filter 680nF
R19 Protection 1KΩ
R20 TRK_out 40KΩ
C14 = C15 Power supply filter capacitor 470 µF , 63V
C16 = C17 Feedback capacitor 100pF
D1 Schottky diode SB360
Note: Vco ntrol is the voltage at Att_Rel pin.
10KΩ
5% 4W
100KΩ
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Page 14
STA550
APPLICATION HINTS
PREAMPLIFIER AND COM PRESSOR
In the application circuit showed in figure 7, R
If the input signal is very low, is possible to increase the gain fixing the product Vin
In that case is possible to increase G decreasing R
cuitbehavior and remaining in the operating range I
So it is possible to increase the preamplifier gain until 25.
If no compression is present (equivalnt compressor Gm=0), the effects are:
– T he outp ut voltage offset increase
– T he SNR decrease
The following table shows these variations:
(or R2/R4) ratio fix the gain of the preamplifier.
1/R3
from 10KΩ until 2KΩ without relevant effetcs on the cir-
1,2
in_max
= V
in_max/R1(2)
,<1mA.
∗
G = cost.
R
1,2
10KΩ 8V 5 15mV 10µV
5KΩ 4V 10 30mV 13µV
2KΩ 1.6V 25 75mV 20µV
R
= 50KΩ and all the other external components are the same
3(4)
V
IN MAX
G
V
OFFSET
EN
Attenuation = 0 dB
If the compression is active the circuit behaviour is the same.
It”s also possible to eliminate the compressor. In this case the ATT_REL (1,2) pin must be connected to gnd.
STBY-MUT E CIRCUIT
In the suggested application circ uit (figure 7), the resistor for Standby/Mute function (R
) is connected between
13
the Standby/Mute switches and 5V Supply.
It is possible to connect the resistor to another Supply Voltage level V
(R
) must be changed according to the following formula (fixing V
13,14
R
R
13
14
4VL10–⋅()KΩ=
4VL10+⋅()KΩ=
, but in that case also the resistor value
L
STBY/MUTE
= 2.5V and R15 = 10KΩ):
HEADROOM
Ω
(R
In the suggested application circuit the supply voltage to obtain 75W (Power Output) on 8
load
)
is:
V
supply
∆VI
,
LMAX
⋅+=
R
DSon
It is also possible to increase the system’s efficiency forcing the headroom to follow the output signal (variable
drop insteadof a constant drop).
In that case:
V()R
L
⋅+=
DSon
14/16
V
supply
∆VI
Page 15
STA550
DIM.
MIN. TYP. MAX. MIN. TYP. MA X.
mm inch
A 4.45 4.50 4.65 0.175 0.177 0.183
B 1.80 1.90 2.00 0.070 0.074 0.079
C 1.40 0.055
D 0.75 0.90 1.05 0.029 0.035 0.041
E 0.37 0.39 0.42 0.014 0.015 0.016
F (1) 0.57 0.022
G 0.80 1.00 1.20 0.031 0.040 0.047
G1 25.75 26.00 26.25 1.014 1.023 1.033
H (2) 28.90 29.23 29.30 1.139 1.150 1.153
H1 17.00 0.669
H2 12.80 0.503
H3 0.80 0.031
L (2) 22.07 22.47 22.87 0.869 0.884 0.904
L1 18.57 18.97 19.37 0.731 0.747 0.762
L2 (2) 15.50 15.70 15.90 0.610 0.618 0.626
L3 7.70 7.85 7.95 0.303 0.309 0.313
L4 5 0.197
L5 3.5 0.138
M 3.70 4.00 4.30 0.145 0.157 0.169
M1 3.60 4.00 4.40 0.142 0.157 0.173
N 2.20 0.086
O 2 0.079
R 1.70 0.067
R1 0.5 0.02
R2 0.3 0.12
R3 1.25 0.049
R4 0.50 0.019
V 5˚ (Typ.)
V1 3˚ (Typ.)
V2 20˚ (Typ.)
V3 45˚ (Typ.)
(1): dam-bar protusio n not included
(2): molding protusion i ncluded
OUTLINE AND
MECH AN ICAL DATA
Flexiwatt27 (vertical)
L2
V
C
B
H
V3
H3
OL3 L4
Pin 1
G
H1
G1
H2
R3
R4
N
V2
F
V
A
V1
R2
R
L
L1
V1
R2
FLEX27ME
L5
R1
R1 R1
M
D
E
M1
7139011
15/16
Page 16
STA550
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of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implic ation or oth erwise under any patent or pat ent rights of STMicroelectronic s. Specifications mentioned in this publication are subject
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