Datasheet STA533WF Datasheet (ST)

18-volt, 3-amp, quad power half-bridge

Features

■ Multipower BCD technology

■ Low input/output pulse width distortion

■ 200-mΩ R

stage

■ CMOS-compatible logic inputs

■ Thermal protection

■ Thermal warning output

■ Undervoltage protection

■ Short-circuit protection

Description

The STA533WF is a monolithic quad half-bridge
stage in multipower BCD technology. The device
can be used as a dual bridge or reconfigured, by
connecting pin CONFIG to pins VDD, as a single
bridge with double-current capability.

The device is designed for the output stage of a
stereo Full Flexible Amplifier (FFX™). It is
capable of delivering 10 W x 4 channels into 4-Ω

Table 1. Device summary

complementary DMOS output

dsON

STA533WF

PowerSSO36 package
with exposed pad down

loads with 10% THD at V
single-ended configuration.

It can also deliver 20 W + 20 W into 8-Ω loads
with 10% THD at V

= 18 V in BTL configuration

CC

or, in single parallel BTL configuration, 40 W into
a 4-Ω load with 10% THD at V

The input pins have a threshold proportional to
the voltage on pin VL.

The STA533WF comes in a 36-pin PowerSSO
package with exposed pad down (EPD).

=18V in

CC

= 18 V.

CC

Order code Temperature range Package Packaging

STA533WF 0 to 70 °C PowerSSO36 EPD Tube

STA533WF13TR 0 to 70 °C PowerSSO36 EPD Tape and reel

June 2011 Doc ID 17658 Rev 2 1/15

www.st.com

15

Pin description STA533WF

1 Pin description

Figure 1. Pin out

Table 2. Pin list

GNDSUB

OUT2B
OUT2B

VCC2B
GND2B
GND2A

VCC2A

OUT2A

OUT2A

OUT1B

OUT1B

VCC1B
GND1B
GND1A

VCC1A

OUT1A

OUT1A

N.C.

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18

STA533WF

36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19

Pin Name Type Description

1 GNDSUB PWR Substrate ground

2, 3 OUT2B O Output half-bridge 2B

4 VCC2B PWR Positive supply

VCCSIG
VCCSIG
VSS
VSS
IN2B
IN2A
IN1B
IN1A
THWARN
FAU LT
TRISTATE
PWRDN
CONFIG
VL
VDD
VDD
GNDREG
GNDCLEAN

5 GND2B PWR Negative supply

6 GND2A PWR Negative supply

7 VCC2A PWR Positive supply

8, 9 OUT2A O Output half-bridge 2A

10, 11 OUT1B O Output half-bridge 1B

12 VCC1B PWR Positive supply

13 GND1B PWR Negative supply

14 GND1A PWR Negative supply

15 VCC1A PWR Positive supply

16, 17 OUT1A O Output half-bridge 1A

18 N.C. - No internal connection

19 GNDCLEAN PWR Logical ground

20 GNDREG PWR Filtering for regulator; this is an internally generated ground for V

21, 22 VDD PWR 5-V regulator referred to ground

23 VL PWR High logical state setting voltage, V

2/15 Doc ID 17658 Rev 2

DD

L

STA533WF Pin description

Table 2. Pin list (continued)

Pin Name Type Description

Configuration pin:

24 CONFIG I

25 PWRDN I

26 TRISTATE I

27 FAULT O

28 THWARN O

29 IN1A I Input of half-bridge 1A

30 IN1B I Input of half-bridge 1B

0: normal operation
1: bridges in parallel, see Parallel-output and high-current operation

on page 8

Stand-by pin:
0: low-power mode

1: normal operation

Hi-Z pin:
0: all power amplifier outputs in high-impedance state

1: normal operation

Fault pin advisor (open-drain device, needs pull-up resistor):
0: fault detected (short circuit or thermal, for example)

1: normal operation

Thermal-warning advisor (open-drain device, needs pull-up
resistor):

o

0: temperature of the IC >130

C

1: normal operation

31 IN2A I Input of half-bridge 2A

32 IN2B I Input of half-bridge 2B

33, 34 VSS PWR 5-V regulator referred to +V

CC

35, 36 VCCSIG PWR Filtering for regulator, this is an internally generated supply for V

SS

Doc ID 17658 Rev 2 3/15

Electrical characteristics STA533WF

2 Electrical characteristics

Table 3. Absolute maximum ratings

Symbol Parameter Value Unit

V

CC

V

Lmax

V

inputs

V

config

T

stg

Table 4. Recommended operating conditions

DC supply voltage (Pins 4, 7, 12, 15) 23 V

Voltage on pin 23 4.0 V

Voltage on pins 25, 26, 29 to 32 -0.3 to VL + 0.3 V

Voltage on pins 24 -0.3 to VDD + 0.3 V

, TjStorage and junction temperature -40 to 150 °C

Symbol Parameter Min Typ Max Unit

V

CC

V

L

T

amb

Table 5. Thermal data

DC supply voltage (Pins 4, 7, 12, 15) 5.0 - 18 V

Input logic reference 2.7 3.3 3.6 V

Ambient temperature 0 - 70 °C

Symbol Parameter Min Typ Max Unit

T

j-case

T

jSD

T

warn

t

hSD

Thermal resistance junction to case (thermal pad) - - 1.5 °C/W

Thermal shut-down junction temperature - 150 - °C

Thermal warning temperature - 130 - °C

Thermal shut-down hysteresis - 25 - °C

Unless otherwise stated, the test conditions for Ta bl e 6 below are VL = 3.3 V, VCC = 18 V,
R

=8Ω, fSW = 384 kHz and T

L

Table 6. Electrical characteristics

Symbol Parameter Test conditions Min Typ Max Unit

P

R

I

dss

g

N

g

P

OUT

dsON

Output power in BTL mode THD+N > 10% - 20 - W

Power P-channel/N-channel
MOSFET on resistance

Power P-channel/N-channel
leakage

Power P-channel R
matching

Power N-channel R
matching

Dt_s Low current dead time (static) see Figure 2 - 5 10 ns

4/15 Doc ID 17658 Rev 2

amb

dsON

dsON

= 25 °C.

= 1 A - 180 230 mΩ

I

dd

- --10μA

I

= 1 A 95--%

dd

= 1 A 95--%

I

dd

STA533WF Electrical characteristics

Table 6. Electrical characteristics (continued)

Symbol Parameter Test conditions Min Typ Max Unit

Dt_d

t

d_ON

t

d OFF

t

r

t

f

V

IN-Low

V

IN-High

I

IN-H

I

IN-L

I

PWRDN-H

V

Low

V

High

High current dead time
(dynamic)

L = 22 μH, C = 470 nF

= 8 Ω, Idd = 2.0 A

R

L

see Figure 3

- 1020ns

Turn-on delay time Resistive load - 40 60 ns

Turn-off delay time Resistive load - 40 60 ns

Rise time

Fall time

Half-bridge input, low-level
voltage

Half-bridge input, high-level
voltage

High-level input current VIN = V

Resistive load
see Figure 2

Resistive load
see Figure 2

-

-

L

- 8 10 ns

- 8 10 ns

/ 2 -

V

-

VL / 2 +
300 mV

-

-

L

300 mV

-

V

V

-1-μA

Low-level input current VIN = 0.3 V - 1 - μA

High level PWRDN pin input
current

Low logical state voltage
(pins PWRDN, TRISTATE)

High logical state voltage
(pins PWRDN, TRISTATE)

= 3.3 V - 35 - μA

V

L

= 3.3V --0.8V

V

L

V

= 3.3 V 1.7 - - V

L

I

VCC-

PWRDN

I

FAULT

I

VCC-HiZ

I

VCC

I

OCP

V

UVP

t

pw_min

Supply current from VCC in
power down mode

V

= 0 V --10µA

PWRDN

Output current on pins
FAULT, THWARN with fault

= 3.3V -1-mA

V

pin

condition

Supply current from VCC in
3-state

V

TRISTATE

= 0 V - 22 - mA

Input pulse width

Supply current from VCC in
operation (both channels
switching)

= 50% duty,
switching frequency

= 384 kHz,

-50-mA

no LC filters

Overcurrent protection
threshold (short-circuit current

-3.04.0-A

limit)

Undervoltage protection
threshold

--3.54.3V

Output minimum pulse width No load 70 - 150 ns

Doc ID 17658 Rev 2 5/15

Electrical characteristics STA533WF

Table 7. Logic truth table

Pin

PWRDN

Pin

TRISTATE

Inputs as per Figure 3 Transistors as per Figure 3

Output mode

INxA INxB Q1 Q2 Q3 Q4

0 0 x x Off Off Off Off Hi Z

1 1 0 0 Off Off On On Dump

1 1 0 1 Off On On Off Negative

1 1 1 0 On Off Off On Positive

1 1 1 1 On On Off Off Not used

Test circuits

Figure 2. Test circuit

Low current dead time = MAX(DTr,DTf)

Duty cycle = 50%

INxY

gnd

+Vcc

OUTxY

OUTxY

R 8Ω

DTfDTr

+

-

Vcc

(3/4)Vcc

(1/2)Vcc

(1/4)Vcc

t

vdc = Vcc/2

D03AU1458

Figure 3. Current dead time test circuit

High Current Dead time for Bridge application = ABS(DTout(A)-DTin(A))+ABS(DTOUT(B)-DTin(B))

+V

CC

Duty cycle=A Duty cycle=B

DTin(A)

INxA

Duty cycle A and B: Fixed to have DC output current of Iout in the direction shown in figure

6/15 Doc ID 17658 Rev 2

Q1

OUTxA

Q3

DTout(A)

Rload=8Ω

Iout

470nF

DTout(B) DTin(B)

22μ22μ

470nF470nF

Q2

OUTxB

Iout

Q4

INxB

D00AU1162_00

STA533WF Applications information

3 Applications information

The STA533WF is a dual-channel H-bridge audio power amplifier that can deliver 20 W per
channel into 8 Ω with 10% THD at V

The STA533WF converts both FFX and binary-logic-controlled PWM signals into audio
power at the load. It includes a logic interface, integrated bridge drivers, high-efficiency
MOSFET outputs and thermal and short-circuit protection circuitry.

In FFX mode, two logic-level signals per channel are used to control the high-speed
MOSFET switches which drive the speaker load in a bridge configuration, according to the
damped ternary modulation operation.

In binary mode, both full-bridge and half-bridge modes are supported.

The STA533WF includes overcurrent and thermal protection as well as an undervoltage
lockout with automatic recovery. A thermal warning status is also provided.

Figure 4. Block diagram for FFX or binary modes

= 18 V with high efficiency.

CC

INL[1,2]

INR[1,2]

VL

PWRDN

TRISTATE

FAU LT

THWARN

Logic
interface
and
decode

Protection
circuit

Regulators

Left
H-bridge

Right
H-bridge

Figure 5. Block diagram for binary half-bridge mode

INL[1,2]

INR[1,2]

VL

PWRDN

TRISTATE

FAU LT

THWARN

Logic
interface
and
decode

Protection
circuit

Regulators

Left A
bridge

Left B
bridge

Right A
bridge

Right B
bridge

OUTPL

OUTNL

OUTPR

OUTNR

OUTPL

OUTNL

OUTPR

OUTNR

Logic interface and decode

The STA533WF power outputs are controlled using one or two logic-level timing signals. In
order to provide a proper logic interface, pin VL must have the same voltage as the PWM
input signal.

Doc ID 17658 Rev 2 7/15

Applications information STA533WF

Protection circuits

The STA533WF includes protection circuitry for overcurrent and thermal overload
conditions. A thermal warning pin (THWARN) is activated low (open-drain MOSFET) when
the IC temperature exceeds 130 °C, which is in advance of the thermal shutdown protection.
When a fault condition is detected an internal fault signal acts to immediately disable the
output power MOSFETs, placing both H-bridges in the high-impedance state. At the same
time an open-drain MOSFET connected to pin FAULT is switched on.

There are two possible modes subsequent to activating a fault:

● Shutdown mode:

with pins FAULT (with pull-up resistor) and TRISTATE independent, an activated fault
disables the device, signalling low at pin FAULT.
The device may subsequently be reset to normal operation by toggling pin TRISTATE
from high to low and back to high using an external logic signal.

● Automatic recovery mode:

This is shown in the applications circuit in Figure 6 and Figure 7 on page 10.
Pins FAULT and TRISTATE are shorted together and connected to a time constant
circuit comprising R59 and C58.
An activated fault forces a reset on pin TRISTATE causing normal operation to resume
following a delay determined by the time constant of the circuit.
If the fault condition is still present this operation continues to repeat until the fault
condition is removed.
An increase in the time constant of the circuit produces a longer recovery interval.

Care must be taken in the overall system design so as not to exceed the protection
thresholds under normal operation.

Power outputs

The STA533WF power and output pins are duplicated to provide a low-impedance path for
the device bridged outputs. All duplicated power, ground and output pins must be connected
for reliable operation.

Pins PWRDN or TRISTATE should be used to set all MOSFETS to the high-impedance
state during power-up and until the logic power supply on pin VL has settled.

Parallel-output and high-current operation

When using FFX mode, the STA533WF outputs can be connected in parallel to increase the
output current capability. In this configuration the device can provide 40 W into 4 Ω.

This mode of operation is enabled with pin CONFIG connected to V
combined to give INLA = INLB and INRA = INRB, then the corresponding outputs can be
shorted together to give OUTLA = OUTLB and OUTRA = OUTRB.

The snubber RC network shown in the applications figures must be placed as close as
possible to the output pins. This reduces ringing, over- and undervoltage effects, and
improves the audio quality and EMI performance.

. The inputs must be

DD

8/15 Doc ID 17658 Rev 2

STA533WF Applications information

Supply decoupling capacitors

To meet the performance figures given in this datasheet the STA533WF power supply must
be adequately filtered.

For this purpose capacitors connected from pins VCC1 to GND1 and from VCC2 to GND2
must be placed as close as possible to the related IC pins.

For reliability and optimum performance the following capacitors are suggested:

● 100-nF ceramic capacitor with lead length less than 2 mm, connected to the ground

plane and as close as possible to the GND pin

● 1-uF X7R (low ESR) capacitors.

Pin GNDREG is used to filter the internal reference voltage V

; This pin must not be

DD

connected to other ground pins, it is an internally generated supply.

Pin VCCSIG is used to filter the internal reference voltage V

; This pin must not be

SS

connected to other supply pins, it is an internally generated supply.

Output filter

A passive 2nd-order filter is used on the STA533WF power outputs to reconstruct an analog
audio signal. The system performance can be significantly affected by the output filter
design and choice of passive components.

Filter designs for 4-Ω and 8-Ω loads are shown in the applications circuits below.

Applications circuits

Figure 6 shows a typical full-bridge circuit for supplying 20 W + 20 W into 8-Ω speakers with

10% THD when V

Figure 7 shows a single-BTL configuration capable of supplying 40 W into a 4-Ω load at

10% THD when V
STA309A + STA533WF demo board.

For both applications circuits a PWM modulator is required as driver.

= 18 V.

CC

= 19 V. This result was obtained with peak power for <1 s using the

CC

Doc ID 17658 Rev 2 9/15

10/15 Doc ID 17658 Rev 2

Figure 6. Applications circuit for stereo full-bridge configuration

Applications information STA533WF

U2

C29
100nF

TH W

EAPD

3V3

3V3

R8
10K

R10 10k

C30

100nF

C22

100nF

RIGHT_B
RIGHT_A
LEFT_B
LEFT_A

C31

100nF

36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19

VCCSIG
VCCSIG
VSS
VSS
IN2B
IN2A
IN1B
IN1A
THWARN
FAULT
TRISTATE
PWRDN
CONFIG
VL
VDD
VDD
GNDREG
GNDCLEAN

STA533WF

GNDSUB

OUT2B
OUT2B

VCC2B
GND2B
GND2A

VCC2A

OUT2A

OUT2A

OUT1B

OUT1B
VCC1B

GND1B
GND1A

VCC1A

OUT1A

OUT1A

NC

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18

Figure 7. Applications circuit for single-BTL configuration

U1

TH W

C12
100nF

EAPD

R1
10K

3V3

C13

100nF

3V3

C2

100nF

INPUT_A

INPUT_B

R5 10 k

C14

100nF

C18

100nF

36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19

VCCSIG
VCCSIG
VSS
VSS
IN2B
IN2A
IN1B
IN1A
THWARN
FAULT
TRISTATE
PWRDN
CONFIG
VL
VDD
VDD
GNDREG
GNDCLEAN

STA533WF

GNDSUB

OUT2B
OUT2B

VCC2B
GND2B
GND2A
VCC2A

OUT2A

OUT2A

OUT1B

OUT1B
VCC1B
GND1B
GND1A
VCC1A

OUT1A

OUT1A

NC

C23 10 0nF

C25 1uF 25V

C32 100nF

C33

Vcc

C36

1000uF/25V

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18

1000uF/ 25V

1uF 25V

+

C1 10 0nF

C6 1uF 25V

C15 100nF

C17

Vcc

+

C19

L3 22uH

R6

22

C26
330pF

L4 22uH

L5 22uH

R11

22

C45
330pF

L6 22uH

1uF 25V

C20 100n F

C28

C43 100n F

C42 100n F

L1 10uH

C3
680pF

R3
10

L2 10uH

R7

6.2

R9

6.2

100nF

R12

6.2

R13

6.2

C4 220n F

220nF

C10

220nF

C11 220nF

C38

C8

1uF

C16

1nF

C5

1nF

1nF

C37

1nF

C39

1nF

1nF

C9

1nF

C41

C35

1nF

C40

1nF

J2

1
2

J3

1
2

J1

1
2

RIGHT 8OHM

LEFT 8OHM

OUT 4OHM

C21

100nF

C24

470nF

C27

100nF

C47

100nF

C44

470nF

C46

100nF

C7

R2

3R3

R4

3R3

STA533WF Heatsink requirements

4 Heatsink requirements

Using the STA533WF mounted on a double-layer PCB having 2 copper ground areas of
3x3cm

2

and with 16 via holes the junction to ambient thermal resistance is approximately

24 °C/W in natural air convection.

Figure 8. Double-layer PCB with copper ground areas and 16 via holes

With the dissipated power within the device depending primarily on the supply voltage, the
load impedance and the output modulation level, the maximum estimated dissipated power,
Pdmax, for the STA533WF is:

4 W for 2 x 20 W into 8 Ω at 18 V

< 5 W for 2 x 10 W into 8 Ω + 1 x 20 W into 4 Ω at 18 V.

The figure below shows the power derating curve for the PowerSSO36 EPD package on
PCBs with copper areas of 2 x 2 cm

2

and 3 x 3 cm2.

Figure 9. Power derating curves for PCB used as heatsink

Pd (W)

8

7

6

5

4

Copper Area 3x3 cm
and via holes

TDA7491P

STA533WF

PSSO36

PowerSSO36

3

2

Copper Area 2x2 cm
and via holes

1

0

0 20 40 60 80 100 120 140 160

Tamb ( °C)

Doc ID 17658 Rev 2 11/15

Package mechanical data STA533WF

5 Package mechanical data

The STA533WF comes in a 36-pin PowerSSO package with exposed pad down (EPD).

Figure 10 below shows the package outline and Ta bl e 8 gives the dimensions.

In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK

Table 8. PowerSSO36 EPD dimensions

Symbol

A 2.15 - 2.47 0.085 - 0.097

A2 2.15 - 2.40 0.085 - 0.094

a1 0.00 - 0.10 0.000 - 0.004

b 0.18 - 0.36 0.007 - 0.014

c 0.23 - 0.32 0.009 - 0.013

D 10.10 - 10.50 0.398 - 0.413

E 7.40 - 7.60 0.291 - 0.299

e - 0.5 - - 0.020 -

e3 - 8.5 - - 0.335 -

F - 2.3 - - 0.091 -

G- - 0.10 - - 0.004

H 10.10 - 10.50 0.398 - 0.413

h- - 0.40 - - 0.016

®

packages, depending on their level of environmental compliance. ECOPACK®

®

is an ST trademark.

Dimensions in mm Dimensions in inches

Min Typ Max Min Typ Max

k 0 - 8 degrees 0 - 8 degrees

L 0.60 - 1.00 0.024 - 0.039

M - 4.30 - - 0.169 -

N - - 10 degrees - - 10 degrees

O - 1.20 - - 0.047 -

Q - 0.80 - - 0.031 -

S - 2.90 - - 0.114 -

T - 3.65 - - 0.144 -

U - 1.00 - - 0.039 -

X 4.10 - 4.70 0.161 - 0.185

Y 6.50 - 7.10 0.256 - 0.280

12/15 Doc ID 17658 Rev 2

Doc ID 17658 Rev 2 13/15

Figure 10. PowerSSO36 EPD outline drawing

STA533WF Package mechanical data

h x 45°

Revision history STA533WF

6 Revision history

Table 9. Document revision history

Date Revision Changes

02-Jul-2010 1 Initial release.

22-Jun-2011 2 Updated Applications circuits on page 9

14/15 Doc ID 17658 Rev 2

STA533WF

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Doc ID 17658 Rev 2 15/15