Datasheet STA516B Datasheet (ST)

Features

! Low input/output pulse-width distortion

! 200 mΩ R

stage

! CMOS-compatible logic inputs

! Thermal protection

! Thermal warning output

! Undervoltage protection

complementary DMOS output

dsON

STA516B

65-volt, 7.5-amp, quad power half bridge

Description

PowerSO36 package

with exposed pad up
STA516B is a monolithic quad half-bridge stage in
Multipower BCD Technology. The device can be
used as dual bridge or reconfigured, by
connecting pin CONFIG to pins VDD, as a single
bridge with double-current capability or as a half
bridge (binary mode) with half-current capability.

The device is intended for the output stage of a
stereo all-digital high-efficiency amplifier. It is
capable of delivering 200 W + 200 W into 6-Ω
loads with THD = 10% at V

= 51 V or, in single

CC

The input pins have a threshold proportional to
the voltage on pin VL.

The STA516B is aimed at audio amplifiers in Hi-Fi
applications, such as home theatre systems,
active speakers and docking stations.

It comes in a 36-pin PowerSO package with

exposed pad up (EPU).
BTL configuration, 400 W into a 3-Ω load with
THD = 10% at V

Table 1. Device summary

Order code Temperature range Package Packaging

STA516B 0 to 90 °C PowerSO36 EPU Tube

STA516B13TR 0 to 90 °C PowerSO36 EPU Tape and reel

= 52 V.

CC

November 2010 Doc ID 13183 Rev 4 1/17

www.st.com

17

Introduction STA516B

1 Introduction

The STA516B is a high performance quad half-bridge amplifier with the capability to drive up
to 220 W

(a)

stereo into 3- to 8-ohm speakers from a single 50 V supply.

It offers the highest flexibility since it can be configured as a stereo-BTL, as a mono-BTL or
as four channels of single-ended outputs to fit different application requirements.

It provides remarkably high levels of efficiency when driven by the FFX-patented 3-state
pulse-width modulator embedded in STMs digital audio processors .

The device is self-protected by design. Overcurrent, overtemperature, under- and
overvoltage protection are provided with an automatic recovery feature to safeguard the
device and speakers against fault conditions that could damage the overall system.

a. The achievable output power depends on the thermal configuration of the final application.

A high performance thermal interface material between the package exposed pad and the heat sink should be
used in order to maximize output power levels

2/17 Doc ID 13183 Rev 4

STA516B Pin description

2 Pin description

Figure 1. Pin out

VCC_SIGN
VCC_SIGN

TH_WARN

TRISTATE

PWRDN

CONFIG

GND_REG

GND_CLEAN

Table 2. Pin function

VSS

VSS
IN2B
IN2A
IN1B
IN1A

FAU LT

VL
VDD
VDD

36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19

STA516B

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18

Pin Name Type Description

1 GND_SUB PWR Substrate ground

2, 3 OUT2B O Output half bridge 2B

4 VCC2B PWR Positive supply

SUB_GND
OUT2B
OUT2B
VCC2B
GND2B
GND2A
VCC2A
OUT2A
OUT2A
OUT1B
OUT1B
VCC1B
GND1B
GND1A
VCC1A
OUT1A
OUT1A
N.C.

5 GND2B PWR Negative supply

6 GND2A PWR Negative supply

7 VCC2A PWR Positive supply

8, 9 OUT2A O Output half bridge 2A

10, 11 OUT1B O Output half bridge 1B

12 VCC1B PWR Positive supply

13 GND1B PWR Negative supply

14 GND1A PWR Negative supply

15 VCC1A PWR Positive supply

16, 17 OUT1A O Output half bridge 1A

18 N.C. - No internal connection

19 GND_CLEAN PWR Logical ground

20 GND_REG PWR Ground for regulator V

DD

21, 22 VDD PWR 5-V regulator referred to ground

23 VL PWR High logical state setting voltage, V

Doc ID 13183 Rev 4 3/17

L

Pin description STA516B

Table 2. Pin function (continued)

Pin Name Type Description

Configuration pin:

24 CONFIG I

25 PWRDN I

26 TRISTATE I

27 FAULT O

28 TH_WARN O

29 IN1A I Input of half bridge 1A

30 IN1B I Input of half bridge 1B

0: normal operation
1: bridges in parallel (OUT1A = OUT1B, OUT2A = OUT2B (If
IN1A = IN1B, IN2A = IN2B))

Standby pin:
0: low-power mode

1: normal operation

Hi-Z pin:
0: all power amplifier outputs in high impedance state

1: normal operation

Fault pin advisor (open-drain device, needs pull-up resistor):
0: fault detected (short circuit or thermal, for example)

1: normal operation

Thermal warning advisor (open-drain device, needs pull-up
resistor):

0: temperature of the IC >130 °C
1: normal operation

31 IN2A I Input of half bridge 2A

32 IN2B I Input of half bridge 2B

33, 34 VSS PWR 5-V regulator referred to +V

35, 36 VCC_SIGN PWR Signal positive supply

CC

4/17 Doc ID 13183 Rev 4

STA516B Electrical specifications

3 Electrical specifications

Table 3. Absolute maximum ratings

Symbol Parameter Value Unit

V

CC_MAX

V

max

T

j_MAX

T

stg

DC supply voltage (pins 4, 7, 12, 15) 65 V

Maximum voltage on pins 23 to 32 5.5 V

Operating junction temperature 0 to 150 °C

Storage temperature -40 to 150 °C

Warning: Stresses beyond those listed under “Absolute maximum

ratings” may cause permanent damage to the device. These
are stress ratings only, and functional operation of the device
at these or any other conditions beyond those indicated
under “Recommended operating condition” are not implied.
Exposure to absolute-maximum-rated conditions for
extended periods may affect device reliability. In the real
application, power supplies with nominal values rated within
the recommended operating conditions, may experience
some rising beyond the maximum operating conditions for a
short time when no or very low current is being drawn
(amplifier in mute state, for instance). In this case the
reliability of the device is guaranteed, provided that the
absolute maximum rating is not exceeded.

Table 4. Thermal data

Symbol Parameter Min Typ Max Unit

T

j-case

T

warn

T

jSD

t

hSD

Table 5. Recommended operating conditions

Thermal resistance junction to case (thermal pad) - 1 2.5 °C/W

Thermal warning temperature - 130 - °C

Thermal shut-down junction temperature - 150 - °C

Thermal shut-down hysteresis - 25 - °C

Symbol Parameter Min Typ Max Unit

V

T

CC

amb

Supply voltage for pins PVCCA, PVCCB 10 - 58 V

Ambient operating temperature 0 - 90 °C

Doc ID 13183 Rev 4 5/17

Electrical specifications STA516B

Unless otherwise stated, the test conditions for Ta bl e 6 below are VL = 3.3 V, VCC = 50 V
and T

Table 6. Electrical characteristics

Symbol Parameter Test conditions Min Typ Max Unit

amb

= 25 °C

R

I

g

g

dsON

dss

N

P

Power P-channel/N-channel
MOSFET R

dsON

Power P-channel/N-channel
leakage Idss

Power P-channel R

dsON

matching

Power N-channel R

dsON

matching

= 1 A - 200 240 mΩ

I

dd

- --50µA

= 1 A 95--%

I

dd

= 1 A 95--%

I

dd

Dt_s Low current dead time (static) see Figure 2 - 1020ns

L = 22 µH, C = 470 nF

= 8 Ω, Idd = 4.5 A

R

L

--50ns

see Figure 3

Resistive load
see Figure 2

Resistive load
see Figure 2

--25ns

--25ns

V

/ 2 +

L

300 mV

/ 2

-

V

L

300 mV

L

= 3.3 V - 35 - µA

V

L

-1-µA

--V

V

Dt_d

t

d ON

t

d OFF

t

r

t

f

V

IN-High

V

IN-Low

I

IN-H

I

IN-L

I

PWRDN-H

High current dead time
(dynamic)

Turn-on delay time Resistive load - - 100 ns

Turn-off delay time Resistive load - - 100 ns

Rise time

Fall time

High level input voltage - - -

Low level input voltage -

High level input current VIN = V

Low level input current VIN = 0.3V -1 -µA

High level PWRDN pin input
current

Low logical state voltage

V

Low

(pins PWRDN, TRISTATE)

= 3.3 V 0.8 - V

V

L

(seeTa bl e 7 )

High logical state voltage

V

High

(pins PWRDN, TRISTATE)

= 3.3 V - 1.7 V

V

L

(seeTa bl e 7 )

I

VCC-

PWRDN

Supply current from VCC in
power down

V

PWRDN

= 0 V --2.4mA

Output current on pins

I

FAULT

FAULT, TH_WARN with fault

V

= 3.3V -1-mA

pin

condition

I

VCC-HiZ

Supply current from VCC in
3-state

V

TRISTATE

= 0 V - 22 - mA

6/17 Doc ID 13183 Rev 4

STA516B Electrical specifications

Table 6. Electrical characteristics (continued)

Symbol Parameter Test conditions Min Typ Max Unit

Input pulse width
= 50% duty,

switching frequency

-70-mA

=384kHz,
no LC filters

-7.58.510A

I

VCC

I

OCP

Supply current from VCC in
operation, both channels
switching)

Overcurrent protection
threshold Isc (short-circuit
current limit)

(1)

V

UVP

V

OVP

t

pw_min

1. See application note AN1994

Table 7. Threshold switching voltage variation with voltage on pin VL

Voltage on pin VL, V

Undervoltage protection
threshold

Overvoltage protection
threshold

--7-V

-6162.5V

Output minimum pulse width No load 50 - 110 ns

V

L

max V

LOW

min Unit

HIGH

2.7 1.05 1.65 V

3.3 1.4 1.95 V

5.0 2.2 2.8 V

Table 8. Logic truth table

Pin

TRISTATE

Inputs as per Figure 3 Transistors as per Figure 3

Output mode

INxA INxB Q1 Q2 Q3 Q4

0 x x Off Off Off Off Hi Z

100OffOffOnOnDump

101OffOnOnOffNegative

110OnOffOffOnPositive

111OnOnOffOffNot used

Doc ID 13183 Rev 4 7/17

Electrical specifications STA516B

3.1 Test circuits

Figure 2. Test circuit

Low current dead time = MAX(DTr,DTf)

+Vcc

Duty cycle = 50%

M58

INxY

M57

OUTxY

gnd

Figure 3. Current dead-time test circuit

High Current Dead time for Bridge application = ABS(DTout(A)-DTin(A))+ABS(DTOUT(B)-DTin(B))

Duty cycle=A Duty cycle=B

M58

DTin(A)

INxA

M57

Q1

Q3

OUTxA

Iout=4.5A

DTout(A)

C69

470nF

+V

Rload=8Ω

C71 470nF

OUTxY

Vcc

(3/4)Vcc

(1/2)Vcc

(1/4)Vcc

t

DTfDTr

R 8Ω

+

V67 =

-

vdc = Vcc/2

D03AU1458

CC

M64

OUTxB

Q2

INxB

M63

Q4

DTout(B) DTin(B)

L68 22µL67 22µ

Iout=4.5A

C70

470nF

Duty cycle A and B: Fixed to have DC output current of 4.5A in the direction shown in figure

8/17 Doc ID 13183 Rev 4

D00AU1162

STA516B Power supply and control sequencing

4 Power supply and control sequencing

To guarantee correct operation and reliability, the recommended power-on/off sequence as
shown in Figure 4 should be followed

Figure 4. Suggested power-on/off sequence

V

Vcc > V

L

PWRDN

IN

V

should be turned on before VL. This prevents uncontrolled current flowing through the

CC

internal protection diode connected between V

V

cc

V

L

(logic supply) and V

L

t

t

t

(high power supply).

CC

which could result in damage to the device.

PWRDN must be released after V

is switched on. An input signal can then be sent to the

L

power stage.

Doc ID 13183 Rev 4 9/17

Applications information STA516B

5 Applications information

The STA516B is a dual channel H-bridge that is able to deliver 200 W per channel (into
R

=6Ω with THD = 10% and VCC = 51V) of audio output power very efficiently. It operates

L

in conjunction with a pulse-width modulator driver such as the STA321 or STA309A.

The STA516B converts ternary, phase-shift or binary-controlled PWM signals into audio
power at the load. It includes a logic interface, integrated bridge drivers, high efficiency
MOSFET outputs and thermal and short-circuit protection circuitry.

In differential mode (ternary, phase-shift or binary differential), two logic level signals per
channel are used to control high-speed MOSFET switches to connect the speaker load to
the input supply or to ground in a bridge configuration, according to the damped ternary
modulation operation.

In binary mode, both full bridge and half bridge modes are supported. The STA516B
includes overcurrent and thermal protection as well as an undervoltage lockout with
automatic recovery. A thermal warning status is also provided.

Figure 5. Block diagram of full-bridge FFX

INL[1,2]

INR[1,2]

VL

PWRDN

TRISTATE

FAULT

THWARN

Logic
interface
and
decode

Protection

Regulators

®

or binary mode

Left
H-bridge

Right
H-bridge

Figure 6. Block diagram of binary half-bridge mode

INL[1,2]

INR[1,2]

VL

PWRDN

TRISTATE

FAULT

THWARN

Logic
interface
and
decode

Protection

Regulators

LeftA
½-bridge

LeftB
½-bridge

RightA
½-bridge

RightB
½-bridge

OUTPL

OUTNL

OUTPR

OUTNR

OUTPL

OUTNL

OUTPR

OUTNR

5.1 Logic interface and decode

The STA516B power outputs are controlled using one or two logic-level timing signals. In
order to provide a proper logic interface, the VL input must operate at the same voltage as
the FFX

10/17 Doc ID 13183 Rev 4

®

control logic supply.

STA516B Applications information

5.2 Protection circuitry

The STA516B includes protection circuitry for overcurrent and thermal overload conditions.
A thermal warning pin (THWARN, pin 28, open drain MOSFET) is activated low when the IC
temperature exceeds 130 °C, just in advance of thermal shutdown. When a fault condition is
detected an internal fault signal immediately disables the output power MOSFETs, placing
both H-bridges in a high-impedance state. At the same time the open-drain MOSFET of pin
FAULT (pin 27) is switched on.

There are two possible modes subsequent to activating a fault.

" Shutdown mode: with pins FAULT (with pull-up resistor) and TRISTATE separate, an

activated fault disables the device, signalling a low at pin FAULT output.
The device may subsequently be reset to normal operation by toggling pin TRISTATE
from high to low to high using an external logic signal.

" Automatic recovery mode: This is shown in the applications circuits below where pins

FAULT and TRISTATE are connected together to a time-constant circuit (R59 and C58).
An activated fault forces a reset on pin TRISTATE causing normal operation to resume
following a delay determined by the time constant of the circuit.
If the fault condition persists, the circuit operation repeats until the fault condition is
cleared.
An increase in the time constant of the circuit produces a longer recovery interval. Care
must be taken in the overall system design not to exceed the protection thresholds
under normal operation.

5.3 Power outputs

The STA516B power and output pins are duplicated to provide a low-impedance path for the
device bridged outputs. All duplicate power, ground and output pins must be connected for
proper operation.

The PWRDN or TRISTATE pin should be used to set all power MOSFETs to the
high-impedance state during power-up until the logic power supply, V

5.4 Parallel output / high current operation

When using the FFX® mode output, the STA516B outputs can be connected in parallel to
increase the output current capability to the load. In this configuration the STA516B can
provide up to 400 W into a 3-Ω load.

This mode of operation is enabled with pin CONFIG (pin 24) connected to pin VDD. The
inputs are joined so that IN1A = IN1B, IN2A = IN2B and similarly the outputs
OUT1A = OUT1B, OUT2A = OUT2B as shown in Figure 8.

5.5 Output filtering

A passive 2nd-order filter is used on the STA516B power outputs to reconstruct the analog
audio signal. System performance can be significantly affected by the output filter design
and choice of passive components. Filter designs for 3- and 6-Ω loads are shown in the
applications circuits of Figure 7, Figure 8 and Figure 9.

, has settled.

L

Doc ID 13183 Rev 4 11/17

Applications information STA516B

5.6 Applications circuits

Figure 7. Typical stereo-BTL configuration for 200 W per channel

+V

CC

C55

1000µF

8Ω

6 Ω

6 Ω

8Ω

+3.3V

TH_WAR

C58

100nF

V

1A

CC

15

IN1A

CONFIG

PWRDNPWRDN

FAULT

TRI-STATE

TH_WAR

VCCSIGN

SIGN

V

CC

GND-Reg

GND-Clean

GNDSUB

IN1B

IN2A

IN2B

29

V

23

L

24

25

PROTECTIONS

27

&

LOGIC

26

28

30

21

V

DD

V

22

DD

33

V

REGULATORS

SS

34

V

SS

35

36

31

20

19

32

1

IN1A

R57

R59

10K

10K

C58

100nF

IN1B

C53

100nF

C60

100nF

IN2A

IN2B

M3

M2

M5

M4

M17

M15

M16

M14

C30
1µF

17

OUT1A

16

OUT1A

GND1A

14

1B

12

V

CC

OUT1B

OUT1B

GND1B

V

CC

OUT2A

OUT2A

GND2A

V

CC

OUT2B

OUT2B

GND2B

C31
1µF

2A

C32
1µF

2B

C33
1µF

11

10

13

7

8

9

6

4

3

2

5

L18 22µH

C52

330pF

R63

20

L19 22µH

L113 22µH

C109

330pF

R104

20

L112 22µH

D00AU1148B

C20

100nF

R98

R100

C21

100nF

C110
100nF

R103

R102

C111
100nF

C99

100nF

6

6

6

6

470nF

C101

100nF

C107

100nF

470nF

C106

100nF

C23

C108

Figure 8 below shows a single-BLT configuration capable of giving 400 W into a 3-Ω load at

10% THD with V

= 52 V. This result was obtained using the STA30X+STA50X demo

CC

board. Note that a PWM modulator as driver is required.

Figure 8. Typical single-BTL configuration for 400 W

V

L

+3.3V

100nF

100nF

10K

X7R

TH_WAR

nPWRDN

10K

100nF

IN1A

IN1B

100nF

X7R

100nF

X7R

Add.

12/17 Doc ID 13183 Rev 4

23 N.C.

GND-Clean

19

GND-Reg

20

V

DD

21

V

DD

22

CONFIG

24

TH_WAR

28

PWRDN

25

FAULT

27

26

TRI-STATE

IN1A

29

IN1B

30

IN2A

31

IN2B

32

V

SS

33

V

SS

34

VCCSIGN

35

SIGN

V

CC

36

GNDSUB

1

18

17

OUT1A

16

OUT1A

11

OUT1B

10

OUT1B

OUT2A

9

OUT2A

8

OUT2B

3

OUT2B

2

V

1A

CC

15

V

1B

CC

12

2A

V

CC

7

2B

V

CC

4

GND1A

14

GND1B

13

GND2A

6

GND2B

5

22Ω

1/2W

330pF

1µF

X7R

1µF

X7R

D04AU1545

12µH

12µH

1/2W

1/2W

100nF

FILM

100nF

6.2
X7R

680nF

100nF

FILM

2200µF

63V

100nF

X7R

V

+36V

V

+36V

FILM

CC

CC

6.2

3 Ω

4Ω

STA516B Applications information

Figure 9. Typical quad half-bridge configuration for 100 W per channel

+V

CC

C21

2200µF

4Ω

3 Ω

4Ω

3 Ω

3 Ω

4Ω

3 Ω

4Ω

+3.3V

TH_WAR

100nF

V

1P

CC

IN1A

R57

R59

10K

10K

C58

100nF

IN1B

C58

C53

100nF

C60

100nF

IN2A

IN2B

CONFIG

PWRDNPWRDN

FAULT

TRI-STATE

TH_WAR

VCCSIGN

V

SIGN

CC

GND-Reg

GND-Clean

GNDSUB

23

V

L

24

25

PROTECTIONS

27

LOGIC

26

28

30

IN1B

21

V

DD

22

V

DD

33

V

REGULATORS

SS

34

V

SS

35

36

IN2A

31

20

19

32

IN2B

1

29

IN1A

M3

M2

&

M5

M4

M17

M15

M16

M14

15

17

16

14

12

11

10

13

7

8

9

6

4

3

2

5

OUTPL

OUTPL

PGND1P

V

CC

OUTNL

OUTNL

PGND1N

V

CC

OUTPR

OUTPR

PGND2P

V

CC

OUTNR

OUTNR

PGND2N

D03AU1474

R61

C31 820µF

C81

100nF

C82

100nF

C83

100nF

C84

100nF

5K

C91
1µF

R62

5K

R63

C32 820µF

5K

C92
1µF

R64

5K

R65

C33 820µF

5K

C93
1µF

R66

5K

R67

C34 820µF

5K

C94
1µF

R68

5K

L11 22µH

C71

R41

100nF

20

R51

C41

330pF

1N

C51
1µF

100nF

330pF

2P

330pF

2N

C52
1µF

100nF

330pF

6

C61

L12 22µH

C72

R42

100nF

20

R52

C42

6

L13 22µH

C73

R43

100nF

20

R53

C43

6

C62

L14 22µH

C74

R44

100nF

20

R54

C44

6

For more information, refer to the applications note AN1994.

Doc ID 13183 Rev 4 13/17

Package mechanical data STA516B

Figure 10. PowerSO36 exposed pad up outline drawing

6 Package mechanical data

14/17 Doc ID 13183 Rev 4

STA516B Package mechanical data

Table 9. PowerSO36 exposed pad up dimensions

Dimensions in mm Dimensions in inch

Symbol

Min Typ Max Min Typ Max

A 3.25 - 3.43 0.128 - 0.135

A2 3.10 - 3.20 0.122 - 0.126

A4 0.80 - 1.00 0.031 - 0.039

A5-0.20--0.008-

a1 0.03 - -0.04 0.001 - -0.002

b 0.22 - 0.38 0.009 - 0.015

c 0.23 - 0.32 0.009 - 0.013

D 15.80 - 16.00 0.622 - 0.630

D1 9.40 - 9.80 0.370 - 0.386

D2-1.00--0.039-

E 13.90 - 14.50 0.547 - 0.571

E1 10.90 - 11.10 0.429 - 0.437

E2--2.90--0.114

E3 5.80 - 6.20 0.228 - 0.244

E4 2.90 - 3.20 0.114 - 0.126

e - 0.65 - - 0.026 -

e3 - 11.05 - - 0.435 -

G0-0.080-0.003

H 15.50 - 15.90 0.610 - 0.626

h--1.10--0.043

L 0.80 - 1.10 0.031 - 0.043

M 2.25 - 2.60 0.089 - 0.102

N - - 10 degrees - - 10 degrees

R - 0.6 - - 0.024 -

s - - 8 degrees - - 8 degrees

In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK

®

packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK

®

is an ST trademark.

Doc ID 13183 Rev 4 15/17

Revision history STA516B

7 Revision history

Table 10. Document revision history

Date Revision Changes

01-Feb-2007 1 Initial release.

19-Mar-2007 2 Update to reflect product maturity

11-Aug-2009 3 Updated section Description on cover page.

Modified presentation

16-Nov-2010 4

Updated Chapter 3: Electrical specifications on page 5
Added Chapter 5: Applications information on page 10

16/17 Doc ID 13183 Rev 4

STA516B

Please Read Carefully:

Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the
right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any
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