Datasheet STA505 Datasheet (SGS Thomson Microelectronics)

40V 3.5A QUAD POWER HALF BRIDGE

■ MINIMUM INPUT OUTPUT PULSE WIDTH

DISTORTION

■ 200mΩ R

OUTPUT STA GE

■ CMOS COMPATIBLE LOGIC INPUTS

■ THERMAL PROTECT I O N

■ THERMAL WARNING OUTPUT

■ UNDER VOLTAGE PROTECTION

DESCRIPTION

STA505 is a monoli thic quad half bridge stage in Mul­tipower BCD Technology. The device can be us ed as
dual bridge or reconfigured, by connecting CONFIG
pin to Vdd pin, as single bridge with double current
capability, and as half bridge (Binary mode) with half
current capability.

The device is particularly designed to make the out-

COMPLEMENTAR Y DM OS

dsON

STA505

MULTIPOWER BCD TECHNOLOGY

PowerSO36

ORDERING NUMBER: STA505

put stage of a stereo All-Digital High Efficiency
(DDX™) amplifier capable to deliver 50 + 50W @
THD = 10% at V
80W @ THD = 10% at V
BTL configuration.

The input pins have threshold proportional to Ibias
pin voltage.

30V output power on 8Ω load and

cc

36V on 8Ω load in single

cc

AUDIO APPLICATION CIRCUIT (Dual BTL)

29

IN1A

+3.3V

TH_WAR

100nF

C58

R57
10K

100nF

C60

100nF

R59
10K

C58

C53

100nF

IN1A

IN1B

IN2A

IN2B

IBIAS

CONFIG

PWRDNPWRDN

FAULT

TRI-STATE

TH_WAR

IN1B

V
V
V
V

VCCSIGN

V

SIGN

CC

IN2A

GND-Reg

GND-Clean

IN2B 32

GNDSUB

DD
DD
SS
SS

23
24

25

27
26

28

30

21
22
33
34

35

36

31

20

19

1

PROTECTIONS

&

LOGIC

REGULATORS

M17

M15

M16

M14

1A

V

CC

15

M3

M2

M5

M4

C30
1µF

17

OUT1A

16

OUT1A

14

GND1A

12

V

1B

CC

OUT1B

OUT1B

GND1B

2A

V

CC

OUT2A

OUT2A
GND2A

2B

V

CC

OUT2B

OUT2B

GND2B

C32
1µF

C31
1µF

C33
1µF

11

10

13

7

8

9

6

4

3

2

5

L18 22µH

C52

330pF

R63

20

L19 22µH

L113 22µH

C109

330pF

R104

20

L112 22µH

D00AU1148B

C20

100nF

R98

6

R100

6

C21

100nF

C110

100nF

R103

6

R102

6

C111

100nF

C99

100nF

470nF

C101

100nF

C107

100nF

C108

470nF

C106

100nF

C23

+V

1000µF

CC

C55

July 2003

1/9

STA505

PIN FUNCTION

N° Pin Description

1 GND-SUB Substrate ground

35 ; 36 Vcc Sign Signal Positive Supply

15 Vcc1A Positive Supply
12 Vcc1B Positive Supply

7 Vcc2A Positive Supply

4 Vcc2B Positive Supply
14 GND1A Negative Supply
13 GND1B Negative Supply

6 GND2A Negative Supply

5 GND2B Negative Supply

16 ; 17 OUT1A Output half bridge 1A
10 ; 11 OUT1B Output half bridge 1B

8 ; 9 OUT2A Output half bridge 2A
2 ; 3 OUT2B Output half bridge 2B

29 IN1A Input of half bridge 1A
30 IN1B Input of half bridge 1B
31 IN2A Input of half bridge 2A
32 IN2B Input of half bridge 2B

21 ; 22 Vdd 5V Regulator referred to ground
33 ; 34 Vss 5V Regulator referred to +Vcc

25 PWRDN Stand-by pin
26 TRI-STATE Hi-Z pin
27 FAULT Fault pin advisor
24 CONFIG Configuration pin
28 TH-WAR Thermal warning advisor
19 GND-clean Logical ground
23 IBIAS High logical state setting voltage
18 NC Not connected
20 GND-Reg Ground for regulator Vdd

2/9

FUNCTIONAL PIN STATUS

PIN NAME Logical value IC -STATUS

FAULT 0 Fault detected (Short circuit, or Thermal ..)

STA505

FAULT

(*)

1 Normal Operation

TRI-STATE 0 All powers in Hi-Z state
TRI-STATE 1 Normal operation

PWRDN 0 Low absorpion
PWRDN 1 Normal operation

THWAR 0 Temperature of the IC =130C

THWAR

(*)

1 Normal operation

CONFIG 0 Normal Operation

CONFIG

(*) : The pin is open collector. To have the high logic va l ue, it needs to be pulled up by a r esistor.
(**): To put CONFIG = 1 mean s c onnect Pin 24 (CONFIG) to Pins 21, 22 (Vdd)

(**)

1 OUT1A=OUT1B ; OUT2A=OUT2B

(IF IN1A = IN1B; IN2A = IN2B)

PIN CONNECTION

V

Sign

CC

VCCSign

V

SS

V

SS

IN2B

IN1B
IN1A

FAULT

TRI-STATE

PWRDN

CONFIG

IBIAS

V

DD

V

DD

36
35
34
33
32
31
30
29
28

26
25

23
22
21
20
19

D01AU1273

1
2
3
4
5
6
7
8

9
1027
11
12
1324
14
15
16
17
18

GND-SUB
OUT2B
OUT2B

2B

V

CC

GND2B
GND2AIN2A
V

2A

CC

OUT2A
OUT2ATH_WAR
OUT1B
OUT1B
V

1B

CC

GND1B
GND1A
V

1A

CC

OUT1A
OUT1AGND-Reg
N.C.GND-Clean

3/9

STA505

ABSOLUTE MAXIMUM RATINGS

Symbol Parameter Value Unit

V

CE

V

max

T

op

T

stg

DC Supply Voltage (Pin 4,7,12,15) 40 V
Maximum Voltage on pins 23 to 32 5.5 V
Operating Temperature Range 0 to 70 °C

, TjStorage and Junction Temperature -40 to 150 °C

THERMAL DATA

Symbol Parameter Min. Typ. Max. Unit

T

j-case

T

T

warn

t

hSD

ELECTRICAL CHARACTERISTCS

Symbol Parameter Test conditions Min. Typ. Max. Unit

R

dsON

I

Thermal Resistance Junction to Case (thermal pad) 2.5 °C/W
Thermal shut-down junction temperature 150 °C

jSD

Thermal war ning tempe rature 130 °C
Thermal shut-d own hysteresis 25 °C

(Ibias = 3.3V; Vcc = 30V; T = 25°C unless otherwise specified)

Power Pchannel/Nchannel
MOSFET RdsON

Power Pchannel/Nchannel

dss

leakage Idss

Id=1A; 200 270 mΩ

Vcc=35V 50 µA

Power Pchannel RdsON

g

N

Id=1A 95 %

Matching

g

Power Nchannel RdsON

P

Id=1A 95 %

Matching
Dt_s Low current Dead Time (static) see test circuit no.1; see fig. 1 10 20 ns
Dt_d High current Dead Time (dinamic) L=22µH; C = 470nF; Rl = 8 Ω

50 ns

Id=3.5A; see fig. 3

t

d ON

t

d OFF

V

V

Turn-on delay time Resistive load 100 ns

Turn-off delay time Resistive load 100 ns

t

Rise time Resistive load; as fig.1; 25 ns

r

t

Fall time Resistive load; as fig. 1; 25 ns

f

Supply voltage operating voltage 9 36 V

CC

High level input voltage Ibias/2

IN-H

+300mV

V

Low level input voltage Ibias/2

IN-L

-300mV

I

IN-H

I

IN-L

Hi level Input current Pin voltage = Ibias 1 µA

Low level input current Pin voltage = 0.3V 1 µA

V

V

4/9

STA505

ELECTRICAL CHARACTERISTCS

(continued)

Symbol Parameter Test conditions Min. Typ. Max. Unit

I

PWRDN-H

Hi level PWRDN pin input current Ibias = 3.3V 35 µA

V

Low logical state voltage VL (pin

L

Ibias = 3.3V 0.8 V

PWRDN, TRISTATE) (note 1)

V

High logical state voltage VH (pin

H

Ibias = 3.3V 1.7 V

PWRDN, TRISTATE) (note 1)

I

VCC-

PWRDN

I

FAULT

Supply current from Vcc in Power

Down

Output Current pins

FAULT -TH-WARN when

PWRDN = 0 3 mA

Vpin = 3.3V 1 mA

FAULT CONDITIONS

I

VCC-hiz

Supply current from Vcc in Tri-

Tri-state=0 22 mA

state
I

VCC

I

VCC-q

Supply current from Vcc in

operation

both channel switching)

Isc (short circuit current limit)

Input pulse width = 50% Duty;
Switching Frequency = 384Khz;
No LC filters;

80 mA

3.5 6 8 A

(note 2)

I

OUT-SH

Undervoltage protection threshold 7 V

V

Notes: 1. The following table explains the VL, VH variation with Ibias

Output minimum pulse width No Load 70 150 ns

OV

Ibias VLmin VHmax Unit

2.7 0.7 1.5 V

3.3 0.8 1.7 V
5 0.85 1.85 V

Note 2: If used in single BTL configuration, the device may be not short circuit protected

LOGIC TRUTH TABLE

(see fig. 2)

TRI-STATE INxA INxB Q1 Q2 Q3 Q4

0 x x OFF OFF OFF OFF Hi-Z
1 0 0 OFF OFF ON ON DUMP
1 0 1 OFF ON ON OFF NEGATIVE
1 1 0 ON OFF OFF ON POSITIVE
1 1 1 ON ON OFF OFF Not used

OUTPUT

MODE

5/9

STA505

Figure 1. Tes t Circ ui t.

Low current dead time = MAX(DTr,DTf)

Duty cycle = 50%

INxY

M58

+Vcc

OUTxY

OUTxY

Vcc

(3/4)Vcc

(1/2)Vcc
(1/4)Vcc

t

DTfDTr

R 8Ω

Figure 2.

Figure 3.

M57

gnd

+V

CC

Q1

INxA INxB

OUTxA

Q3

GND

High Current Dead time for Bridge application = ABS(DTout(A)-DTin(A))+ABS(DTOUT(B)-DTin(B))

+V

Q2

OUTxB

Q4

D00AU1134

CC

+

V67 =

-

vdc = Vcc/2

D03AU1458

Duty cycle=A Duty cycle=B

M58

DTin(A)

INxA

M57

Duty cycle A and B: Fixed to have DC output current of 3.5A in the direction shown in figure

Q1

OUTxA

Q3

DTout(A)

Iout=3.5A

C69

470nF

Rload=8Ω

C71 470nF

DTout(B) DTin(B)

L68 22µL67 22µ

Iout=3.5A

C70

470nF

Q2

OUTxB

Q4

M64

M63

6/9

INxB

D00AU1162

STA505

Figure 4. Typical Single BTL Configuration to obtain 80W @ THD 10%, RL = 8Ω, VCC = 36V (note 1)

IBIAS

+3.3V

TH_WAR

10K

nPWRDN

IN1A

IN1B

100nF

100nF

X7R

10K

100nF

100nF

X7R

100nF

X7R

Add.

GND-Clean

GND-Reg

TH_WAR

FAULT

TRI-STATE

VCCSIGN

V

GNDSUB

23 N.C.

19

20

V

DD

21

V

DD

22

CONFIG

24

28

PWRDN

25

27
26

IN1A

29

IN1B

30

IN2A

31

IN2B

32

V

SS

33

V

SS

34

35

SIGN

CC

36

1

18

17

OUT1A

16

OUT1A

11

OUT1B

10

OUT1B
OUT2A

9

OUT2A

8

OUT2B

3

OUT2B

2

V

1A

CC

15

1B

V

CC

12

2A

V

CC

7

2B

V

CC

4

GND1A

14

GND1B

13

GND2A

6

GND2B

5

22Ω

1/2W

330pF

1µF
X7R

1µF
X7R

22µH

22µH

6.2

1/2W

6.2

1/2W

100nF

FILM

100nF

FILM

2200µF

63V

100nF

X7R

100nF

X7R

+36V

+36V

470nF

FILM

8Ω

D01AU1274

Note: 1. "A PWM modulator as driver is needed . In part i cular, this res ul t is performed using the ST A 30X+STA50X demo board".

Figure 5. Typical Quad Half bridge Configuration

+V

CC

C21

2200µF

+3.3V

TH_WAR

C58

100nF

1P

V

CC

IN1A

R57

R59

10K

10K

TRI-STATE

C58

100nF

IN1B

C53

100nF

C60

100nF

IN2A

GND-Clean

IN2B

IBIAS

CONFIG

PWRDNPWRDN

FAULT

TH_WAR

IN1B

VCCSIGN

V

SIGN

CC

IN2A

GND-Reg

IN2B 32

GNDSUB

23
24

25

PROTECTIONS

27

&

LOGIC

26

28

30

21

V

DD

V

22

DD

V
V

REGULATORS

33

SS

34

SS

35

36

31

20

19

1

29

IN1A

M3

M2

M5

M4

M17

M15

M16

M14

15

17

16

14

12

11

10

13

7

8

9

6

4

3

2

5

D03AU1474

OUTPL

OUTPL
PGND1P

V

1N

CC

OUTNL

OUTNL

PGND1N

2P

V

CC

OUTPR

OUTPR
PGND2P

V

2N

CC

OUTNR

OUTNR

PGND2N

L11 22µH

C71

R41

100nF

20

C41

330pF

C51

C61

1µF

100nF

R42

C42

330pF

R43

C43

330pF

C52

C62

1µF

100nF

R44

C44

330pF

R51

6

L12 22µH

C72

100nF

20

R52

6

L13 22µH

C73

100nF

20

R53

6

L14 22µH

C74

100nF

20

R54

6

C81

100nF

C82

100nF

C83

100nF

C84

100nF

R61

C31 820µF

5K

C91
1µF

R62

5K

R63

C32 820µF

5K

C92
1µF

R64

5K

R65

C33 820µF

5K

C93
1µF

R66

5K

R67

C34 820µF

5K

C94
1µF

R68

5K

For more information refer to the application notes AN1456 and AN1661

7/9

STA505

DIM.

(1) “D and E1” do not include mold flash or protusions.
(2) No intrusion allowed inwards the leads.

MIN. TYP. MAX. MIN. TYP. MA X.

A 3.25 3.5 0.128 0.138
A2 3.3 0.13
A4 0.8 1 0.031 0.039
A5 0.2 0.008

a1 0 0.075 0 0.003

b 0.22 0.38 0.008 0.015
c 0.23 0.32 0.009 0.012

D 15.8 16 0.622 0.630
D1 9.4 9.8 0.37 0.38
D2 1 0 .039

E 13.9 14.5 0.547 0.57
E1 10.9 11.1 0.429 0.437
E2 2.9 0.114
E3 5.8 6.2 0.228 0.244
E4 2.9 3.2 0.114 1.259

e

e3 11.05 0.435

G 0 0.07 5 0 0.003

H 15.5 15.9 0.61 0.625

h 1.1 0.043
L 0.8 1.1 0.031 0.043

N 10˚ (max)

s 8˚ (max)

Mold flash or protusions sh al l not exceed 0.15 m m (0.006”)

mm inch

0.65 0.026

OUTLINE AND

MECHANICAL DA T A

PowerSO36 (SLUG UP)

8/9

7183931

STA505

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by implic ation or oth erwise under any pat ent or patent rights of STMicroe l ectronics. Specificat i ons menti oned in this publicati on are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics product s are not
authorized for use as cri t i cal compone nt s i n l i f e support dev i ces or systems wi t hout express written approval of STMi croelectronics.

The ST logo is a registered trademark of STMicroelectronics



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9/9