Datasheet SST39SF010A, SST39SF020A, SST39SF040 Datasheet
Features
1 Mbit / 2 Mbit / 4 Mbit (x8) Multi-Purpose Flash
SST39SF010A / SST39SF020A / SST39SF040
Data Sheet
The SST39SF010A / SST39SF020A / SST39SF040 are CMOS Multi-Purpose
Flash (MPF) devices manufactured with SST proprietary, high performance
CMOS SuperFlash technology. The split-gate cell design and thick oxide tunneling injector attain better reliability and manufacturability compared with alternate
approaches. The SST39SF010A / SST39SF020A / SST39SF040 write (Program
or Erase) with a 4.5-5.5V power supply, and conforms to JEDEC standard pinouts
for x8 memories
• Organized as 128K x8 / 256K x8 / 512K x8
• Single 4.5-5.5V Read and Write Operations
• Superior Reliability
– Endurance: 100,000 Cycles (typical)
– Greater than 100 years Data Retention
• Low Power Consumption
(typical values at 14 MHz)
– Active Current: 10 mA (typical)
– Standby Current: 30 µA (typical)
• Sector-Erase Capability
– Uniform 4 KByte sectors
• Fast Read Access Time:
– 55 ns
– 70 ns
• Latched Address and Data
• Automatic Write Timing
– Internal VPP Generation
• Fast Erase and Byte-Program
– Sector-Erase Time: 18 ms (typical)
– Chip-Erase Time: 70 ms (typical)
– Byte-Program Time: 14 µs (typical)
– Chip Rewrite Time:
2 seconds (typical) for SST39SF010A
4 seconds (typical) for SST39SF020A
8 seconds (typical) for SST39SF040
• End-of-Write Detection
– Toggle Bit
– Data# Polling
• TTL I/O Compatibility
• JEDEC Standard
– Flash EEPROM Pinouts and command sets
• Packages Available
– 32-lead PLCC
– 32-lead TSOP (8mm x 14mm)
– 32-pin PDIP
• All devices are RoHS compliant
©2002-2016 DS20005022C 04/16
www.microchip.com
Product Description
The SST39SF010A/020A/040 are CMOS Multi-Purpose Flash (MPF) manufactured with SST’s proprietary, high performance CMOS SuperFlash technology. The split-gate cell design and thick oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. The
SST39SF010A/020A/040 devices write (Program or Erase) with a 4.5-5.5V power supply. The
SST39SF010A/020A/040 devices conform to JEDEC standard pinouts for x8 memories.
Featuring high performance Byte-Program, the SST39SF010A/020A/040 devices provide a maximum
Byte-Program time of 20 µsec. These devices use Toggle Bit or Data# Polling to indicate the completion of Program operation. To protect against inadvertent write, they have on-chip hardware and Software Data Protection schemes. Designed, manufactured, and tested for a wide spectrum of
applications, these devices are offered with a guaranteed typical endurance of 100,000 cycles. Data
retention is rated at greater than 100 years.
The SST39SF010A/020A/040 devices are suited for applications that require convenient and economical updating of program, configuration, or data memory. For all system applications, they significantly
improve performance and reliability, while lowering power consumption. They inherently use less
energy during erase and program than alternative flash technologies. The total energy consumed is a
function of the applied voltage, current, and time of application. Since for any given voltage range, the
SuperFlash technology uses less current to program and has a shorter erase time, the total energy
consumed during any Erase or Program operation is less than alternative flash technologies. These
devices also improve flexibility while lowering the cost for program, data, and configuration storage
applications.
1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash
SST39SF010A / SST39SF020A / SST39SF040
Data Sheet
The SuperFlash technology provides fixed Erase and Program times, independent of the number of
Erase/Program cycles that have occurred. Therefore the system software or hardware does not have
to be modified or de-rated as is necessary with alternative flash technologies, whose Erase and Program times increase with accumulated Erase/Program cycles.
To meet high density, surface mount requirements, the SST39SF010A/020A/040 are offered in 32-lead
PLCC and 32-lead TSOP packages. A 600 mil, 32-pin PDIP is also available. See Figures 2, 3, and 4
for pin assignments.
©2002-2016 DS20005022C 04/16
2
Block Diagram
1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash
SST39SF010A / SST39SF020A / SST39SF040
Data Sheet
Memory Address
Address Buffers & Latches
CE#
OE#
WE#
Control Logic
Figure 1: Functional Block Diagram
X-Decoder
SuperFlash
Memory
Y-Decoder
I/O Buffers and Data Latches
- DQ
DQ
7
0
1147 B1.2
©2002-2016 DS20005022C 04/16
3
Pin Assignment
SST39SF010A
SST39SF010A
SST39SF010A
SST39SF010A
5
6
7
8
9
10
11
12
13
29
28
27
26
25
24
23
22
21
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
SST39SF020ASST39SF040
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
A14
A13
A8
A9
A11
OE#
A10
CE#
DQ7
SST39SF020A SST39SF040
A14
A13
A8
A9
A11
OE#
A10
CE#
DQ7
A14
A13
A8
A9
A11
OE#
A10
CE#
DQ7
4 3 2 1 32 31 30
A12
A15
A16NCVDDWE#
NC
SST39SF020A SST39SF040
A12
A15
A16NCVDDWE#
A17
A12
A15
A16
A18
VDDWE#
A17
32-lead PLCC
Top View
1147 32-plcc P2.4
14 15 16 17 18 19 20
DQ1
DQ2
V
SS
DQ3
DQ4
DQ5
DQ6
SST39SF020ASST39SF040
DQ1
DQ2
V
SS
DQ3
DQ4
DQ5
DQ6
DQ1
DQ2
V
SS
DQ3
DQ4
DQ5
DQ6
1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash
SST39SF010A / SST39SF020A / SST39SF040
Data Sheet
©2002-2016 DS20005022C 04/16
Figure 2: Pin Assignments for 32-lead PLCC
4
1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash
A11
A9
A8
A13
A14
NC
WE#
V
DD
NC
A16
A15
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
V
SS
DQ2
DQ1
DQ0
A0
A1
A2
A3
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
1147 32-tsop P1.1
Standard Pinout
Top View
Die Up
SST39SF010A
A11
A9
A8
A13
A14
A17
WE#
V
DD
NC
A16
A15
A12
A7
A6
A5
A4
A11
A9
A8
A13
A14
A17
WE#
V
DD
A18
A16
A15
A12
A7
A6
A5
A4
SST39SF020ASST39SF040
SST39SF010A
OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
V
SS
DQ2
DQ1
DQ0
A0
A1
A2
A3
OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
V
SS
DQ2
DQ1
DQ0
A0
A1
A2
A3
SST39SF020A SST39SF040
SST39SF010A / SST39SF020A / SST39SF040
Figure 3: Pin Assignments for 32-lead TSOP (8mm x 14mm)
Data Sheet
NC
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
V
SS
SST39SF010A
NC
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Top View
SST39SF040
A18
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
V
SS
SST39SF020A
Figure 4: Pin Assignments for 32-pin PDIP
32-pin
PDIP
SST39SF010A
32
V
DD
31
WE#
30
NC
29
A14
28
A13
27
A8
26
A9
25
A11
24
OE#
23
A10
22
CE#
21
DQ7
20
DQ6
19
DQ5
18
DQ4
17
DQ3
SST39SF020A
V
DD
WE#
A17
A14
A13
A8
A9
A11
OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
1147 32-pdip P3.2
SST39SF040
V
DD
WE#
A17
A14
A13
A8
A9
A11
OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
5
©2002-2016 DS20005022C 04/16
1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash
SST39SF010A / SST39SF020A / SST39SF040
Table 1: Pin Description
Symbol Pin Name Functions
1
A
-A
MS
DQ
-DQ
7
CE# Chip Enable To activate the device when CE# is low.
OE# Output Enable To gate the data output buffers.
WE# Write Enable To control the Write operations.
V
DD
V
SS
NC No Connection Unconnected pins.
1. AMS = Most significant address
A
MS
Address Inputs To provide memory addresses.
0
During Sector-Erase A
Data Input/output To output data during Read cycles and receive input data during Write cycles.
0
address lines will select the sector.
MS-A12
Data is internally latched during a Write cycle.
The outputs are in tri-state when OE# or CE# is high.
Power Supply To provide 5.0V supply (4.5-5.5V)
Ground
= A16 for SST39SF010A, A17 for SST39SF020A, and A18 for SST39SF040
Data Sheet
T1.2 25022
©2002-2016 DS20005022C 04/16
6
Device Operation
Commands are used to initiate the memory operation functions of the device. Commands are written
to the device using standard microprocessor write sequences. A command is written by asserting WE#
low while keeping CE# low. The address bus is latched on the falling edge of WE# or CE#, whichever
occurs last. The data bus is latched on the rising edge of WE# or CE#, whichever occurs first.
Read
The Read operation of the SST39SF010A/020A/040 is controlled by CE# and OE#, both have to be
low for the system to obtain data from the outputs. CE# is used for device selection. When CE# is high,
the chip is deselected and only standby power is consumed. OE# is the output control and is used to
gate data from the output pins. The data bus is in high impedance state when either CE# or OE# is
high. Refer to the Read cycle timing diagram (Figure 5) for further details.
Byte-Program Operation
The SST39SF010A/020A/040 are programmed on a byte-by-byte basis. Before programming, the sector where the byte exists must be fully erased. The Program operation is accomplished in three steps.
The first step is the three-byte load sequence for Software Data Protection. The second step is to load
byte address and byte data. During the Byte-Program operation, the addresses are latched on the falling edge of either CE# or WE#, whichever occurs last. The data is latched on the rising edge of either
CE# or WE#, whichever occurs first. The third step is the internal Program operation which is initiated
after the rising edge of the fourth WE# or CE#, whichever occurs first. The Program operation, once
initiated, will be completed, within 20 µs. See Figures 6 and 7 for WE# and CE# controlled Program
operation timing diagrams and Figure 16 for flowcharts. During the Program operation, the only valid
reads are Data# Polling and Toggle Bit. During the internal Program operation, the host is free to perform additional tasks. Any commands written during the internal Program operation will be ignored.
1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash
SST39SF010A / SST39SF020A / SST39SF040
Data Sheet
Sector-Erase Operation
The Sector-Erase operation allows the system to erase the device on a sector-by-sector basis. The
sector architecture is based on uniform sector size of 4 KByte. The Sector-Erase operation is initiated
by executing a six-byte command load sequence for Software Data Protection with Sector-Erase command (30H) and sector address (SA) in the last bus cycle. The sector address is latched on the falling
edge of the sixth WE# pulse, while the command (30H) is latched on the rising edge of the sixth WE#
pulse. The internal Erase operation begins after the sixth WE# pulse. The End-of-Erase can be determined using either Data# Polling or Toggle Bit methods. See Figure 10 for timing waveforms. Any commands written during the Sector-Erase operation will be ignored.
Chip-Erase Operation
The SST39SF010A/020A/040 provide Chip-Erase operation, which allows the user to erase the entire
memory array to the “1s” state. This is useful when the entire device must be quickly erased.
The Chip-Erase operation is initiated by executing a six- byte Software Data Protection command
sequence with Chip-Erase command (10H) with address 5555H in the last byte sequence. The internal
Erase operation begins with the rising edge of the sixth WE# or CE#, whichever occurs first. During the
internal Erase operation, the only valid read is Toggle Bit or Data# Polling. See Table 4 for the command sequence, Figure 11 for timing diagram, and Figure 19 for the flowchart. Any commands written
during the Chip-Erase operation will be ignored.
©2002-2016 DS20005022C 04/16
7
1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash
SST39SF010A / SST39SF020A / SST39SF040
Write Operation Status Detection
The SST39SF010A/020A/040 provide two software means to detect the completion of a Write (Program or Erase) cycle, in order to optimize the system Write cycle time. The software detection includes
two status bits: Data# Polling (DQ
after the rising edge of WE# which initiates the internal Program or Erase operation.
The actual completion of the nonvolatile write is asynchronous with the system; therefore, either a
Data# Polling or Toggle Bit read may be simultaneous with the completion of the Write cycle. If this
occurs, the system may possibly get an erroneous result, i.e., valid data may appear to conflict with
either DQ
routine should include a loop to read the accessed location an additional two (2) times. If both reads
are valid, then the device has completed the Write cycle, otherwise the rejection is valid.
or DQ6. In order to prevent spurious rejection, if an erroneous result occurs, the software
7
Data# Polling (DQ7)
When the SST39SF010A/020A/040 are in the internal Program operation, any attempt to read DQ7 will
produce the complement of the true data. Once the Program operation is completed, DQ
true data. Note that even though DQ
internal Write operation, the remaining data outputs may still be invalid: valid data on the entire data
bus will appear in subsequent successive Read cycles after an interval of 1 µs. During internal Erase
operation, any attempt to read DQ
DQ
will produce a ‘1’. The Data# Polling is valid after the rising edge of fourth WE# (or CE#) pulse for
7
Program operation. For Sector- or Chip-Erase, the Data# Polling is valid after the rising edge of sixth
WE# (or CE#) pulse. See Figure 8 for Data# Polling timing diagram and Figure 17 for a flowchart.
) and Toggle Bit (DQ6). The End-of-Write detection mode is enabled
7
will produce a ‘0’. Once the internal Erase operation is completed,
7
Data Sheet
will produce
7
may have valid data immediately following the completion of an
7
Toggle Bit (DQ6)
During the internal Program or Erase operation, any consecutive attempts to read DQ6 will produce
alternating 0s and 1s, i.e., toggling between 0 and 1. When the internal Program or Erase operation is
completed, the toggling will stop. The device is then ready for the next operation. The Toggle Bit is valid
after the rising edge of fourth WE# (or CE#) pulse for Program operation. For Sector- or Chip-Erase,
the Toggle Bit is valid after the rising edge of sixth WE# (or CE#) pulse. See Figure 9 for Toggle Bit timing diagram and Figure 17 for a flowchart.
Data Protection
The SST39SF010A/020A/040 provide both hardware and software features to protect nonvolatile data
from inadvertent writes.
Hardware Data Protection
Noise/Glitch Protection: A WE# or CE# pulse of less than 5 ns will not initiate a Write cycle.
V
Power Up/Down Detection: The Write operation is inhibited when VDD is less than 2.5V.
DD
Write Inhibit Mode:
vents inadvertent writes during power-up or power-down.
Forcing OE# low, CE# high, or WE# high will inhibit the Write operation. This pre-
©2002-2016 DS20005022C 04/16
8
1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash
SST39SF010A / SST39SF020A / SST39SF040
Software Data Protection (SDP)
The SST39SF010A/020A/040 provide the JEDEC approved Software Data Protection scheme for all
data alteration operations, i.e., Program and Erase. Any Program operation requires the inclusion of a
series of three-byte sequence. The three-byte load sequence is used to initiate the Program operation,
providing optimal protection from inadvertent Write operations, e.g., during the system power-up or
power-down. Any Erase operation requires the inclusion of six-byte load sequence. The
SST39SF010A/020A/040 devices are shipped with the Software Data Protection permanently
enabled. See Table 4 for the specific software command codes. During SDP command sequence,
invalid commands will abort the device to read mode, within T
Product Identification
The Product Identification mode identifies the device as the SST39SF040, SST39SF010A, or
SST39SF020A and manufacturer as SST. This mode may be accessed by software operations. Users
may wish to use the software Product Identification operation to identify the part (i.e., using the device
ID) when using multiple manufacturers in the same socket. For details, Table 4 for software operation,
Figure 12 for the software ID entry and read timing diagram and Figure 18 for the ID entry command
sequence flowchart.
Data Sheet
RC.
Table 2: Product Identification
Manufacturer’s ID 0000H BFH
Device ID
SST39SF010A 0001H B5H
SST39SF020A 0001H B6H
SST39SF040 0001H B7H
Product Identification Mode Exit/Reset
In order to return to the standard Read mode, the Software Product Identification mode must be exited.
Exit is accomplished by issuing the Exit ID command sequence, which returns the device to the Read
operation. Please note that the software reset command is ignored during an internal Program or
Erase operation. See Table 4 for software command codes, Figure 13 for timing waveform and Figure
18 for a flowchart.
Address Data
T2.2 25022
©2002-2016 DS20005022C 04/16
9
Loading...