Datasheet SST39VF801C, SST39VF802C, SST39LF801C, SST39LF802C Datasheet

A

8 Mbit (x16) Multi-Purpose Flash Plus

Microchip Technology Company

SST39VF801C / SST39VF802C / SST39LF801C / SST39LF802C

The SST39VF801C / SST39VF802C / SST39LF801C / SST39LF802C are 512K
x16 CMOS Multi-Purpose Flash Plus (MPF+) manufactured with SST proprietary,
high performance CMOS SuperFlash® technology. The split-gate cell design and
thick-oxide tunneling injector attain better reliability and manufacturability com­pared with alternate approaches. The SST39VF801C / SST39VF802C /
SST39LF801C / SST39LF802C write (Program or Erase) with a 2.7-3.6V power
supply. These devices conforms to JEDEC standard pinouts for x16 memories.

Features

• Organized as 512K x16

• Single Voltage Read and Write Operations

– 2.7-3.6V for SST39VF801C/802C
– 3.0-3.6V for SST39LF801C/802C

• Superior Reliability

– Endurance: 100,000 Cycles (Typical)
– Greater than 100 years Data Retention

• Low Power Consumption (typical values at 5 MHz)

– Active Current: 5 mA (typical)
– Standby Current: 3 µA (typical)
– Auto Low Power Mode: 3 µA (typical)

• Hardware Block-Protection/WP# Input Pin

– Top Block-Protection (top 8 KWord)
– Bottom Block-Protection (bottom 8 KWord)

• Sector-Erase Capability

– Uniform 2 KWord sectors

• Block-Erase Capability

– Flexible block architecture; one 8-, two 4-, one 16-, and

fifteen 32-KWord blocks

Data Sheet

• Security-ID Feature

– SST: 128 bits; User: 128 words

• Fast Read Access Time:

– 70 ns for SST39VF801C/802C
– 55 ns for SST39LF801C/802C

• Fast Erase and Word-Program:

– Sector-Erase Time: 18 ms (typical)
– Block-Erase Time: 18 ms (typical)
– Chip-Erase Time: 40 ms (typical)
– Word-Program Time: 7 µs (typical)

• Automatic Write Timing

– Internal VPPGeneration

• End-of-Write Detection

– Toggle Bits
– Data# Polling
– Ready/Busy# Pin

• CMOS I/O Compatibility

• JEDEC Standard

– Flash EEPROM Pinouts and command sets

• Chip-Erase Capability

• Erase-Suspend/Erase-Resume Capabilities

• Hardware Reset Pin (RST#)

• Packages Available

– 48-lead TSOP (12mm x 20mm)
– 48-ball TFBGA (6mm x 8mm)
– 48-ball WFBGA (4mm x 6mm)

• All devices are RoHS compliant

• Latched Address and Data

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www.microchip.com

8 Mbit (x16) Multi-Purpose Flash Plus

A

Microchip Technology Company

SST39VF801C / SST39VF802C / SST39LF801C / SST39LF802C

Product Description

The SST39VF801C/802C and SST39LF801C/802C devices are 512K x16 CMOS Multi-Purpose Flash
Plus (MPF+) manufactured with SST proprietary, high performance CMOS SuperFlash technology.
The split-gate cell design and thick-oxide tunneling injector attain better reliability and manufacturability
compared with alternate approaches. The SST39VF801C/802C and SST39LF801C/802C write (Program
or Erase) with a 2.7-3.6V power supply. These devices conform to JEDEC standard pinouts for x16
memories.

Featuring high performance Word-Program, the SST39VF801C/802C and SST39LF801C/802C
devices provide a typical Word-Program time of 7 µsec. These devices use Toggle Bit, Data# Polling,
or the RY/BY# pin to indicate the completion of Program operation. To protect against inadvertent
write, they have on-chip hardware and Software Data Protection schemes. Designed, manufactured,
and tested for a wide spectrum of applications, these devices are offered with a guaranteed typical
endurance of 100,000 cycles. Data retention is rated at greater than 100 years.

The SST39VF801C/802C and SST39LF801C/802C devices are suited for applications that require
convenient and economical updating of program, configuration, or data memory. For all system appli­cations, they significantly improve performance and reliability, while lowering power consumption. They
inherently use less energy during Erase and Program than alternative flash technologies. The total
energy consumed is a function of the applied voltage, current, and time of application. Since for any
given voltage range, the SuperFlash technology uses less current to program and has a shorter erase
time, the total energy consumed during any Erase or Program operation is less than alternative flash
technologies. These devices also improve flexibility while lowering the cost for program, data, and con­figuration storage applications.

Data Sheet

The SuperFlash technology provides fixed Erase and Program times, independent of the number of
Erase/Program cycles that have occurred. Therefore the system software or hardware does not have
to be modified or de-rated as is necessary with alternative flash technologies, whose Erase and Pro­gram times increase with accumulated Erase/Program cycles.

To meet high density, surface mount requirements, the SST39VF801C/802C and SST39LF801C/802C
are offered in 48-lead TSOP, 48-ball TFBGA, and 48-ball WFBGA packages. See Figures 2, 3, and 4
for pin assignments.

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Block Diagrams

Figure 1: Functional Block Diagram

SST39VF801C / SST39VF802C / SST39LF801C / SST39LF802C

Data Sheet

SuperFlash

Memory

Y-Decoder

I/O Buffers and Data Latches

-DQ

DQ

15

0

1434 B1.0

Memory Address

RESET#

RY/BY#

CE#

OE#
WE#
WP#

X-Decoder

Address Buffer Latches

Control Logic

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8 Mbit (x16) Multi-Purpose Flash Plus

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Pin Assignment

SST39VF801C / SST39VF802C / SST39LF801C / SST39LF802C

Data Sheet

A15

A14

A13

A12

A11

A10

NC
NC

WE#

RST#

NC

WP#

RY/BY#

A18

A17

1
2
3
4
5

6
A9
A8

A7
A6
A5
A4
A3
A2
A1

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

Standard Pinout

Top View

Die Up

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25

A16
NC
V

SS

DQ15
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
V

DD

DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
V

SS

CE#
A0

Figure 2: Pin Assignments for 48-Lead TSOP

TOP VIEW (balls facing down)

6

A13

5

4

3

2

1

A9

WE#

RY/BY#

A7

A3

A12

A8

RST#

WP#

A17

A4

A14

A10

NC

A18

A6

A2

A15

A11

NC

NC

A5

A1

ABCDEFGH

Figure 3: Pin Assignments for 48-Ball TFBGA

A16

DQ7

DQ5

DQ2

DQ0

A0

NC

DQ15

DQ14

DQ13

DQ12

V

DD

DQ10

DQ11

DQ8

DQ9

CE#

OE#

1434 48-tfbga B3K P2.0

1434 48-tsop EK P1.0

V

SS

DQ6

DQ4

DQ3

DQ1

V

SS

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8 Mbit (x16) Multi-Purpose Flash Plus

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Figure 4: Pin Assignments for 48-Ball WFBGA

Table 1: Pin Description

Symbol Pin Name Functions

A

DQ

WP# Write Protect To protect the top/bottom boot block from Erase/Program operation when

RST# Reset To reset and return the device to Read mode.

CE# Chip Enable To activate the device when CE# is low.

OE# Output Enable To gate the data output buffers.

WE# Write Enable To control the Write operations.

V

V

NC No Connection Unconnected pins.

RY/BY# Ready/Busy# To output the status of a Program or Erase operation

SST39VF801C / SST39VF802C / SST39LF801C / SST39LF802C

Data Sheet

TOP VIEW (balls facing down)

6

A2

A4

A6

5

A1

4

A0

3

CE#

2

V

SS

1

A3

A5

DQ8

OE#

DQ0

A7

A18

DQ10

DQ9

DQ1

A17

WP#

NC

DQ2NCDQ3NCV

AB C D E F G H J K L

1

-A

MS

-DQ0Data Input/output To output data during Read cycles and receive input data during Write cycles.

15

DD

SS

1. AMS= Most significant address
AMS=A

Address Inputs To provide memory addresses.

0

During Sector-Erase A
During Block-Erase A

Data is internally latched during a Write cycle.
The outputs are in tri-state when OE# or CE# is high.

grounded.

Power Supply To provide power supply voltage: 2.7-3.6V

Ground

RY/BY# is a open drain output, so a 10K - 100K pull-up resistor is required
to allow RY/BY# to transition high indicating the device is ready to read.

18

WE#

RST#

A9

A11

RY/BY#

A10

A13

A14

A8

A12

A15

DQ4

DQ11

A16

NC

DQ5

DQ6

DQ7

DQ12

DQ13

DQ14

DQ15

DD

address lines will select the sector.

MS-A11

address lines will select the block.

MS-A15

V

SS

1434 48-wfbga MAQ P3.0

T1.2 25041

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Table 2: Top / Bottom Boot Block Address

SST39VF801C / SST39VF802C / SST39LF801C / SST39LF802C

Data Sheet

Top Boot Block Address

SST39VF802C/SST39LF802C

#

18 8 7E000H-7FFFFH 18 32 78000H-7FFFFH

17 4 7D000H-7DFFFH 17 32 70000H-77FFFH

16 4 7C000H-7CFFFH 16 32 68000H-6FFFFH

15 16 78000H-7BFFFH 15 32 60000H-67FFFH

14 32 70000H-77FFFH 14 32 58000H-5FFFFH

13 32 68000H-6FFFFH 13 32 50000H-57FFFH

12 32 60000H-67FFFH 12 32 48000H-4FFFFH

11 32 58000H-5FFFFH 11 32 40000H-47FFFH

10 32 50000H-57FFFH 10 32 38000H-3FFFFH

9 32 48000H-4FFFFH 9 32 30000H-37FFFH

8 32 40000H-47FFFH 8 32 28000H-2FFFFH

7 32 38000H-3FFFFH 7 32 20000H-27FFFH

6 32 30000H-37FFFH 6 32 18000H-1FFFFH

5 32 28000H-2FFFFH 5 32 10000H-17FFFH

4 32 20000H-27FFFH 4 32 08000H-0FFFFH

3 32 18000H-1FFFFH 3 16 04000H-07FFFH

2 32 10000H-17FFFH 2 4 03000H-03FFFH

1 32 08000H-0FFFFH 1 4 02000H-02FFFH

0 32 00000H-07FFFH 0 8 00000H-01FFFH

Size

(KWord)

Address Range #

Bottom Boot Block Address

SST39VF801C/SST39LF801C

Size

(KWord)

Address Range

T2.25041

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Device Operation

Commands are used to initiate the memory operation functions of the device. Commands are written
to the device using standard microprocessor write sequences. A command is written by asserting WE#
low while keeping CE# low. The address bus is latched on the falling edge of WE# or CE#, whichever
occurs last. The data bus is latched on the rising edge of WE# or CE#, whichever occurs first.

The SST39VF801C/802C and SST39LF801C/802C also have the Auto Low Power mode which puts
the device in a near standby mode after data has been accessed with a valid Read operation. This
reduces the IDDactive read current from typically 5 mA to typically 3 µA. The Auto Low Power mode
reduces the typical IDDactive read current to the range of 2 mA/MHz of Read cycle time. The device
exits the Auto Low Power mode with any address transition or control signal transition used to initiate
another Read cycle, with no access time penalty. Note that the device does not enter Auto-Low Power
mode after power-up with CE# held steadily low, until the first address transition or CE# is driven high.

Read

The Read operation of the SST39VF801C/802C and SST39LF801C/802C is controlled by CE# and OE#,
both have to be low for the system to obtain data from the outputs. CE# is used for device selection.
When CE# is high, the chip is deselected and only standby power is consumed. OE# is the output con­trol and is used to gate data from the output pins. The data bus is in high impedance state when either
CE# or OE# is high. Refer to the Read cycle timing diagram for further details (Figure 6).

SST39VF801C / SST39VF802C / SST39LF801C / SST39LF802C

Data Sheet

Word-Program Operation

The SST39VF801C/802C and SST39LF801C/802C are programmed on a word-by-word basis. Before
programming, the sector where the word exists must be fully erased. The Program operation is accom­plished in three steps. The first step is the three-byte load sequence for Software Data Protection. The
second step is to load word address and word data. During the Word-Program operation, the
addresses are latched on the falling edge of either CE# or WE#, whichever occurs last. The data is
latched on the rising edge of either CE# or WE#, whichever occurs first. The third step is the internal
Program operation which is initiated after the rising edge of the fourth WE# or CE#, whichever occurs
first. The Program operation, once initiated, will be completed within 10 µs. See Figures 7 and 8 for
WE# and CE# controlled Program operation timing diagrams and Figure 22 for flowcharts. During the
Program operation, the only valid reads are Data# Polling and Toggle Bit. During the internal Program
operation, the host is free to perform additional tasks. Any commands issued during the internal Pro­gram operation are ignored. During the command sequence, WP# should be statically held high or low.

Sector/Block-Erase Operation

The Sector- (or Block-) Erase operation allows the system to erase the device on a sector-by-sector (or
block-by-block) basis. The SST39VF801C/802C and SST39LF801C/802C offer both Sector-Erase and
Block-Erase mode.

The sector architecture is based on a uniform sector size of 2 KWord. The Block-Erase mode is based
on non-uniform block sizes—fifteen 32 KWord, one 16 KWord, two 4 KWord, and one 8 KWord blocks.
See Figure 2 for top and bottom boot device block addresses. The Sector-Erase operation is initiated
by executing a six-byte command sequence with Sector-Erase command (50H) and sector address
(SA) in the last bus cycle. The Block-Erase operation is initiated by executing a six-byte command
sequence with Block-Erase command (30H) and block address (BA) in the last bus cycle. The sector
or block address is latched on the falling edge of the sixth WE# pulse, while the command (30H or
50H) is latched on the rising edge of the sixth WE# pulse. The internal Erase operation begins after the

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sixth WE# pulse. The End-of-Erase operation can be determined using either Data# Polling or Toggle
Bit methods. See Figures 12 and 13 for timing waveforms and Figure 26 for the flowchart. Any com­mands issued during the Sector- or Block-Erase operation are ignored. When WP# is low, any attempt
to Sector- (Block-) Erase the protected block will be ignored. During the command sequence, WP#
should be statically held high or low.

Erase-Suspend/Erase-Resume Commands

The Erase-Suspend operation temporarily suspends a Sector- or Block-Erase operation thus allowing
data to be read from any memory location, or program data into any sector/block that is not suspended
for an Erase operation. The operation is executed by issuing one byte command sequence with Erase­Suspend command (B0H). The device automatically enters read mode typically within 20 µs after the
Erase-Suspend command had been issued. Valid data can be read from any sector or block that is not
suspended from an Erase operation. Reading at address location within erase-suspended sectors/
blocks will output DQ2toggling and DQ6at ‘1’. While in Erase-Suspend mode, a Word-Program opera­tion is allowed except for the sector or block selected for Erase-Suspend.

To resume Sector-Erase or Block-Erase operation which has been suspended the system must issue
Erase Resume command. The operation is executed by issuing one byte command sequence with
Erase Resume command (30H) at any address in the last Byte sequence.

SST39VF801C / SST39VF802C / SST39LF801C / SST39LF802C

Data Sheet

Chip-Erase Operation

The SST39VF801C/802C and SST39LF801C/802C provide a Chip-Erase operation, which allows the
user to erase the entire memory array to the ‘1’ state. This is useful when the entire device must be
quickly erased.

The Chip-Erase operation is initiated by executing a six-byte command sequence with Chip-Erase
command (10H) at address 555H in the last byte sequence. The Erase operation begins with the rising
edge of the sixth WE# or CE#, whichever occurs first. During the Erase operation, the only valid read is
Toggle Bit or Data# Polling. See Table 7 for the command sequence, Figure 11 for timing diagram, and
Figure 26 for the flowchart. Any commands issued during the Chip-Erase operation are ignored. When
WP# is low, any attempt to Chip-Erase will be ignored. During the command sequence, WP# should
be statically held high or low.

Write Operation Status Detection

The SST39VF801C/802C and SST39LF801C/802C provide two software means to detect the comple­tion of a Write (Program or Erase) cycle, in order to optimize the system write cycle time. The software
detection includes two status bits: Data# Polling (DQ7) and Toggle Bit (DQ6). The End-of-Write detec­tion mode is enabled after the rising edge of WE#, which initiates the internal Program or Erase opera­tion.

The actual completion of the nonvolatile write is asynchronous with the system; therefore, either a
Data# Polling or Toggle Bit read may be simultaneous with the completion of the write cycle. If this
occurs, the system may possibly get an erroneous result, i.e., valid data may appear to conflict with
either DQ7or DQ6. In order to prevent spurious rejection, if an erroneous result occurs, the software
routine should include a loop to read the accessed location an additional two (2) times. If both reads
are valid, then the device has completed the Write cycle, otherwise the rejection is valid.

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Ready/Busy# (RY/BY#)

The devices include a Ready/Busy# (RY/BY#) output signal. RY/BY# is an open drain output pin that
indicates whether an Erase or Program operation is in progress. Since RY/BY# is an open drain out­put, it allows several devices to be tied in parallel to VDDvia an external pull-up resistor. After the rising
edge of the final WE# pulse in the command sequence, the RY/BY# status is valid.

When RY/BY# is actively pulled low, it indicates that an Erase or Program operation is in progress.
When RY/BY# is high (Ready), the devices may be read or left in standby mode.

Data# Polling (DQ7)

When the SST39VF801C/802C and SST39LF801C/802C are in the internal Program operation, any
attempt to read DQ7will produce the complement of the true data. Once the Program operation is
completed, DQ7will produce true data. Note that even though DQ7may have valid data immediately follow­ing the completion of an internal Write operation, the remaining data outputs may still be invalid: valid data on
the entire data bus will appear in subsequent successive Read cycles after an interval of 1 µs. During internal
Erase operation, any attempt to read DQ7will produce a ‘0’. Once the internal Erase operation is com­pleted, DQ7will produce a ‘1’. The Data# Polling is valid after the rising edge of fourth WE# (or CE#)
pulse for Program operation. For Sector-, Block- or Chip-Erase, the Data# Polling is valid after the ris­ing edge of sixth WE# (or CE#) pulse. See Figure 9 for Data# Polling timing diagram and Figure 23 for
a flowchart.

SST39VF801C / SST39VF802C / SST39LF801C / SST39LF802C

Data Sheet

Toggle Bits (DQ6 and DQ2)

During the internal Program or Erase operation, any consecutive attempts to read DQ6will produce
alternating ‘1’s and ‘0’s, i.e., toggling between 1 and 0. When the internal Program or Erase operation
is completed, the DQ6bit will stop toggling. The device is then ready for the next operation. For Sector­, Block-, or Chip-Erase, the toggle bit (DQ6) is valid after the rising edge of sixth WE# (or CE#) pulse.
DQ6will be set to ‘1’ if a Read operation is attempted on an Erase-Suspended Sector/Block. If Pro­gram operation is initiated in a sector/block not selected in Erase-Suspend mode, DQ6will toggle.

An additional Toggle Bit is available on DQ2, which can be used in conjunction with DQ6to check
whether a particular sector is being actively erased or erase-suspended. Table 3 shows detailed status
bits information. The Toggle Bit (DQ2) is valid after the rising edge of the last WE# (or CE#) pulse of
Write operation. See Figure 10 for Toggle Bit timing diagram and Figure 23 for a flowchart.

Table 3: Write Operation Status

Status DQ

Normal Operation Standard Program DQ

Standard Erase 0 Toggle Toggle 0

Erase-Suspend
Mode

Note: DQ7and DQ2require a valid address when reading status information.

Read from Erase-Sus­pended Sector/Block

Read from Non-Erase­Suspended Sector/Block

Program DQ

7

# Toggle No Toggle 0

7

1 1 Toggle 1

Data Data Data 1

# Toggle N/A 0

7

DQ

6

DQ

2

RY/BY#

T3.0 25041

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Data Protection

The SST39VF801C/802C and SST39LF801C/802C provide both hardware and software features to pro­tect nonvolatile data from inadvertent writes.

Hardware Data Protection

Noise/Glitch Protection: A WE# or CE# pulse of less than 5 ns will not initiate a write cycle.

VDDPower Up/Down Detection: The Write operation is inhibited when VDDis less than 1.5V.

Write Inhibit Mode: Forcing OE# low, CE# high, or WE# high will inhibit the Write operation. This pre­vents inadvertent writes during power-up or power-down.

Hardware Block Protection

The SST39VF802C/SST39LF802C support top hardware block protection, which protects the top 8
KWord block of the device. The SST39VF801C/SST39LF801C support bottom hardware block protec­tion, which protects the bottom 8KWord block of the device. The Boot Block address ranges are
described in Table 4. Program and Erase operations are prevented on the 8 KWord when WP# is low.
If WP# is left floating, it is internally held high via a pull-up resistor, and the Boot Block is unprotected,
enabling Program and Erase operations on that block.

SST39VF801C / SST39VF802C / SST39LF801C / SST39LF802C

Data Sheet

Table 4: Boot Block Address Ranges

Product Address Range

Bottom Boot Block

SST39VF801C/SST39LF801C 00000H - 01FFFH

Top Boot Block

SST39VF802C/SST39LF802C 7E000H - 7FFFFH

Hardware Reset (RST#)

The RST# pin provides a hardware method of resetting the device to read array data. When the RST#
pin is held low for at least T
no internal Program/Erase operation is in progress, a minimum period of T
is driven high before a valid Read can take place (see Figure 18).

The Erase or Program operation that has been interrupted needs to be re-initiated after the device
resumes normal operation mode to ensure data integrity.

any in-progress operation will terminate and return to Read mode. When

RP,

Software Data Protection (SDP)

The SST39VF801C/802C and SST39LF801C/802C provide the JEDEC approved Software Data Pro­tection scheme for all data alteration operations, i.e., Program and Erase. Any Program operation
requires the inclusion of the three-byte sequence. The three-byte load sequence is used to initiate the
Program operation, providing optimal protection from inadvertent Write operations, e.g., during the
system power-up or power-down. Any Erase operation requires the inclusion of six-byte sequence.
These devices are shipped with the Software Data Protection permanently enabled. See Table 7 for

is required after RST#

RHR

T4.0 25041

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the specific software command codes. During SDP command sequence, invalid commands will abort
the device to read mode within T
during any SDP command sequence.

Common Flash Memory Interface (CFI)

The SST39VF801C/802C and SST39LF801C/802C also contain the CFI information to describe the
characteristics of the device. In order to enter the CFI Query mode, the system writes a three-byte
sequence, same as product ID entry command with 98H (CFI Query command) to address 555H in
the last byte sequence. Additionally, the system can use the one-byte sequence with 55H on the
Address and 89H on the Data Bus to enter the CFI Query mode. Once the device enters the CFI
Query mode, the system can read CFI data at the addresses given in Tables 8 through 10. The system
must write the CFI Exit command to return to Read mode from the CFI Query mode.

Product Identification

The Product Identification mode identifies the devices as the SST39VF801C / SST39VF802C /
SST39LF801C / SST39LF802C, and manufacturer as SST. This mode may be accessed software
operations. Users may use the Software Product Identification operation to identify the part (i.e., using
the device ID) when using multiple manufacturers in the same socket. For details, see Table 7 for soft­ware operation, Figure 14 for the Software ID Entry and Read timing diagram and Figure 24 for the
Software ID Entry command sequence flowchart.

SST39VF801C / SST39VF802C / SST39LF801C / SST39LF802C

Data Sheet

The contents of DQ15-DQ8can be VILor VIH, but no other value,

RC.

Table 5: Product Identification

Manufacturer’s ID 0000H BFH

Device ID

SST39VF801C/SST39LF801C 0001H 233BH

SST39VF802C/SST39LF802C 0001H 233AH

Product Identification Mode Exit/CFI Mode Exit

In order to return to the standard Read mode, the Software Product Identification mode must be exited.
Exit is accomplished by issuing the Software ID Exit command sequence, which returns the device to
the Read mode. This command may also be used to reset the device to the Read mode after any inad­vertent transient condition that apparently causes the device to behave abnormally, e.g., not read cor­rectly. Please note that the Software ID Exit/CFI Exit command is ignored during an internal Program
or Erase operation. See Table 7 for software command codes, Figure 16 for timing waveform, and Fig­ure 25 for flowcharts.

Address Data

T5.2 25041

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Security ID

The SST39VF801C/802C and SST39LF801C/802C devices offer a 136 Word Security ID space. The
Secure ID space is divided into two segments—one factory programmed segment and one user pro­grammed segment. The first segment is programmed and locked at SST with a random 128-bit num­ber. The user segment, with a 128 word space, is left un-programmed for the customer to program as
desired.

To program the user segment of the Security ID, the user must use the Security ID Word-Program
command. To detect end-of-write for the SEC ID, read the toggle bits. Do not use Data# Polling. Once
this is complete, the Sec ID should be locked using the User Sec ID Program Lock-Out. This disables
any future corruption of this space. Note that regardless of whether or not the Sec ID is locked, neither
Sec ID segment can be erased.

The Secure ID space can be queried by executing a three-byte command sequence with Enter Sec ID
command (88H) at address 555H in the last byte sequence. To exit this mode, the Exit Sec ID com­mand should be executed. Refer to Table 7 for more details.

SST39VF801C / SST39VF802C / SST39LF801C / SST39LF802C

Data Sheet

©2011 Silicon Storage Technology, Inc. DS25041A 05/11

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