A
1 Mbit / 2 Mbit / 4 Mbit (x8) Multi-Purpose Flash
SST39LF010 / SST39LF020 / SST39LF040
Microchip Technology Company
The SST39LF010, SST39LF020, SST39LF040 and SST39VF010, SST39VF020,
SST39VF040 are 128K x8, 256K x8 and 5124K x8 CMOS Multi-Purpose Flash
(MPF) manufactured with SST’s proprietary, high performance CMOS SuperFlash
technology. The split-gate cell design and thick-oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. The
SST39LF010/020/040 devices write (Program or Erase) with a 3.0-3.6V power
supply. The SST39VF010/020/040 devices write with a 2.7-3.6V power supply.
The devices conform to JEDEC standard pinouts for x8 memories.
Features
• Organized as 128K x8 / 256K x8 / 512K x8
• Single Voltage Read and Write Operations
– 3.0-3.6V for SST39LF010/020/040
– 2.7-3.6V for SST39VF010/020/040
• Superior Reliability
– Endurance: 100,000 Cycles (typical)
– Greater than 100 years Data Retention
• Low Power Consumption
(typical values at 14 MHz)
– Active Current: 5 mA (typical)
– Standby Current: 1 µA (typical)
• Sector-Erase Capability
– Uniform 4 KByte sectors
SST39VF010 / SST39VF020 / SST39VF040
Data Sheet
• Fast Erase and Byte-Program:
– Sector-Erase Time: 18 ms (typical)
– Chip-Erase Time: 70 ms (typical)
– Byte-Program Time: 14 µs (typical)
– Chip Rewrite Time:
2 seconds (typical) for SST39LF/VF010
4 seconds (typical) for SST39LF/VF020
8 seconds (typical) for SST39LF/VF040
• Automatic Write Timing
– Internal VPPGeneration
• End-of-Write Detection
– Toggle Bit
– Data# Polling
• CMOS I/O Compatibility
• Fast Read Access Time:
– 45 ns for SST39LF010/020/040
– 55 ns for SST39LF020/040
– 70 ns for SST39VF010/020/040
• Latched Address and Data
• JEDEC Standard
– Flash EEPROM Pinouts and command sets
• Packages Available
– 32-lead PLCC
– 32-lead TSOP (8mm x 14mm)
– 48-ball TFBGA (6mm x 8mm)
– 34-ball WFBGA (4mm x 6mm) for 1M and 2M
• All devices are RoHS compliant
©2011 Silicon Storage Technology, Inc. DS25023A 08/11
www.microchip.com
1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash
A
SST39LF010 / SST39LF020 / SST39LF040
Microchip Technology Company
Product Description
The SST39LF010, SST39LF020, SST39LF040 and SST39VF010, SST39VF020, SST39VF040 are
128K x8, 256K x8 and 5124K x8 CMOS Multi-Purpose Flash (MPF) manufactured with SST’s proprietary, high performance CMOS SuperFlash technology. The split-gate cell design and thick-oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. The
SST39LF010/020/040 devices write (Program or Erase) with a 3.0-3.6V power supply. The
SST39VF010/020/040 devices write with a 2.7-3.6V power supply. The devices conform to JEDEC
standard pinouts for x8 memories.
Featuring high performance Byte-Program, the SST39LF010/020/040 and SST39VF010/020/040
devices provide a maximum Byte-Program time of 20 µsec. These devices use Toggle Bit or Data#
Polling to indicate the completion of Program operation. To protect against inadvertent write, they have
on-chip hardware and Software Data Protection schemes. Designed, manufactured, and tested for a
wide spectrum of applications, they are offered with a guaranteed typical endurance of 100,000 cycles.
Data retention is rated at greater than 100 years.
The SST39LF010/020/040 and SST39VF010/020/040 devices are suited for applications that require
convenient and economical updating of program, configuration, or data memory. For all system applications, they significantly improves performance and reliability, while lowering power consumption.
They inherently use less energy during Erase and Program than alternative flash technologies. The
total energy consumed is a function of the applied voltage, current, and time of application. Since for
any given voltage range, the SuperFlash technology uses less current to program and has a shorter
erase time, the total energy consumed during any Erase or Program operation is less than alternative
flash technologies. These devices also improve flexibility while lowering the cost for program, data, and
configuration storage applications.
SST39VF010 / SST39VF020 / SST39VF040
Data Sheet
The SuperFlash technology provides fixed Erase and Program times, independent of the number of
Erase/Program cycles that have occurred. Therefore the system software or hardware does not have
to be modified or de-rated as is necessary with alternative flash technologies, whose Erase and Program times increase with accumulated Erase/Program cycles.
To meet surface mount requirements, the SST39LF010/020/040 and SST39VF010/020/040 devices
are offered in 32-lead PLCC and 32-lead TSOP packages. The SST39LF/VF010 and SST39LF/VF020
are also offered in a 48-ball TFBGA package. See Figures 2, 3, 4, and 5 for pin assignments.
©2011 Silicon Storage Technology, Inc. DS25023A 08/11
2
1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash
A
SST39LF010 / SST39LF020 / SST39LF040
Microchip Technology Company
Block Diagram
Figure 1: Functional Block Diagram
Memory Address
SST39VF010 / SST39VF020 / SST39VF040
Address Buffers Latches
CE#
OE#
WE#
Control Logic
X-Decoder
SuperFlash
Memory
Y-Decoder
I/O Buffers and Data Latches
DQ
-DQ
7
0
Data Sheet
1150 B1.1
©2011 Silicon Storage Technology, Inc. DS25023A 08/11
3
1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash
A
SST39LF010 / SST39LF020 / SST39LF040
Microchip Technology Company
Pin Assignments
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
SST39VF010 / SST39VF020 / SST39VF040
Data Sheet
A12
A15
A16
A18
VDDWE#
A17
A12
A15
A16NCVDDWE#
A12
A15
A16NCVDDWE#
SST39LF/VF010SST39LF/VF020SST39LF/VF040 SST39LF/VF010 SST39LF/VF020 SST39LF/VF040
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
4 3 21323130
5
6
7
8
32-lead PLCC
9
10
11
12
13
Top View
14 15 16 17 18 19 20
A17
NC
29
28
27
26
25
24
23
22
21
A14
A13
A8
A9
A11
OE#
A10
CE#
DQ7
A14
A13
A8
A9
A11
OE#
A10
CE#
DQ7
A14
A13
A8
A9
A11
OE#
A10
CE#
DQ7
V
DQ1
DQ2
SST39LF/VF010SST39LF/VF020SST39LF/VF040 SST39LF/VF010 SST39LF/VF020 SST39LF/VF040
V
DQ1
DQ2
V
DQ1
DQ2
Figure 2: Pin Assignments for 32-lead PLCC
SS
SS
SS
DQ3
DQ3
DQ3
DQ4
DQ4
DQ4
DQ5
DQ5
DQ5
1150 32-plcc NH P4.4
DQ6
DQ6
DQ6
©2011 Silicon Storage Technology, Inc. DS25023A 08/11
4
1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash
A
SST39LF010 / SST39LF020 / SST39LF040
Microchip Technology Company
Figure 3: Pin Assignments for 32-lead TSOP (8mm x 14mm)
A11
A13
A14
A17
WE#
V
DD
A18
A16
A15
A12
SST39VF010 / SST39VF020 / SST39VF040
Data Sheet
SST39LF/VF010SST39LF/VF020SST39LF/VF040 SST39LF/VF010 SST39LF/VF020 SST39LF/VF040
A9
A8
A7
A6
A5
A4
A11
A13
A14
A17
WE#
V
DD
NC
A16
A15
A12
A9
A8
A7
A6
A5
A4
TOP VIEW (balls facing down)
A11
A13
A14
NC
WE#
V
DD
NC
A16
A15
A12
A9
A8
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
SST39LF/VF010
Standard Pinout
Top View
Die Up
OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
V
DQ2
DQ1
DQ0
A0
A1
A2
A3
1150 32-tsop WH P1.1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
TOP VIEW (balls facing down)
SST39LF/VF020
SS
OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
V
DQ2
DQ1
DQ0
A0
A1
A2
A3
SS
OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
V
DQ2
DQ1
DQ0
A0
A1
A2
A3
SS
6
5
4
3
2
1
A14
A9
WE#
NC
A7
A3
A13
A8
NC
NC
NC
A4
A15
A11
NC
NC
A6
A2
A16
A12
NC
NC
A5
A1
NC
NC
DQ5
DQ2
DQ0
A0
NC
A10
NC
DQ3
NC
CE#
NC
DQ6
V
DD
V
DD
NC
OE#
V
SS
DQ7
DQ4
NC
DQ1
V
SS
1150 48-tfbga B3K P2.0
ABCDEFGH
6
5
4
3
2
1
A14
A9
WE#
NC
A7
A3
A13
A8
NC
NC
NC
A4
A15
A11
NC
NC
A6
A2
A16
A12
NC
NC
A5
A1
A17
NC
DQ5
DQ2
DQ0
A0
NC
A10
NC
DQ3
NC
CE#
NC
DQ6
V
DD
V
DD
NC
OE#
V
SS
DQ7
DQ4
NC
DQ1
V
SS
1150 48-tfbga B3K P3.0
ABCDEFGH
TOP VIEW (balls facing down)
SST39LF/VF040
6
5
4
3
2
1
A14
A9
WE#
NC
A7
A3
A13
A8
NC
NC
A18
A4
A15
A11
NC
NC
A6
A2
A16
A12
NC
NC
A5
A1
A17
NC
DQ5
DQ2
DQ0
A0
NC
A10
NC
DQ3
NC
CE#
NC
DQ6
V
DD
V
DD
NC
OE#
V
SS
DQ7
DQ4
NC
DQ1
V
SS
1150 48-tfbga B3K P4.0
ABCDEFGH
Figure 4: Pin Assignment for 48-ball TFBGA (6mm x 8mm) for 1 Mbit, 2 Mbit, and 4 Mbit
©2011 Silicon Storage Technology, Inc. DS25023A 08/11
5
1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash
A
SST39LF010 / SST39LF020 / SST39LF040
Microchip Technology Company
Figure 5: Pin Assignment for 34-ball WFBGA (4mm x 6mm) for 1 Mbit and 2 Mbit
Table 1: Pin Description
Symbol Pin Name Functions
A
DQ
CE# Chip Enable To activate the device when CE# is low.
OE# Output Enable To gate the data output buffers.
WE# Write Enable To control the Write operations.
V
V
NC No Connection Unconnected pins.
SST39VF010 / SST39VF020 / SST39VF040
Data Sheet
TOP VIEW (balls facing down)
6
A2
5
A1
4
A0
3
CE#
2
V
SS
1
1
-A
MS
Address Inputs To provide memory addresses. During Sector-Erase AMS-A12address lines will
0
select the sector. During Block-Erase A
-DQ0Data Input/output To output data during Read cycles and receive input data during Write cycles.
7
Data is internally latched during a Write cycle.
The outputs are in tri-state when OE# or CE# is high.
DD
SS
1. AMS= Most significant address
Power Supply To provide power supply voltage: 3.0-3.6V for SST39LF010/020/040
Ground
AMS=A16for SST39LF/VF010, A17for SST39LF/VF020, and A18for SST39LF/VF040
A8
A9
A17
V
A16
A12
A11A4NC1
A14
A13
WE#
DD
A18
A15
A7
A6
A5
NC2
OE#A3A10
DQ7
A0
A2
CE#
DQ5
DQ3
DQ2
DQ0
A1
DQ6
DQ4
V
DQ1
AB C D E F G H J
Note: For SST39LF020, ball B3 is No Connect
For SST39LF010, balls B3 and A5 are No Connect
MS-A16
2.7-3.6V for SST39VF010/020/040
SS
1150 34-wfbga MM P5.0
address lines will select the block.
T1.1 25023
©2011 Silicon Storage Technology, Inc. DS25023A 08/11
6
1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash
A
SST39LF010 / SST39LF020 / SST39LF040
Microchip Technology Company
Device Operation
Commands are used to initiate the memory operation functions of the device. Commands are written
to the device using standard microprocessor write sequences. A command is written by asserting WE#
low while keeping CE# low. The address bus is latched on the falling edge of WE# or CE#, whichever
occurs last. The data bus is latched on the rising edge of WE# or CE#, whichever occurs first.
Read
The Read operation of the SST39LF010/020/040 and SST39VF010/020/040 devices are controlled by
CE# and OE#, both have to be low for the system to obtain data from the outputs. CE# is used for
device selection. When CE# is high, the chip is deselected and only standby power is consumed. OE#
is the output control and is used to gate data from the output pins. The data bus is in high impedance
state when either CE# or OE# is high. Refer to the Read cycle timing diagram for further details (Figure
6).
Byte-Program Operation
The SST39LF010/020/040 and SST39VF010/020/040 are programmed on a byte-by-byte basis.
Before programming, the sector where the byte exists must be fully erased. The Program operation is
accomplished in three steps. The first step is the three-byte load sequence for Software Data Protection. The second step is to load byte address and byte data. During the Byte-Program operation, the
addresses are latched on the falling edge of either CE# or WE#, whichever occurs last. The data is
latched on the rising edge of either CE# or WE#, whichever occurs first. The third step is the internal
Program operation which is initiated after the rising edge of the fourth WE# or CE#, whichever occurs
first. The Program operation, once initiated, will be completed, within 20 µs. See Figures 7 and 8 for
WE# and CE# controlled Program operation timing diagrams and Figure 17 for flowcharts. During the
Program operation, the only valid reads are Data# Polling and Toggle Bit. During the internal Program
operation, the host is free to perform additional tasks. Any commands written during the internal Program operation will be ignored.
SST39VF010 / SST39VF020 / SST39VF040
Data Sheet
Sector-Erase Operation
The Sector-Erase operation allows the system to erase the device on a sector-by-sector basis. The
sector architecture is based on uniform sector size of 4 KByte. The Sector-Erase operation is initiated
by executing a six-byte command sequence with Sector-Erase command (30H) and sector address
(SA) in the last bus cycle. The sector address is latched on the falling edge of the sixth WE# pulse,
while the command (30H) is latched on the rising edge of the sixth WE# pulse. The internal Erase
operation begins after the sixth WE# pulse. The End-of-Erase can be determined using either Data#
Polling or Toggle Bit methods. See Figure 11 for timing waveforms. Any commands written during the
Sector-Erase operation will be ignored.
Chip-Erase Operation
The SST39LF010/020/040 and SST39VF010/020/040 devices provide a Chip-Erase operation, which
allows the user to erase the entire memory array to the ‘1’s state. This is useful when the entire device
must be quickly erased.
The Chip-Erase operation is initiated by executing a six- byte Software Data Protection command
sequence with Chip-Erase command (10H) with address 5555H in the last byte sequence. The internal
Erase operation begins with the rising edge of the sixth WE# or CE#, whichever occurs first. During the
©2011 Silicon Storage Technology, Inc. DS25023A 08/11
7
1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash
A
SST39LF010 / SST39LF020 / SST39LF040
Microchip Technology Company
internal Erase operation, the only valid read is Toggle Bit or Data# Polling. See Table 4 for the command sequence, Figure 12 for timing diagram, and Figure 20 for the flowchart. Any commands written
during the Chip-Erase operation will be ignored.
Write Operation Status Detection
The SST39LF010/020/040 and SST39VF010/020/040 devices provide two software means to detect
the completion of a Write (Program or Erase) cycle, in order to optimize the system write cycle time.
The software detection includes two status bits: Data# Polling (DQ7) and Toggle Bit (DQ6). The End-ofWrite detection mode is enabled after the rising edge of WE# which initiates the internal Program or
Erase operation.
The actual completion of the nonvolatile write is asynchronous with the system; therefore, either a
Data# Polling or Toggle Bit read may be simultaneous with the completion of the Write cycle. If this
occurs, the system may possibly get an erroneous result, i.e., valid data may appear to conflict with
either DQ7or DQ6. In order to prevent spurious rejection, if an erroneous result occurs, the software
routine should include a loop to read the accessed location an additional two (2) times. If both reads
are valid, then the device has completed the Write cycle, otherwise the rejection is valid.
SST39VF010 / SST39VF020 / SST39VF040
Data Sheet
©2011 Silicon Storage Technology, Inc. DS25023A 08/11
8
1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash
A
SST39LF010 / SST39LF020 / SST39LF040
Microchip Technology Company
Data# Polling (DQ7)
When the SST39LF010/020/040 and SST39VF010/020/040 are in the internal Program operation, any
attempt to read DQ7will produce the complement of the true data. Once the Program operation is
completed, DQ7will produce true data. Note that even though DQ7may have valid data immediately
following completion of an internal Write operation, the remaining data outputs may still be invalid: valid
data on the entire data bus will appear in subsequent successive Read cycles after an interval of 1 µs.
During internal Erase operation, any attempt to read DQ7will produce a “0”. Once the internal Erase
operation is completed, DQ7will produce a “1”. The Data# Polling is valid after the rising edge of fourth
WE# (or CE#) pulse for Program operation. For Sector- or Chip-Erase, the Data# Polling is valid after
the rising edge of sixth WE# (or CE#) pulse. See Figure 9 for Data# Polling timing diagram and Figure
18 for a flowchart.
Toggle Bit (DQ6)
During the internal Program or Erase operation, any consecutive attempts to read DQ6will produce
alternating ‘0’s and ‘1’s, i.e., toggling between 0 and 1. When the internal Program or Erase operation
is completed, the toggling will stop. The device is then ready for the next operation. The Toggle Bit is
valid after the rising edge of fourth WE# (or CE#) pulse for Program operation. For Sector- or ChipErase, the Toggle Bit is valid after the rising edge of sixth WE# (or CE#) pulse. See Figure 10 for Toggle Bit timing diagram and Figure 18 for a flowchart.
SST39VF010 / SST39VF020 / SST39VF040
Data Sheet
Data Protection
The SST39LF010/020/040 and SST39VF010/020/040 provide both hardware and software features to
protect nonvolatile data from inadvertent writes.
Hardware Data Protection
Noise/Glitch Protection: A WE# or CE# pulse of less than 5 ns will not initiate a Write cycle.
VDDPower Up/Down Detection: The Write operation is inhibited when VDDis less than 1.5V.
Write Inhibit Mode: Forcing OE# low, CE# high, or WE# high will inhibit the Write operation. This prevents inadvertent writes during power-up or power-down.
©2011 Silicon Storage Technology, Inc. DS25023A 08/11
9
1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash
A
SST39LF010 / SST39LF020 / SST39LF040
Microchip Technology Company
Software Data Protection (SDP)
The SST39LF010/020/040 and SST39VF010/020/040 provide the JEDEC approved Software Data
Protection scheme for all data alteration operation, i.e., Program and Erase. Any Program operation
requires the inclusion of a series of three-byte sequence. The three-byte load sequence is used to initiate the Program operation, providing optimal protection from inadvertent Write operations, e.g., during the system power-up or power-down. Any Erase operation requires the inclusion of six-byte load
sequence. These devices are shipped with the Software Data Protection permanently enabled. See
Table 4 for the specific software command codes. During SDP command sequence, invalid commands
will abort the device to read mode, within T
Product Identification
The Product Identification mode identifies the devices as the SST39LF/VF010, SST39LF/VF020, and
SST39LF/VF040 and manufacturer as SST. This mode may be accessed by software operations.
Users may use the Software Product Identification operation to identify the part (i.e., using the device
ID) when using multiple manufacturers in the same socket. For details, see Table 4 for software operation, Figure 13 for the Software ID Entry and Read timing diagram, and Figure 19 for the Software ID
entry command sequence flowchart.
Table 2: Product Identification
Manufacturer’s ID 0000H BFH
Device ID
SST39VF010 / SST39VF020 / SST39VF040
Data Sheet
RC.
Address Data
SST39LF/VF010 0001H D5H
SST39LF/VF020 0001H D6H
SST39LF/VF040 0001H D7H
T2.1 25023
Product Identification Mode Exit/Reset
In order to return to the standard Read mode, the Software Product Identification mode must be exited.
Exit is accomplished by issuing the Software ID Exit command sequence, which returns the device to
the Read operation. Please note that the Software ID Exit command is ignored during an internal Program or Erase operation. See Table 4 for software command codes, Figure 14 for timing waveform,
and Figure 19 for a flowchart.
©2011 Silicon Storage Technology, Inc. DS25023A 08/11
10