Datasheet SST25PF020B Datasheet

SST25PF020B

2 Mbit 2.3-3.6V SPI Serial Flash

Features

• Single Voltage Read and Write Operations

- 2.3-3.6V

• Serial Interface Architecture

- SPI Compatible: Mode 0 and Mode 3

• High Speed Clock Frequency

- 80 MHz (2.7-3.6V operation)

- 50 MHz (2.3-2.7V operation)

• Superior Reliability

- Endurance: 100,000 Cycles (typical)

- Greater than 100 years Data Retention

• Low Power Consumption:

- Active Read Current: 10 mA (typical)

- Standby Cu rre nt : 5 µA (typ i c a l)

• Flexible Erase Capability

- Uniform 4 KByte sectors

- Uniform 32 KByte overlay blocks

- Uniform 64 KByte overlay blocks

• Fast Erase and Byte-Program:

- Chip-Erase Time: 35 ms (typical)

- Sector-/Block-Erase Time: 18 ms (typical)

- Byte-Program Time: 7 µs (typical)

• Auto Address Increment (AAI) Programming

- Decrease total chip programming time over
Byte-Program operations

• End-of-Write Detection

- Software polling the BUSY bit in Status Register

- Busy Status readout on SO pin in AAI Mode

• Hold Pin (HOLD#)

- Suspends a serial sequence to the memory
without deselecting the device

• Write Protection (WP#)

- Enables/Disables the Lock-Down function of
the status register

• Software Write Protection

- Write protection through Block-Protection bits
in status register

• Temperature Range

- Commercial: 0°C to +70°C

• Packages Available

- 8-lead SOIC (150 mils)

- 8-contact WSON (6mm x 5mm)

- 8-contact USON (3mm x 2mm)

• All non-Pb (lead-free) devices are RoHS compliant

Product Description

The 25 series Serial Flash family features a four-wire,
SPI-compatible interface that allows for a low pin-count
package which occupies less board space and ulti­mately lowers total system costs. The SST25PF020B
devices are enhanced with improved operating fre­quency and even lower power consumption.
SST25PF020B SPI serial flash memories are manu­factured with proprietary, high-performance CMOS
SuperFlash technology. The split-gate cell design and
thick-oxide tunneling injector attain better reliability and
manufacturability compared with alternate approaches.

The SST25PF020B devices significantly improve per­formance and reliability, while lowering power con­sumption. The devices write (Program or Erase) with a
single power supply of 2.3-3.6V for SST25PF020B.
The total energy consumed is a function of the applied
voltage, current, and time of application. Since for any
given voltage range, the SuperFlash technology uses
less current to program and has a shorter erase time,
the total energy consumed during any Erase or Pro­gram operation is less than alternative flash memory
technologies.

The SST25PF020B device is offered in 8-lead SOIC
(150 mils), 8-contact WSON (6mm x 5mm), and 8-con­tact USON (3mm x 2mm) packages. See Figure 2-1 for
pin assignments.

 2012 Microchip Technology Inc. DS25135A-page 1

SST25PF020B

1.0 FUNCTIONAL BLOCK DIAGRAM

Address

Buffers

and

Latches

Control Logic

X - Decoder

SuperFlash

Memory

Y - Decoder

I/O Buffers

and

Data Latches

Serial Interface

CE#

FIGURE 1-1: FUNCTIONAL BLOCK DIAGRAM

SCK SI SO WP# HOLD#

25135 B1.0

DS25135A-page 2  2012 Microchip Technology Inc.

2.0 PIN DESCRIPTION

1

2

3

4

8

7

6

5

CE#

SO

WP#

V

SS

V

DD

HOLD#

SCK

SI

T op Vie w

25135 08-soic S2A P1.0

8-Lead SOIC

1

2

3

4

8

7

6

5

CE#

SO

WP#

V

SS

T op View

V

DD

HOLD#

SCK

SI

25135 08-wson QA P2.0

8-Contact WSON

1

2

3

4

8

7

6

5

CE#

SO

WP#

V

SS

Top View

V

DD

HOLD#

SCK

SI

25135 08-uson Q3A P1.0

8-Contact USON

SST25PF020B

FIGURE 2-1: PIN ASSIGNMENTS

TABLE 2-1: PIN DESCRIPTION

Symbol Pin Name Functions

SCK Serial Clock To provide the timing of the serial interface.

Commands, addresses, or input data are latched on the rising edge of the clock
input, while output data is shifted out on the falling edge of the clock input.

SI Serial Data Input To transfer commands, addresses, or data serially into the device.

Inputs are latched on the rising edge of the serial clock.

SO Serial Data Output To transfer data serially out of the device.

Data is shifted out on the falling edge of the serial clock.
Outputs Flash busy status during AAI Programming when reconfigured as RY/BY#
pin. See “Hardware End-of-Write Detection” on page 11 for details.

CE# Chip Enable The device is enabled by a high to low transition on CE#. CE# must remain low for

the duration of any command sequence.
WP# Write Protect The Write Protect (WP#) pin is used to enable/disable BPL bit in the status register.
HOLD# Hold To temporarily stop serial communication with SPI flash memory without resetting

the device.
V

DD

V

SS

 2012 Microchip Technology Inc. DS25135A-page 3

Power Supply To provide power supply voltage: 2.3-3.6V for SST25PF020B

Ground

SST25PF020B

25135 SPIprot.0

MODE 3

SCK

SI

SO

CE#

MODE 3

DON'T CARE

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

MODE 0MODE 0

HIGH IMPEDANCE

MSB

MSB

3.0 MEMORY ORGANIZATION

The SST25PF020B S u p e r Fl a s h memory array is orga­nized in uniform 4 KByte erasable sectors with 32
KByte overlay blocks and 64 KByte overlay erasable
blocks.

4.0 DEVICE OPERATION

The SST25 PF 020 B is accessed through the SPI (Serial
Peripheral Interface) bus compatible protocol. The SPI
bus consist of four control lines; Chip Enable (CE#) is

used to select the device, and data is accessed through
the Serial Data Input (SI), Serial Data Output (SO), and
Serial Clock (SCK).

The SST25PF020B supports both Mode 0 (0,0) and
Mode 3 (1,1) of SPI bus operations. The difference
between the two modes, as shown in Figure 4-1, is the
state of the SCK signal when the bus master is in
Standby mode and no data is being transferred. The
SCK signal is low for Mode 0 and SCK signal is high for
Mode 3. For both modes, the Serial Data In (SI) is sam­pled at the rising edge of the SCK clock signal and the
Serial Data Output (SO) is driven after the falling edge
of the SCK clock signal.

FIGURE 4-1: SPI PROTOCOL

4.1 Hold Operation

The HOLD# pin is used to pause a serial sequence
underway with the SPI flash memory without resetting
the clocking sequence. To activate the HOLD# mode,
CE# must be in active low state. The HOLD# mode
begins when the SCK active low state coincides with
the falling edge of the HOLD# signal. The HOLD mode
ends when the HOLD# signal’s rising edge coincides
with the SCK active low state.

If the falling edge of the HOLD# signal does not coin­cide with the SCK active low state, then the device
enters Hold mode when the SCK next reaches the
active low state. Similarly, if the rising edge of the
HOLD# signal does not coincide with the SCK active

SCK

HOLD#

Active Hold Active Hold Active

low state, then the device exits in Hold mode when the
SCK next reaches the active low state. See Figure 4-2
for Hold Condition waveform.

Once the device enters Hold mode, SO will be in high­impedance state while SI and SCK can be V

IL

or V

IH.

If CE# is driven high during a Hold condition, the device
returns to Standby mode. As long as HOLD# signal is
low, the memory remains in the Hold condition. To
resume communication with the device, HOLD# must
be driven active high, and CE# must be driven active
low. See Figure 4-2 for Hold timing.

25135 HoldCond.0

FIGURE 4-2: HOLD CONDITION WAVEFORM

DS25135A-page 4  2012 Microchip Technology Inc.

4.2 Write Protection

SST25PF020B

SST2 5 PF020B provides soft ware Wr ite protection. The
Write Protect pin (WP#) enables or disables the lock­down function of the status register. The Block-Protec­tion bits (BP1, BP0, and BPL) in the status register, and
the Top/Bottom Sector Protection Status bits (TSP and
BSP) in Status Register 1, provide Write protection to
the memory array and the status register. See Table 4-

4 for the Block-Protection description.

4.2.1 WRITE PROTECT PIN (WP#)

The Write Protect (WP#) pin enables the lock-down
function of the BPL bit (bit 7) in the status register.
When WP# is driven low, the execution of the Write­Status-Register (WRSR) instruction is determined by
the value of the BPL bit (see Table 4-1). When WP# is
high, the lock-down function of the BPL bit is disabled.

TABLE 4-1: CONDITIONS TO EXECUTE WRITE-STATUS-REGISTER (WRSR) INSTRUCTION

WP# BPL Execute WRSR Instruction

L1Not Allowed
L0Allowed

HXAllowed

4.3 Status Register

The software status register provides status on
whether the flash memory array is available for any
Read or Write operation, whether the device is Write
enabled, and the state of the Memory Write protection.

TABLE 4-2: SOFTWARE STATUS REGISTER

Bit Name Function

0 BUSY 1 = Internal Write operation is in progress

0 = No internal Write operation is in progress

1 WEL 1 = Device is memory Write enabled

0 = Device is not memory Write enabled

2 BP0 Indicates current level of block write protection (See Table 4-4) 1R/W
3 BP1 Indicates current level of block write protection (See Table 4-4) 1R/W

4:5 RES Reserved for future use 0N/A

6 AAI Auto Address Increment Programming status

1 = AAI programming mode
0 = Byte-Program mode

7 BPL 1 = BP1, BP0 are read-only bits

0 = BP1, BP0 are read/writable

During an internal Erase or Program operation, the sta­tus register may be read only to determine the comple­tion of an operation in progress. Table 4-2 describes
the function of each bit in the software status register.

Default at
Power-up Read/Write

0R

0R

0R

0R/W

 2012 Microchip Technology Inc. DS25135A-page 5

SST25PF020B

4.4 Software Status Register 1

The Software St atus Register 1 is an additional register that
contains Top Sector and Bottom Sector Protection bits.
These register bits are read/writable and determine the lock

and unlock status of the top and bottom sectors. Table 4-3
describes the function of each bit in the Software Status
Register 1.

TABLE 4-3: SOFTWARE STATUS REGISTER 1

Default at

Bit Name Function

0:1 RES Reserved for future use 0N/A

2 TSP Top Sector Protection status

1 = Indicates highest sector is write locked
0 = Indicates highest sector is Write accessible

3 BSP Bottom Sector Protection status

1 = Indicates lowest sector is write locked
0 = Indicates lowest sector is Write accessible

4:7 RES Reserved for future use 0N/A

4.4.1 BUSY

The Busy bit determines whether there is an internal
Erase or Program operation in progress. A “1” for the
Busy bit indicates the device is busy with an operation
in progress. A “0” indicates the device is ready for the
next valid operation.

4.4.2 WRITE ENABLE LATCH (WEL)

The Write-Enable-Latch bit indicates the status of the
internal memory Write Enable Latch. If the Write­Enable-Latch bit is set to “1”, it indicates the device is
Write enabled. If the bit is set to “0” (reset), it indicates
the device is not Write enabled and does not accept
any memory Write (Program/Erase) commands. The
Write-Enable-Latch bit is automatically reset under the
following conditions:

• Power-up

• Write-Disable (WRDI) instruction completion

• Byte-Program instruction completion

• Auto Address Increment (AAI) programming is
completed or reached its highest unprotected

memory address

• Sector-Erase instruction completion

• Block-Erase instruction completion

• Chip-Erase instruction completion

• Write-Status-Register instruction completion

4.4.3 AUTO ADDRESS INCREMENT (AAI)

The Auto Address Increment Programming-Status bit
provides status on whether the device is in AAI pro­gramming mode or Byte-Program mode. The default at
power up is Byte-Program mode.

4.4.4 BLOCK PROTECTION (BP1, BP0)

The Block-Protection (BP1, BP0) bits define the size of
the memory area, as defined in T able 4-4, to be software
protected against any memory Write (Program or Erase)
operation. The Write-Status-Register (WRSR) instruc­tion is used to program the BP1 and BP0 bits as long as
WP# is high or the Block-Protect-Lock (BPL) bit is 0.
Chip-Erase can only be executed if Block-Protection bits
are all 0. After power-up, BP1 and BP0 are set to 1.

Power-up Read/Write

0R/W

0R/W

TABLE 4-4: SOFTWARE STATUS REGISTER BLOCK PROTECTION FOR SST25PF020B

Status Register Bit

Protection Level

000None
1 (1/4 Memory Array) 0 1 030000H-03FFFFH
1 (1/2 Memory Array) 1 0 020000H-03FFFFH
1 (Full Memory Array) 1 1 000000H-03FFFFH

1. X = Don’t Care (RESERVED) default is ‘0’

2. Default at power-up for BP1 and BP0 is ‘11’. (All Blocks Protected)

DS25135A-page 6  2012 Microchip Technology Inc.

BP1 BP0 2 Mbit

2

Protected Memory Address

1

4.4.5 BLOCK PROTECTION LOCK-DOWN
(BPL)

WP# pin driven low (VIL), enables the Block-Protection­Lock-Down (BPL) bit. When BPL is set to 1, it prevents
any further alteration of the BPL, BP1, and BP0 bits of
the status register and BSP and TSP of St atus Register

1. When the WP# pin is driven high (V

has no effect and its value is “Don’t Care”. After power­up, the BPL bit is reset to 0.

), the BPL bit

IH

4.4.6 TOP-SECTOR PROTECTION/
BOTTOM-SECTOR PROTECTION

The Top-Sector Protection (TSP) and Bottom-Sector
Protection (BSP) bits independently indicate whether
the highest and lowest sector locations are Write
locked or Write accessible. When TSP or BSP is set to
‘1’, the respective sector is Write locked; when set to ‘0’
the respective sector is Write accessible. If TSP or BSP
is set to '1' and if the top or bottom sector is within the
boundary of the target address range of the program or
erase instruction, the initiated instruction (Byte-Pro­gram, AAI-Word Program, Sector-Erase, Block-Erase,
and Chip-Erase) will not be executed. Upon power-up,
the TSP and BSP bits are automatically reset to ‘0’.

SST25PF020B

 2012 Microchip Technology Inc. DS25135A-page 7

SST25PF020B

4.5 Instructions

Instructions are used to read, write (Erase and Pro­gram), and configure the SST25PF020B. The instruc­tion bus cycles are 8 bits each for commands (Op
Code), data, and addresses. Prior to executing any
Byte-Program, Auto Address Increment (AAI) program­ming, Sector-Erase, Block-Erase, Write-Status-Regis­ter, or Chip-Erase instructions, the Write-Enable
(WREN) instruction must be executed first. The com­plete list of instructions is provided in Table 4-5. All
instructions are synchronized off a high to low transition

SCK starting with the most significant bit. CE# must be
driven low before an instruction is entered and must be
driven high after the last bit of the instruction has been
shifted in (except for Read, Read-ID, and Read-Status­Register instructions). Any low to high transition on
CE#, before receiving the last bit of an instruction bus
cycle, will terminate the instruction in progress and
return the device to standby mode. Instruction com­mands (Op Code), addresses, and data are all input
from the most significant bit (MSB) first.

of CE#. Inputs will be accepted on the rising edge of

TABLE 4-5: DEVICE OPERATION INSTRUCTIONS

Address

Cycle(s)

Instruction Description Op Code Cycle

1

Read Read Memory 0000 0011b (03H) 301 to ∞
High-Speed Read Read Memory at higher speed 0000 1011b (0BH) 311 to ∞
4 KByte Sector-

3

Erase
32 KByte Block-

4

Erase
64 KByte Block-

5

Erase
Chip-Erase Erase Full Memory Array 0110 0000b (60H) or

Erase 4 KByte of memory array 0010 0000b (20H) 300

Erase 32 KByte block of memory

0101 0010b (52H) 300

array
Erase 64 KByte block of memory

1101 1000b (D8H) 300

array

000

1100 0111b (C7H)
Byte-Program To Program One Data Byte 0000 0010b (02H) 301
AAI-Word-Program

6

Auto Address Increment Program-

1010 1101b (ADH) 302 to ∞

ming

7

RDSR

Read-Status-Register 0000 0101b (05H) 001 to ∞
RDSR1 Read-Status-Register 1 0011 0101b (35H) 001 to ∞
EWSR Enable-Write-Status-Register 0101b 0000b (50H) 000
WRSR Write-Status-Register 0000 0001b (01H) 0 0 1 or 2
WREN Write-Enable 0000 0110b (06H) 000
WRDI Write-Disable 0000 0100b (04H) 000

8

RDID

Read-ID 1001 0000b (90H) or

301 to ∞

1010 1011b (ABH)
JEDEC-ID JEDEC ID Read 1001 1111b (9FH) 003 to ∞
EBSY Enable SO t o o u t p u t RY/BY # s tatus

0111 0000b (70H) 000

during AAI programming

DBSY Disable SO to output RY/BY# status

1000 0000b (80H) 000

during AAI programming

2

Dummy

Cycle(s)

Data

Cycle(s)

1. One bus cycle is eight clock periods.

2. Address bits above the most significant bit of each density can be VIL or VIH.

3. 4KByte Sector Erase addresses: use AMS-A

4. 32KByte Block Erase addresses: use AMS-A

5. 64KByte Block Erase addresses: use AMS-A

6. T o contin ue programming to the ne xt sequential address location, enter the 8-bit command, ADH, f ollow ed by 2 b ytes of data
to be programmed. Data Byte 0 will be programmed into the initial address [A
grammed into the initial address [A

7. The Read-Status-Register is continuous with ongoing clock cycles until terminated by a low to high transition on CE#.

8. Manufacturer’s ID is read with A0=0, and Device ID is read with A0=1. All other address bits are 00H. The Manufacturer’s ID
and Device ID output stream is continuous until terminated by a low-to-high transition on CE#.

DS25135A-page 8  2012 Microchip Technology Inc.

23-A1

remaining addresses are don’t care but must be set either at VIL or V

12,

remaining addresses are don’t care but must be set either at VIL or V

15,

remaining addresses are don’t care but must be set either at VIL or V

16,

] with A0=0, Data Byte 1 will be pro-

] with A0=1.

23-A1

IH.
IH.
IH.

4.5.1 READ (33/25 MHZ)

25135 HSRdSeq.0

CE#

SO

SI

SCK

ADD.

012345678

ADD. ADD.0B

HIGH IMPEDANCE

15 16 23 24 31 32 39 40

47 48 55 56 63 64

N+2 N+3 N+4

N

N+1

X

MSB

MSB

MSB

MODE 0

MODE 3

D

OUT

D

OUT

D

OUTDOUT

80

71 72

D

OUT

Note: X = Dummy Byte: 8 Clocks Input Dummy Cycle (VIL or VIH)

The Read instruction, 03H, supports up to 33 MHz (2.7-

3.6V operation) or 25 MHz (2.3-2.7V operation) Read.
The device outputs the data starting from the specified
address location. The data output stream is continuous
through all addresses until terminated by a low to high
transition on CE#. The internal address pointer will
automatically increment until the highest memory
address is reached. Once the highest memory address
is reached, the address pointer will automatically incre-

CE#

SST25PF020B

ment to the beginning (wrap-around) of the address
space. Once the data from address location 3FFFFH
has been read, the next output will be from address
location 000000H.

The Read instruction is initiated by executing an 8-bit
command, 03H, followed by address bits [A
must remain active low for the duration of the Read
cycle. See Figure 4-3 for the Read sequence.

23-A0

]. CE#

SCK

SO

MODE 3
MODE 0

SI

012345678

03

MSB

HIGH IMPEDANCE

ADD.

MSB

15 16

ADD. ADD.

FIGURE 4-3: READ SEQUENCE

4.5.2 HIGH-SPEED-READ (80/50 MHZ)

The High-Speed-Read instruction, supporting up to 80
MHz (2.7-3.6V operation) or 50 MHz (2.3-2.7V opera­tion) Read, is initiated by executing an 8-bit command,
0BH, followed by address bits [A
byte. CE# must remain active low for the duration of the
High-Speed-Read cycle. See Figure 4-4 for the High­Speed-Read sequence.

Following a dummy cycle, the High-Speed-Read
instruction outputs the data starting from the specified
address location. The data output stream is continuous

] and a dummy

23-A0

23

31

24

MSB

39

OUT

40

N+2 N+3 N+4N N+1

D

OUT

D

OUTDOUT

32

D

7047 48 55 56 63 64

D

OUT

25135 ReadSeq.0

through all addresses until terminated by a low to high
transition on CE#. The internal address pointer will
automatically increment until the highest memory
address is reached. Once the highest memory address
is reached, the address pointer will automatically incre­ment to the beginning (wrap-around) of the address
space. Once the data from address location 3FFFH
has been read, the next output will be from address
location 00000H.

FIGURE 4-4: HIGH-SPEED-READ SEQUENCE

 2012 Microchip Technology Inc. DS25135A-page 9

SST25PF020B

25135 ByteProg.0

CE#

SO

SI

SCK

ADD.

012345678

ADD. ADD. D

IN

02

HIGH IMPEDANCE

15 16

23

24

31

32

39

MODE 0

MODE 3

MSBMSB

MSB

LSB

4.5.3 BYTE-PROGRAM

The Byte-Program instruction programs the bits in the
selected byte to the desired data. The selected byte
must be in the erased state (FFH) when initiating a Pro­gram operation. A Byte-Program instruction applied to a
protected memory area will be ignored.

Prior to any Write operation, the Write-Enable (WREN)
instruction must be executed. CE# must remain active
low for the duration of the Byte-Program instruction.

FIGURE 4-5: BYTE-PROGRAM SEQUENCE

The Byte-Program instruction is initiated by executing
an 8-bit command, 02H, followed by address bits [A

23

A0]. Following the address, the data is input in order
from MSB (bit 7) to LSB (bit 0). CE# must be driven
high before the instruction is executed. The user may
poll the Busy bit in the software status register or wait

for the completion of the internal self-timed Byte-

T

BP

Program operation. See Figure 4-5 for the Byte-Pro­gram sequence.

-

4.5.4 AUTO ADDRESS INCREMENT (AAI)
WORD-PROGRAM

The AAI program instruction allows multiple bytes of
data to be programmed without re-issuing the next
sequential address location. This feature decreases
total programming time when multiple bytes or entire
memory array is to be programmed. An AAI Word pro­gram instruction pointing to a protected memory area
will be ignored. The selected address range must be in
the erased state (FFH) when initiating an AAI Word
Program operation. While within AAI Word Program­ming sequence, only the following instructions are
valid: for software end-of-write detection—AAI Word
(ADH), WRDI (04H), and RDSR (05H); for hardware
end-of-write detection—AAI Word (ADH) and WRDI
(04H). There are three options to determine the com­pletion of each AAI Word program cycle: hardware
detection by reading the Serial Output, software detec­tion by polling the BUSY bit in the software status reg­ister, or wait T
details.

Prior to any write operation, the Write-Enable (WREN)
instruction must be executed. Initiate the AAI Word
Program instruction by executing an 8-bit command,
ADH, followed by address bits [A
addresses, two bytes of data are input sequentially,
each one from MSB (Bit 7) to LSB (Bit 0). The first byte
of data (D0) is programmed into the initial address [A
A

] with A0=0, the second byte of Data (D1) is pro-

1

grammed into the initial address [A
CE# must be driven high before executing the AAI

Refer to“End-of-Write Detection” for

BP.

]. Following the

23-A0

23-A1

] with A0=1.

23

Word Program instruction. Check the BUSY status
before entering the next valid command. Once the
device indicates it is no longer busy, data for the next
two sequential addresses may be programmed, fol­lowed by the next two, and so on.

When programming the last desired word, or the high­est unprotected memory address, check the busy sta­tus using either the hardware or software (RDSR
instruction) method to check for program completion.
Once programming is complete, use the applicable
method to terminate AAI. If the device is in Software
End-of-Write Detection mode, execute the Write-Dis­able (WRDI) instruction, 04H. If the device is in AAI
Hardware End-of-Write Detection mode, execute the
Write-Disable (WRDI) instruction, 04H, followed by the
8-bit DBSY command, 80H. There is no wrap mode
during AAI programming once the highest unprotected
memory address is reached. See Figures 4-8 and 4-9
for the AAI Word programming sequence.

4.5.5 END-OF-WRITE DETECTION

There are three methods to determine completion of a
program cycle during AAI Word programming: hard­ware detection by reading the Serial Output, software
detection by polling the BUSY bit in the Software Status
Register, or wait T
detection method is described in the section below.

-

The Hardware End-of-Write

BP.

DS25135A-page 10  2012 Microchip Technology Inc.