Datasheet SST25PF020B Datasheet

SST25PF020B

2 Mbit 2.3-3.6V SPI Serial Flash

Features

• Single Voltage Read and Write Operations

- 2.3-3.6V

• Serial Interface Architecture

- SPI Compatible: Mode 0 and Mode 3

• High Speed Clock Frequency

- 80 MHz (2.7-3.6V operation)

- 50 MHz (2.3-2.7V operation)

• Superior Reliability

- Endurance: 100,000 Cycles (typical)

- Greater than 100 years Data Retention

• Low Power Consumption:

- Active Read Current: 10 mA (typical)

- Standby Cu rre nt : 5 µA (typ i c a l)

• Flexible Erase Capability

- Uniform 4 KByte sectors

- Uniform 32 KByte overlay blocks

- Uniform 64 KByte overlay blocks

• Fast Erase and Byte-Program:

- Chip-Erase Time: 35 ms (typical)

- Sector-/Block-Erase Time: 18 ms (typical)

- Byte-Program Time: 7 µs (typical)

• Auto Address Increment (AAI) Programming

- Decrease total chip programming time over
Byte-Program operations

• End-of-Write Detection

- Software polling the BUSY bit in Status Register

- Busy Status readout on SO pin in AAI Mode

• Hold Pin (HOLD#)

- Suspends a serial sequence to the memory
without deselecting the device

• Write Protection (WP#)

- Enables/Disables the Lock-Down function of
the status register

• Software Write Protection

- Write protection through Block-Protection bits
in status register

• Temperature Range

- Commercial: 0°C to +70°C

• Packages Available

- 8-lead SOIC (150 mils)

- 8-contact WSON (6mm x 5mm)

- 8-contact USON (3mm x 2mm)

• All non-Pb (lead-free) devices are RoHS compliant

Product Description

The 25 series Serial Flash family features a four-wire,
SPI-compatible interface that allows for a low pin-count
package which occupies less board space and ulti­mately lowers total system costs. The SST25PF020B
devices are enhanced with improved operating fre­quency and even lower power consumption.
SST25PF020B SPI serial flash memories are manu­factured with proprietary, high-performance CMOS
SuperFlash technology. The split-gate cell design and
thick-oxide tunneling injector attain better reliability and
manufacturability compared with alternate approaches.

The SST25PF020B devices significantly improve per­formance and reliability, while lowering power con­sumption. The devices write (Program or Erase) with a
single power supply of 2.3-3.6V for SST25PF020B.
The total energy consumed is a function of the applied
voltage, current, and time of application. Since for any
given voltage range, the SuperFlash technology uses
less current to program and has a shorter erase time,
the total energy consumed during any Erase or Pro­gram operation is less than alternative flash memory
technologies.

The SST25PF020B device is offered in 8-lead SOIC
(150 mils), 8-contact WSON (6mm x 5mm), and 8-con­tact USON (3mm x 2mm) packages. See Figure 2-1 for
pin assignments.

 2012 Microchip Technology Inc. DS25135A-page 1

SST25PF020B

1.0 FUNCTIONAL BLOCK DIAGRAM

Address

Buffers

and

Latches

Control Logic

X - Decoder

SuperFlash

Memory

Y - Decoder

I/O Buffers

and

Data Latches

Serial Interface

CE#

FIGURE 1-1: FUNCTIONAL BLOCK DIAGRAM

SCK SI SO WP# HOLD#

25135 B1.0

DS25135A-page 2  2012 Microchip Technology Inc.

2.0 PIN DESCRIPTION

1

2

3

4

8

7

6

5

CE#

SO

WP#

V

SS

V

DD

HOLD#

SCK

SI

T op Vie w

25135 08-soic S2A P1.0

8-Lead SOIC

1

2

3

4

8

7

6

5

CE#

SO

WP#

V

SS

T op View

V

DD

HOLD#

SCK

SI

25135 08-wson QA P2.0

8-Contact WSON

1

2

3

4

8

7

6

5

CE#

SO

WP#

V

SS

Top View

V

DD

HOLD#

SCK

SI

25135 08-uson Q3A P1.0

8-Contact USON

SST25PF020B

FIGURE 2-1: PIN ASSIGNMENTS

TABLE 2-1: PIN DESCRIPTION

Symbol Pin Name Functions

SCK Serial Clock To provide the timing of the serial interface.

Commands, addresses, or input data are latched on the rising edge of the clock
input, while output data is shifted out on the falling edge of the clock input.

SI Serial Data Input To transfer commands, addresses, or data serially into the device.

Inputs are latched on the rising edge of the serial clock.

SO Serial Data Output To transfer data serially out of the device.

Data is shifted out on the falling edge of the serial clock.
Outputs Flash busy status during AAI Programming when reconfigured as RY/BY#
pin. See “Hardware End-of-Write Detection” on page 11 for details.

CE# Chip Enable The device is enabled by a high to low transition on CE#. CE# must remain low for

the duration of any command sequence.
WP# Write Protect The Write Protect (WP#) pin is used to enable/disable BPL bit in the status register.
HOLD# Hold To temporarily stop serial communication with SPI flash memory without resetting

the device.
V

DD

V

SS

 2012 Microchip Technology Inc. DS25135A-page 3

Power Supply To provide power supply voltage: 2.3-3.6V for SST25PF020B

Ground

SST25PF020B

25135 SPIprot.0

MODE 3

SCK

SI

SO

CE#

MODE 3

DON'T CARE

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

MODE 0MODE 0

HIGH IMPEDANCE

MSB

MSB

3.0 MEMORY ORGANIZATION

The SST25PF020B S u p e r Fl a s h memory array is orga­nized in uniform 4 KByte erasable sectors with 32
KByte overlay blocks and 64 KByte overlay erasable
blocks.

4.0 DEVICE OPERATION

The SST25 PF 020 B is accessed through the SPI (Serial
Peripheral Interface) bus compatible protocol. The SPI
bus consist of four control lines; Chip Enable (CE#) is

used to select the device, and data is accessed through
the Serial Data Input (SI), Serial Data Output (SO), and
Serial Clock (SCK).

The SST25PF020B supports both Mode 0 (0,0) and
Mode 3 (1,1) of SPI bus operations. The difference
between the two modes, as shown in Figure 4-1, is the
state of the SCK signal when the bus master is in
Standby mode and no data is being transferred. The
SCK signal is low for Mode 0 and SCK signal is high for
Mode 3. For both modes, the Serial Data In (SI) is sam­pled at the rising edge of the SCK clock signal and the
Serial Data Output (SO) is driven after the falling edge
of the SCK clock signal.

FIGURE 4-1: SPI PROTOCOL

4.1 Hold Operation

The HOLD# pin is used to pause a serial sequence
underway with the SPI flash memory without resetting
the clocking sequence. To activate the HOLD# mode,
CE# must be in active low state. The HOLD# mode
begins when the SCK active low state coincides with
the falling edge of the HOLD# signal. The HOLD mode
ends when the HOLD# signal’s rising edge coincides
with the SCK active low state.

If the falling edge of the HOLD# signal does not coin­cide with the SCK active low state, then the device
enters Hold mode when the SCK next reaches the
active low state. Similarly, if the rising edge of the
HOLD# signal does not coincide with the SCK active

SCK

HOLD#

Active Hold Active Hold Active

low state, then the device exits in Hold mode when the
SCK next reaches the active low state. See Figure 4-2
for Hold Condition waveform.

Once the device enters Hold mode, SO will be in high­impedance state while SI and SCK can be V

IL

or V

IH.

If CE# is driven high during a Hold condition, the device
returns to Standby mode. As long as HOLD# signal is
low, the memory remains in the Hold condition. To
resume communication with the device, HOLD# must
be driven active high, and CE# must be driven active
low. See Figure 4-2 for Hold timing.

25135 HoldCond.0

FIGURE 4-2: HOLD CONDITION WAVEFORM

DS25135A-page 4  2012 Microchip Technology Inc.

4.2 Write Protection

SST25PF020B

SST2 5 PF020B provides soft ware Wr ite protection. The
Write Protect pin (WP#) enables or disables the lock­down function of the status register. The Block-Protec­tion bits (BP1, BP0, and BPL) in the status register, and
the Top/Bottom Sector Protection Status bits (TSP and
BSP) in Status Register 1, provide Write protection to
the memory array and the status register. See Table 4-

4 for the Block-Protection description.

4.2.1 WRITE PROTECT PIN (WP#)

The Write Protect (WP#) pin enables the lock-down
function of the BPL bit (bit 7) in the status register.
When WP# is driven low, the execution of the Write­Status-Register (WRSR) instruction is determined by
the value of the BPL bit (see Table 4-1). When WP# is
high, the lock-down function of the BPL bit is disabled.

TABLE 4-1: CONDITIONS TO EXECUTE WRITE-STATUS-REGISTER (WRSR) INSTRUCTION

WP# BPL Execute WRSR Instruction

L1Not Allowed
L0Allowed

HXAllowed

4.3 Status Register

The software status register provides status on
whether the flash memory array is available for any
Read or Write operation, whether the device is Write
enabled, and the state of the Memory Write protection.

TABLE 4-2: SOFTWARE STATUS REGISTER

Bit Name Function

0 BUSY 1 = Internal Write operation is in progress

0 = No internal Write operation is in progress

1 WEL 1 = Device is memory Write enabled

0 = Device is not memory Write enabled

2 BP0 Indicates current level of block write protection (See Table 4-4) 1R/W
3 BP1 Indicates current level of block write protection (See Table 4-4) 1R/W

4:5 RES Reserved for future use 0N/A

6 AAI Auto Address Increment Programming status

1 = AAI programming mode
0 = Byte-Program mode

7 BPL 1 = BP1, BP0 are read-only bits

0 = BP1, BP0 are read/writable

During an internal Erase or Program operation, the sta­tus register may be read only to determine the comple­tion of an operation in progress. Table 4-2 describes
the function of each bit in the software status register.

Default at
Power-up Read/Write

0R

0R

0R

0R/W

 2012 Microchip Technology Inc. DS25135A-page 5

SST25PF020B

4.4 Software Status Register 1

The Software St atus Register 1 is an additional register that
contains Top Sector and Bottom Sector Protection bits.
These register bits are read/writable and determine the lock

and unlock status of the top and bottom sectors. Table 4-3
describes the function of each bit in the Software Status
Register 1.

TABLE 4-3: SOFTWARE STATUS REGISTER 1

Default at

Bit Name Function

0:1 RES Reserved for future use 0N/A

2 TSP Top Sector Protection status

1 = Indicates highest sector is write locked
0 = Indicates highest sector is Write accessible

3 BSP Bottom Sector Protection status

1 = Indicates lowest sector is write locked
0 = Indicates lowest sector is Write accessible

4:7 RES Reserved for future use 0N/A

4.4.1 BUSY

The Busy bit determines whether there is an internal
Erase or Program operation in progress. A “1” for the
Busy bit indicates the device is busy with an operation
in progress. A “0” indicates the device is ready for the
next valid operation.

4.4.2 WRITE ENABLE LATCH (WEL)

The Write-Enable-Latch bit indicates the status of the
internal memory Write Enable Latch. If the Write­Enable-Latch bit is set to “1”, it indicates the device is
Write enabled. If the bit is set to “0” (reset), it indicates
the device is not Write enabled and does not accept
any memory Write (Program/Erase) commands. The
Write-Enable-Latch bit is automatically reset under the
following conditions:

• Power-up

• Write-Disable (WRDI) instruction completion

• Byte-Program instruction completion

• Auto Address Increment (AAI) programming is
completed or reached its highest unprotected

memory address

• Sector-Erase instruction completion

• Block-Erase instruction completion

• Chip-Erase instruction completion

• Write-Status-Register instruction completion

4.4.3 AUTO ADDRESS INCREMENT (AAI)

The Auto Address Increment Programming-Status bit
provides status on whether the device is in AAI pro­gramming mode or Byte-Program mode. The default at
power up is Byte-Program mode.

4.4.4 BLOCK PROTECTION (BP1, BP0)

The Block-Protection (BP1, BP0) bits define the size of
the memory area, as defined in T able 4-4, to be software
protected against any memory Write (Program or Erase)
operation. The Write-Status-Register (WRSR) instruc­tion is used to program the BP1 and BP0 bits as long as
WP# is high or the Block-Protect-Lock (BPL) bit is 0.
Chip-Erase can only be executed if Block-Protection bits
are all 0. After power-up, BP1 and BP0 are set to 1.

Power-up Read/Write

0R/W

0R/W

TABLE 4-4: SOFTWARE STATUS REGISTER BLOCK PROTECTION FOR SST25PF020B

Status Register Bit

Protection Level

000None
1 (1/4 Memory Array) 0 1 030000H-03FFFFH
1 (1/2 Memory Array) 1 0 020000H-03FFFFH
1 (Full Memory Array) 1 1 000000H-03FFFFH

1. X = Don’t Care (RESERVED) default is ‘0’

2. Default at power-up for BP1 and BP0 is ‘11’. (All Blocks Protected)

DS25135A-page 6  2012 Microchip Technology Inc.

BP1 BP0 2 Mbit

2

Protected Memory Address

1

4.4.5 BLOCK PROTECTION LOCK-DOWN
(BPL)

WP# pin driven low (VIL), enables the Block-Protection­Lock-Down (BPL) bit. When BPL is set to 1, it prevents
any further alteration of the BPL, BP1, and BP0 bits of
the status register and BSP and TSP of St atus Register

1. When the WP# pin is driven high (V

has no effect and its value is “Don’t Care”. After power­up, the BPL bit is reset to 0.

), the BPL bit

IH

4.4.6 TOP-SECTOR PROTECTION/
BOTTOM-SECTOR PROTECTION

The Top-Sector Protection (TSP) and Bottom-Sector
Protection (BSP) bits independently indicate whether
the highest and lowest sector locations are Write
locked or Write accessible. When TSP or BSP is set to
‘1’, the respective sector is Write locked; when set to ‘0’
the respective sector is Write accessible. If TSP or BSP
is set to '1' and if the top or bottom sector is within the
boundary of the target address range of the program or
erase instruction, the initiated instruction (Byte-Pro­gram, AAI-Word Program, Sector-Erase, Block-Erase,
and Chip-Erase) will not be executed. Upon power-up,
the TSP and BSP bits are automatically reset to ‘0’.

SST25PF020B

 2012 Microchip Technology Inc. DS25135A-page 7

SST25PF020B

4.5 Instructions

Instructions are used to read, write (Erase and Pro­gram), and configure the SST25PF020B. The instruc­tion bus cycles are 8 bits each for commands (Op
Code), data, and addresses. Prior to executing any
Byte-Program, Auto Address Increment (AAI) program­ming, Sector-Erase, Block-Erase, Write-Status-Regis­ter, or Chip-Erase instructions, the Write-Enable
(WREN) instruction must be executed first. The com­plete list of instructions is provided in Table 4-5. All
instructions are synchronized off a high to low transition

SCK starting with the most significant bit. CE# must be
driven low before an instruction is entered and must be
driven high after the last bit of the instruction has been
shifted in (except for Read, Read-ID, and Read-Status­Register instructions). Any low to high transition on
CE#, before receiving the last bit of an instruction bus
cycle, will terminate the instruction in progress and
return the device to standby mode. Instruction com­mands (Op Code), addresses, and data are all input
from the most significant bit (MSB) first.

of CE#. Inputs will be accepted on the rising edge of

TABLE 4-5: DEVICE OPERATION INSTRUCTIONS

Address

Cycle(s)

Instruction Description Op Code Cycle

1

Read Read Memory 0000 0011b (03H) 301 to ∞
High-Speed Read Read Memory at higher speed 0000 1011b (0BH) 311 to ∞
4 KByte Sector-

3

Erase
32 KByte Block-

4

Erase
64 KByte Block-

5

Erase
Chip-Erase Erase Full Memory Array 0110 0000b (60H) or

Erase 4 KByte of memory array 0010 0000b (20H) 300

Erase 32 KByte block of memory

0101 0010b (52H) 300

array
Erase 64 KByte block of memory

1101 1000b (D8H) 300

array

000

1100 0111b (C7H)
Byte-Program To Program One Data Byte 0000 0010b (02H) 301
AAI-Word-Program

6

Auto Address Increment Program-

1010 1101b (ADH) 302 to ∞

ming

7

RDSR

Read-Status-Register 0000 0101b (05H) 001 to ∞
RDSR1 Read-Status-Register 1 0011 0101b (35H) 001 to ∞
EWSR Enable-Write-Status-Register 0101b 0000b (50H) 000
WRSR Write-Status-Register 0000 0001b (01H) 0 0 1 or 2
WREN Write-Enable 0000 0110b (06H) 000
WRDI Write-Disable 0000 0100b (04H) 000

8

RDID

Read-ID 1001 0000b (90H) or

301 to ∞

1010 1011b (ABH)
JEDEC-ID JEDEC ID Read 1001 1111b (9FH) 003 to ∞
EBSY Enable SO t o o u t p u t RY/BY # s tatus

0111 0000b (70H) 000

during AAI programming

DBSY Disable SO to output RY/BY# status

1000 0000b (80H) 000

during AAI programming

2

Dummy

Cycle(s)

Data

Cycle(s)

1. One bus cycle is eight clock periods.

2. Address bits above the most significant bit of each density can be VIL or VIH.

3. 4KByte Sector Erase addresses: use AMS-A

4. 32KByte Block Erase addresses: use AMS-A

5. 64KByte Block Erase addresses: use AMS-A

6. T o contin ue programming to the ne xt sequential address location, enter the 8-bit command, ADH, f ollow ed by 2 b ytes of data
to be programmed. Data Byte 0 will be programmed into the initial address [A
grammed into the initial address [A

7. The Read-Status-Register is continuous with ongoing clock cycles until terminated by a low to high transition on CE#.

8. Manufacturer’s ID is read with A0=0, and Device ID is read with A0=1. All other address bits are 00H. The Manufacturer’s ID
and Device ID output stream is continuous until terminated by a low-to-high transition on CE#.

DS25135A-page 8  2012 Microchip Technology Inc.

23-A1

remaining addresses are don’t care but must be set either at VIL or V

12,

remaining addresses are don’t care but must be set either at VIL or V

15,

remaining addresses are don’t care but must be set either at VIL or V

16,

] with A0=0, Data Byte 1 will be pro-

] with A0=1.

23-A1

IH.
IH.
IH.

4.5.1 READ (33/25 MHZ)

25135 HSRdSeq.0

CE#

SO

SI

SCK

ADD.

012345678

ADD. ADD.0B

HIGH IMPEDANCE

15 16 23 24 31 32 39 40

47 48 55 56 63 64

N+2 N+3 N+4

N

N+1

X

MSB

MSB

MSB

MODE 0

MODE 3

D

OUT

D

OUT

D

OUTDOUT

80

71 72

D

OUT

Note: X = Dummy Byte: 8 Clocks Input Dummy Cycle (VIL or VIH)

The Read instruction, 03H, supports up to 33 MHz (2.7-

3.6V operation) or 25 MHz (2.3-2.7V operation) Read.
The device outputs the data starting from the specified
address location. The data output stream is continuous
through all addresses until terminated by a low to high
transition on CE#. The internal address pointer will
automatically increment until the highest memory
address is reached. Once the highest memory address
is reached, the address pointer will automatically incre-

CE#

SST25PF020B

ment to the beginning (wrap-around) of the address
space. Once the data from address location 3FFFFH
has been read, the next output will be from address
location 000000H.

The Read instruction is initiated by executing an 8-bit
command, 03H, followed by address bits [A
must remain active low for the duration of the Read
cycle. See Figure 4-3 for the Read sequence.

23-A0

]. CE#

SCK

SO

MODE 3
MODE 0

SI

012345678

03

MSB

HIGH IMPEDANCE

ADD.

MSB

15 16

ADD. ADD.

FIGURE 4-3: READ SEQUENCE

4.5.2 HIGH-SPEED-READ (80/50 MHZ)

The High-Speed-Read instruction, supporting up to 80
MHz (2.7-3.6V operation) or 50 MHz (2.3-2.7V opera­tion) Read, is initiated by executing an 8-bit command,
0BH, followed by address bits [A
byte. CE# must remain active low for the duration of the
High-Speed-Read cycle. See Figure 4-4 for the High­Speed-Read sequence.

Following a dummy cycle, the High-Speed-Read
instruction outputs the data starting from the specified
address location. The data output stream is continuous

] and a dummy

23-A0

23

31

24

MSB

39

OUT

40

N+2 N+3 N+4N N+1

D

OUT

D

OUTDOUT

32

D

7047 48 55 56 63 64

D

OUT

25135 ReadSeq.0

through all addresses until terminated by a low to high
transition on CE#. The internal address pointer will
automatically increment until the highest memory
address is reached. Once the highest memory address
is reached, the address pointer will automatically incre­ment to the beginning (wrap-around) of the address
space. Once the data from address location 3FFFH
has been read, the next output will be from address
location 00000H.

FIGURE 4-4: HIGH-SPEED-READ SEQUENCE

 2012 Microchip Technology Inc. DS25135A-page 9

SST25PF020B

25135 ByteProg.0

CE#

SO

SI

SCK

ADD.

012345678

ADD. ADD. D

IN

02

HIGH IMPEDANCE

15 16

23

24

31

32

39

MODE 0

MODE 3

MSBMSB

MSB

LSB

4.5.3 BYTE-PROGRAM

The Byte-Program instruction programs the bits in the
selected byte to the desired data. The selected byte
must be in the erased state (FFH) when initiating a Pro­gram operation. A Byte-Program instruction applied to a
protected memory area will be ignored.

Prior to any Write operation, the Write-Enable (WREN)
instruction must be executed. CE# must remain active
low for the duration of the Byte-Program instruction.

FIGURE 4-5: BYTE-PROGRAM SEQUENCE

The Byte-Program instruction is initiated by executing
an 8-bit command, 02H, followed by address bits [A

23

A0]. Following the address, the data is input in order
from MSB (bit 7) to LSB (bit 0). CE# must be driven
high before the instruction is executed. The user may
poll the Busy bit in the software status register or wait

for the completion of the internal self-timed Byte-

T

BP

Program operation. See Figure 4-5 for the Byte-Pro­gram sequence.

-

4.5.4 AUTO ADDRESS INCREMENT (AAI)
WORD-PROGRAM

The AAI program instruction allows multiple bytes of
data to be programmed without re-issuing the next
sequential address location. This feature decreases
total programming time when multiple bytes or entire
memory array is to be programmed. An AAI Word pro­gram instruction pointing to a protected memory area
will be ignored. The selected address range must be in
the erased state (FFH) when initiating an AAI Word
Program operation. While within AAI Word Program­ming sequence, only the following instructions are
valid: for software end-of-write detection—AAI Word
(ADH), WRDI (04H), and RDSR (05H); for hardware
end-of-write detection—AAI Word (ADH) and WRDI
(04H). There are three options to determine the com­pletion of each AAI Word program cycle: hardware
detection by reading the Serial Output, software detec­tion by polling the BUSY bit in the software status reg­ister, or wait T
details.

Prior to any write operation, the Write-Enable (WREN)
instruction must be executed. Initiate the AAI Word
Program instruction by executing an 8-bit command,
ADH, followed by address bits [A
addresses, two bytes of data are input sequentially,
each one from MSB (Bit 7) to LSB (Bit 0). The first byte
of data (D0) is programmed into the initial address [A
A

] with A0=0, the second byte of Data (D1) is pro-

1

grammed into the initial address [A
CE# must be driven high before executing the AAI

Refer to“End-of-Write Detection” for

BP.

]. Following the

23-A0

23-A1

] with A0=1.

23

Word Program instruction. Check the BUSY status
before entering the next valid command. Once the
device indicates it is no longer busy, data for the next
two sequential addresses may be programmed, fol­lowed by the next two, and so on.

When programming the last desired word, or the high­est unprotected memory address, check the busy sta­tus using either the hardware or software (RDSR
instruction) method to check for program completion.
Once programming is complete, use the applicable
method to terminate AAI. If the device is in Software
End-of-Write Detection mode, execute the Write-Dis­able (WRDI) instruction, 04H. If the device is in AAI
Hardware End-of-Write Detection mode, execute the
Write-Disable (WRDI) instruction, 04H, followed by the
8-bit DBSY command, 80H. There is no wrap mode
during AAI programming once the highest unprotected
memory address is reached. See Figures 4-8 and 4-9
for the AAI Word programming sequence.

4.5.5 END-OF-WRITE DETECTION

There are three methods to determine completion of a
program cycle during AAI Word programming: hard­ware detection by reading the Serial Output, software
detection by polling the BUSY bit in the Software Status
Register, or wait T
detection method is described in the section below.

-

The Hardware End-of-Write

BP.

DS25135A-page 10  2012 Microchip Technology Inc.

4.5.6 HARDWARE END-OF-WRITE DETECTION

CE#

SO

SI

SCK

01234567

70

HIGH IMPEDANCE

MODE 0

MODE 3

25135 EnableSO.0

MSB

The Hardware End-of-Write detection method elimi­nates the overhead of polling the Busy bit in the Soft­ware Status Register during an AAI Word program
operation. The 8-bit command, 70H, configures the
Serial Output (SO) pin to indicate Flash Busy status
during AAI Word programming. (see Figure 4-6) The 8­bit command, 70H, must be executed prior to initiating
an AAI Word-Program instruction. Once an internal
programming operation begins, asserting CE# will
immediately drive the status of the internal flash status
on the SO pin. A ‘0’ indicates the device is busy and a

SST25PF020B

‘1’ indicates the device is ready for the next instruction.
De-asserting CE# will return the SO pin to tri-state.
While in AAI and Hardware End-of-Write detection
mode, the only valid instructions are AAI Word (ADH)
and WRDI (04H).

To exit AAI Hardware End-of-Write detection, first exe­cute WRDI instruction, 04H, to reset the Write-Enable­Latch bit (WEL=0) and AAI bit. Then execute the 8-bit
DBSY command, 80H, to disable RY/BY# status during
the AAI command. See Figures 4-7 and 4-8.

FIGURE 4-6: ENABLE SO AS HARDWARE RY/BY# DURING AAI PROGRAMMING

CE#

SCK

SO

MODE 3
MODE 0

SI

01234567

80

MSB

HIGH IMPEDANCE

25135 DisableSO.0

FIGURE 4-7: DISABLE SO AS HARDWARE RY/BY# DURING AAI PROGRAMMING

 2012 Microchip Technology Inc. DS25135A-page 11

SST25PF020B

CE#

SI

SCK

SO

25135 AAI.HW.3

Check for Flash Busy Status to load next valid1 command

Load AAI command, Address, 2 bytes data

Note: 1. Valid commands during AAI programming: AAI command or WRDI command

2. User must configure the SO pin to output Flash Busy status during AAI programming

0

AAAADD0 AD

MODE 3
MODE 0

D1 D2 D3

7

WREN

EBSY

0

7

078 32 4715 16 23 24 31 04039 7 8 15 16 23

D

OUT

WRDI followed by DBSY

to exit AAI Mode

WRDI RDSR

70157 80

DBSY

70

CE# cont.

SI cont.

SCK cont.

SO cont.

Last 2

Data Bytes

AD

D

n-1

D

n

7 8 15 16 230

Check for Flash Busy Status to load next valid1 command

078 32 4715 16 23 24 31 04039 7 8 15 16 23 7 8 15 16 23 70 157800

CE#

SI

SCK

SO

D

OUT

MODE 3
MODE 0

25135 AAI.SW.2

Note: 1. Valid commands during AAI programming: AAI command, RDSR command, or WRDI command

Wait TBP or poll Software Status

register to load next valid

1

command

Last 2

Data Bytes

WRDI to exit

AAI Mode

Load AAI command, Address, 2 bytes data

AAAAD D0 ADD1 D2 D3 AD

D

n-1Dn

WRDI

RDSR

FIGURE 4-8: AUTO ADDRESS INCREMENT (AAI) WORD-PROGRAM SEQUENCE WITH

HARDWARE END-OF-WRITE DETECTION

FIGURE 4-9: AUTO ADDRESS INCREMENT (AAI) WORD-PROGRAM SEQUENCE WITH

SOFTWARE END-OF-WRITE DETECTION

DS25135A-page 12  2012 Microchip Technology Inc.

4.5.7 4-KBYTE SECTOR-ERASE

CE#

SO

SI

SCK

ADDR

012345678

ADDR ADDR

52

HIGH IMPEDANCE

15 16

23

24

31

MODE 0

MODE 3

25135 32KBklEr.0

MSB MSB

The Sector-Erase instruction clears all bits in the
selected 4 KByte sector to FFH. A Sector-Erase
instruction applied to a protected memory area will be
ignored. Prior to any Write operation, the Write-Enable
(WREN) instruction must be executed. CE# must
remain active low for the duration of any command
sequence. The Sector-Erase instruction is initiated by
executing an 8-bit command, 20H, followed by address

CE#

SST25PF020B

bits [A
nificant address) are used to determine the sector
address (SA
CE# must be driven high before the instruction is exe­cuted. The user may poll the Busy bit in the software
status register or wait T
internal self-timed Sector-Erase cycle. See Figure 4-10
for the Sector-Erase sequence.

]. Address bits [AMS-A12] (AMS=Most Sig-

23-A0

), remaining address bits can b e VIL or V

X

for the completion of the

SE

IH.

SCK

SO

MODE 3
MODE 0

SI

012345678

20

HIGH IMPEDANCE

FIGURE 4-10: SECTOR-ERASE SEQUENCE

4.5.8 32-KBYTE AND 64-KBYTE BLOCK­ERASE

The 32-KByte Block-Erase instruction clears all bits in
the selected 32 KByte block to FFH. A Block-Erase
instruction applied to a protected memory area will be
ignored. The 64-KByte Block-Erase instruction clears all bits
in the selected 64 KByte block to FFH. A Block-Erase
instruction applied to a protected memory area will be
ignored. Prior to any Write operation, the Write-Enable
(WREN) instruction must be executed. CE# m u st r e main
active low for the duration of any command sequence.
The 32-KByte Block-Erase instruction is initiated by
executing an 8-bit command, 52H, followed by address
bits [A

]. Address bits [AMS-A15] (AMS= Most Sig-

23-A0

15 16

ADD.

MSBMSB

23

24

ADD. ADD.

25135 SecErase.0

31

nificant Address) are used to determine block address

), remaining address bits can be VIL or V

(BA

X

must be driven high before the instruction is executed. The
64-KByte Block-Erase instruction is initiated by executing an
8-bit command D8H, followed by address bits [A
Address bits [AMS-A16] are used to determine block address
(BAX), remaining address bits can be VIL or V

CE# must

IH.

be driven high before the instruction is executed. The user
ma y po ll th e Bu sy bit in th e software status register or wait

for the completion of the internal self-timed 32-

T

BE

KByte Block-Erase or 64-KByte Block-Erase cycles.
See Figures 4-11 and 4-12 for the 32-KByte Block­Erase and 64-KByte Block-Erase sequences.

IH.

23-A0

CE#

].

FIGURE 4-11: 32-KBYTE BLOCK-ERASE SEQUENCE

 2012 Microchip Technology Inc. DS25135A-page 13

SST25PF020B

CE#

SCK

SO

MODE 3
MODE 0

SI

012345678

D8

MSB MSB

HIGH IMPEDANCE

ADDR

15 16

FIGURE 4-12: 64-KBYTE BLOCK-ERASE SEQUENCE

4.5.9 CHIP-ERASE

The Chip-Erase instruction clears all bits in the device
to FFH. A Chip-Erase instruction will be ignored if any
of the memory area is protected. Prior to any Wri te oper­ation, the Write-Enable (WREN) instruction must be exe­cuted. CE# must remain active low for the duration of
the Chip-Erase instruction sequence. The Chip-Erase

CE#

MODE 3
MODE 0

SCK

01234567

instruction is initiated by executing an 8-bit command,
60H or C7H. CE# must be driven high before the instruction
is executed. The user may poll the Busy bit in the software
status register or wait T
internal self-timed Chip-Erase cycle. See Figure 4-13
for the Chip-Erase sequence.

23

24

ADDR ADDR

25135 63KBlkEr.0

31

for the completion of the

CE

SI

SO

HIGH IMPEDANCE

FIGURE 4-13: CHIP-ERASE SEQUENCE

4.5.10 READ-STATUS-REGISTER (RDSR)

The Read-Status-Register (RDSR) instruction allows
reading of the status register. The Status Register may
be read at any time even during a Write (Program/
Erase) operation. When a Write operation is in prog­ress, the Busy bit may be checked before sending any
new commands to assure that the new commands are
properly received by the device. CE# must be driven
low before the RDSR instruction is entered and remain
low until the status data is read. Read-Status-Register
is continuous with ongoing clock cycles until it is termi­nated by a low to high transition of the CE#. See Figure

4-14 for the RDSR instruction sequence.

60 or C7

MSB

25135 ChEr.0

DS25135A-page 14  2012 Microchip Technology Inc.

FIGURE 4-14: READ-STATUS-REGISTER (RDSR) SEQUENCE

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14

25135 RDSRseq.0

MODE 3

SCK

SI

SO

CE#

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

05

MODE 0

HIGH IMPEDANCE

Status

Register Out

MSB

MSB

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14

25135 RDSR1seq.0

MODE 3

SCK

SI

SO

CE#

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

35

MODE 0

HIGH IMPEDANCE

Status

Register Out

MSB

MSB

CE#

SO

SI

SCK

01234567

06

HIGH IMPEDANCE

MODE 0

MODE 3

25135 WREN.0

MSB

SST25PF020B

4.5.11 READ-STATUS-REGISTER (RDSR1)

The Read-Status-Register 1 (RDSR1) instruction
allows reading of the status register 1. CE# must be
driven low before the RDSR instruction is entered and

remain low until the status data is read. Read-Status­Register 1 is continuous with ongoing clock cycles until
it is terminated by a low to high transition of the CE#.
See Figure 4-15 for the RDSR instruction sequence.

FIGURE 4-15: READ-STATUS-REGISTER 1 (RDSR1) SEQUENCE

4.5.12 WRITE-ENABLE (WREN)

The Write-Enable (WREN) instruction sets the Write­Enable-Latch bit in the Status Register to 1 allowing
Write operations to occur. The WREN instruction must
be executed prior to any Write (Program/Erase) opera­tion. The WREN instruction may also be used to allow

execution of the Write-Status-Register (WRSR) instruc­tion; however, the Write-Enable-Latch bit in the Status
Register will be cleared upon the rising edge CE# of the
WRSR instruction. CE# must be driven high before the
WREN instruction is executed.

FIGURE 4-16: WRITE ENABLE (WREN) SEQUENCE

 2012 Microchip Technology Inc. DS25135A-page 15

SST25PF020B

25135 EWSR.0

MODE 3

HIGH IMPEDANCE

MODE 0

STATUS

REGISTER IN

76543210

MSBMSBMSB

01

MODE 3

SCK

SI

SO

CE#

MODE 0

50 or 06

0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

4.5.13 WRITE-DISABLE (WRDI)

The Write-Disable (WRDI) instruction resets the Write­Enable-Latch bit and AAI bit to 0 disabling any new
Write operations from occurring. The WRDI instruction

ress. Any program operation in progress may continue
up to T
must be driven high before the WRDI instruction is exe­cuted.

will not terminate any programming operation in pro g-

CE#

SCK

SO

MODE 3
MODE 0

SI

01234567

04

MSB

HIGH IMPEDANCE

FIGURE 4-17: WRITE DISABLE (WRDI) SEQUENCE

4.5.14 ENABLE-WRITE-STATUS­REGISTER (EWSR)

The Enable-Write-Status-Register (EWSR) instruction
arms the Write-Status-Register (WRSR) instruction
and opens the status register for alteration. The Write­Status-Register instruction must be executed immedi­ately after the execution of the Enable-Write-Status­Register instruction. This two-step instruction
sequence of the EWSR instruction followed by the
WRSR instruction works like SDP (software data pro­tection) command structure which prevents any acci­dental alteration of the status register values. CE# must
be driven low before the EWSR instruction is entered
and must be driven high before the EWSR instruction
is executed.

4.5.15 WRITE-STATUS-REGISTER (WRSR)

The Write-Status-Register instruction writes new val­ues to the BP1, BP0, and BPL bi ts of the stat us register .
CE# must be driven low before the command

sequence of the WRSR instruction is entered and
driven high before the WRSR instruction is executed.
See Figure 4-18 for EWSR or WREN and WRSR for
byte-data input sequences.

Executing the Write-Status-Register instruction will be
ignored when WP# is low and BPL bit is set to “1”.
When the WP# is low, the BPL bit can only be set from
“0” to “1” to lock-down the status register, but cannot be
reset from “1” to “0”. When WP# is high, the lock-down
function of the BPL bit is disabled and the BPL, BP0,
and BP1 bits in the status register can all be changed.
As long as BPL bit is set to 0 or WP# pin is driven high
(V
the end of the WRSR instruction, the bits in the status
register can all be altered by the WRSR instruction. In
this case, a single WRSR instruction can set the BPL
bit to “1” to lock down the status register as well as
altering the BP0, BP1, and BP2 bits at the same time.
See Table 4-1 for a summary description of WP# and
BPL functions.

after executing the WRDI instruction. CE#

BP

25135 WRDI.0

) prior to the low-to-high transition of the CE# pin at

IH

FIGURE 4-18: ENABLE-WRITE-STATUS-REGISTER (EWSR) OR WRITE-ENABLE (WREN) AND

WRITE-STATUS-REGISTER (WRSR) BYTE-DATA INPUT SEQUENCE

DS25135A-page 16  2012 Microchip Technology Inc.

SST25PF020B

25135 EWSR1.0

MODE 3

HIGH IMPEDANCE

MODE 0

STATUS

REGISTER

76543210

MSBMSBMSB

01

MODE 3

SCK

SI

SO

CE#

MODE 0

50 or 06

01234567 0123456789101112131415

STATUS

REGISTER 1

76543210

MSB

16 17 18 19 20 21 22 23

The Write-Status-Register instruction also writes new
values to the Status Register 1. To write values to Sta­tus Register 1, the WRSR sequence needs a word­data input—the first byte being the Status Register bits,
followed by the second byte S tat us Register 1 bits. CE#
must be driven low before the command sequence of
the WRSR instruction is entered and driven high before
the WRSR instruction is executed. See Figure 4-19 for
EWSR or WREN and WRSR instruction word-data
input sequences.

Executing the Write-Status-Register instruction will be
ignored when WP# is low and BPL bit is set to ‘1’. When
the WP# is low, the BPL bit can only be set from ‘0’ to

‘1’ to lock-down the status registers, but cannot be
reset from ‘1’ to ‘0’. When WP# is high, the lock-down
function of the BPL bit is disabled and the BPL, BP0,
BP1, TSP, and BSP bits in the status register can all be
changed. As long as BPL bit is set to 0 or WP# pin is
driven high (V

) prior to the low-to-high transition of the

IH

CE# pin at the end of the WRSR instruction, the bits in
the status register can all be altered by the WRSR
instruction. In this case, a single WRSR instruction can
set the BPL bit to “1” to lock down the status register as
well as altering the BPL, BP0, BP1, TSP, and BSP bits
at the same time. See T able 4-1 for a summary descrip­tion of WP# and BPL functions.

FIGURE 4-19: ENABLE-WRITE-STATUS-REGISTER (EWSR) OR WRITE-ENABLE (WREN) AND

WRITE-STATUS-REGISTER (WRSR) WORD-DATA INPUT SEQUENCE

The WRSR instruction can either execute a byte-data
or a word-data input. Extra data/clock input, or within
byte-/word-data input, will not be executed. The reason
for the byte support is for backward compatibility to
products where WRSR instruction sequence is fol­lowed by only a byte-data.

 2012 Microchip Technology Inc. DS25135A-page 17

SST25PF020B

25 8C

25135 JEDECID.1

CE#

SO

SI

SCK

012345678

HIGH IMPEDANCE

15 1614 28 29 30 31

BF

MODE 3
MODE 0

MSBMSB

9 10111213 17189F19 20 21 22 23 24 25 26 27

4.5.16 JEDEC READ-ID

The JEDEC Read-ID instruction identifies the device as
SST25PF020B and the manufacturer as Microchip.
The device information can be read from executing the
8-bit command, 9FH. Following the JEDEC Read-ID
instruction, the 8-bit manufacturer’s ID, BFH, is output
from the device. After that, a 16-bit device ID is shifted
out on the SO pin. Byte 1, BFH, identifies the manufac-

turer as Microchip. Byte 2, 25H, identifies the memory
type as SPI Serial Flash. Byte 3, 8CH, identifies the
device as SST25PF020B. The instruction sequence is
shown in Figure 4-20. The JEDEC Read ID instruction
is terminated by a low to high transition on CE# a t any
time during data output.

FIGURE 4-20: JEDEC READ-ID SEQUENCE

TABLE 4-6: JEDEC READ-ID DATA

Device ID

Manufacturer’s ID Memory Type Memory Capacity

Byte1 Byte 2 Byte 3

BFH 25H 8CH

DS25135A-page 18  2012 Microchip Technology Inc.

4.5.17 READ-ID (RDID)

25135 RdID.0

CE#

SO

SI

SCK

00

012345678

00 ADD

1

90 or AB

HIGH IMPEDANCE

15 16

23

24

31

32

39

40

47 48 55 56 63

BF

Device ID

BF

Device ID

Note: The manufacturer's and device ID output stream is continuous until terminated by a low to high transition on CE#.
Device ID = 8CH for SST25PF020B

1. 00H will output the manfacturer's ID first and 01H will output device ID first before toggling between the two.

HIGH

IMPEDANCE

MODE 3
MODE 0

MSB MSB

MSB

The Read-ID instruction (RDID) identifies the devices
as SST2 5PF020B and manufacturer as Microchip. The
device information can be read from executing an 8-bit
command, 90H or ABH, followed by address bits [A

]. Following the Read-ID instruction, the manufac-

A

0

turer’s ID is located in address 00000H and the device
ID is located in address 00001H. Once the device is in

23

SST25PF020B

Read-ID mode, the manufacturer’s and device ID out­put data toggles between address 00000H and 00001H
until terminated by a low to high transition on CE#.

-

Refer to Tables 4-6 and 4-7 for device identification
data.

FIGURE 4-21: READ-ID SEQUENCE

TABLE 4-7: PRODUCT IDENTIFICATION

Address Data

Manufacturer’s ID 00000H BFH
Device ID

SST25PF020B 00001H 8CH

 2012 Microchip Technology Inc. DS25135A-page 19

SST25PF020B

5.0 ELECTRICAL SPECIFICATIONS

Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maxi­mum Stress Ratings” may cause permanent damage to the device. This is a stress rating only and func­tional operation of the device at these conditions or conditions great er than tho se define d in the o perat ional
sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may
affect device reliability. )

Temperature Under Bias. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C

D. C. Voltage on Any Pin to Ground Potential. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to V

Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . -2.0V to V

Package Power Dissipation Capability (T

= 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W

A

Surface Mount Solder Reflow Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C for 10 seconds

1

Output Short Circuit Current

1. Output shorted for no more than one second. No more than one output shorted at a time.

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA

DD
DD

+0.5V
+2.0V

TABLE 5-1: OPERATING RANGE

Range Ambient Temp V

Commercial 0°C to +70°C 2.3-3.6V

DD

TABLE 5-3: DC OPERATING CHARACTERISTICS

Limits

Symbol Parameter

I

DDR

I

DDR3

I

DDW

I

SB

I

LI

I

LO

V

IL

V

IH

V

OL

V

OL2

V

OH

Read Current 12 mA CE#=0.1 VDD/0.9 VDD@33 MHz, SO=open
Read Current 20 mA CE#=0.1 VDD/0.9 VDD@80 MHz, SO=open
Program and Erase Current 30 mA CE#=V
Standby Current 20 µA CE#=VDD, VIN=VDD or V
Input Leakage Current 1µAVIN=GND to VDD, VDD=VDD Max
Output Leakage Current 1µAV
Input Low Voltage 0.7 V VDD=VDD Min
Input High Voltage 0.7 V

DD

Output Low Voltage 0.2 V IOL=100 µA, VDD=VDD Min
Output Low Voltage 0.4 V IOL=1.6 mA, VDD=VDD Min
Output High Voltage VDD-0.2 V IOH=-100 µA, VDD=VDD Min

TABLE 5-2: AC CONDITIONS OF TEST

Input Rise/Fall Time Output Load

SS

= 30 pF

L

5ns C

1. See Figures 5-6 and 5-7

Test ConditionsMin Max Units

DD

=GND to VDD, VDD=VDD Max

OUT

V VDD=VDD Max

1

DS25135A-page 20  2012 Microchip Technology Inc.

SST25PF020B

TABLE 5-4: CAPACITANCE (T

= 25°C, F=1 MHZ, OTHER PINS OPEN)

A

Parameter Description Test Condit ion Maximum

1

C

OUT

1

C

IN

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

Output Pin Capacitance V

= 0V 12 pF

OUT

Input Capacitance VIN = 0V 6 pF

TABLE 5-5: RELIABILITY CHARACTERISTICS

Symbol Parameter Minimum Specification Units Test Method

1

N

END

1

T

DR

1

I

LTH

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

Endurance 10,000 Cycles JEDEC Standard A117
Data Retention 100 Years JEDEC Standard A103
Latch Up 100 + I

DD

mA JEDEC Standard 78

TABLE 5-6: AC OPERATING CHARACTERISTICS, 2.3-2.7V

25 MHz 50 MHz

Symbol Parameter

1

F

CLK

T

SCKH

T

SCKL

T

SCKR

T

SCKF

T

CES

T

CEH

T

CHS

T

CHH

T

CPH

T

CHZ

T

CLZ

T

DS

T

DH

T

HLS

T

HHS

T

HLH

T

HHH

T

HZ

T

LZ

T

OH

T

V

T

SE

T

BE

T

SCE

T

BP

2
2
2

2

Serial Clock Frequency 25 50 MHz
Serial Clock High Time 18 9 ns
Serial Clock Low Time 18 9 ns
Serial Clock Rise Time (Slew Rate) 0.1 0.1 V/ns
Serial Clock Fall Time (Slew Rate) 0.1 0.1 V/ns
CE# Active Setup Time 55ns
CE# Active Hold Time 55ns
CE# Not Active Setup Time 55ns
CE# Not Active Hold Time 55ns
CE# High Time 50 50 ns
CE# High to High-Z Output 77ns
SCK Low to Low-Z Output 00ns
Data In Setup Time 22ns
Data In Hold Time 44ns
HOLD# Low Setup Time 55ns
HOLD# High Setup Time 55ns
HOLD# Low Hold Time 55ns
HOLD# High Hold Time 55ns
HOLD# Low to High-Z Output 77ns
HOLD# High to Low-Z Output 77ns
Output Hold from SCK Change 00ns
Output Valid from SCK 12 8 ns
Sector-Erase 25 25 ms
Block-Erase 25 25 ms
Chip-Erase 50 50 ms
Byte-Program 10 10 µs

UnitsMinMaxMinMax

1. Maximum clock frequency for Read instruction, 03H, is 25 MHz

2. Relative to SCK

 2012 Microchip Technology Inc. DS25135A-page 21

SST25PF020B

TABLE 5-7: AC OPERATING CHARACTERISTICS, 2.7-3.6V

33 MHz 80 MHz

Symbol Parameter

1

F

CLK

T

SCKH

T

SCKL

T

SCKR

T

SCKF

T

CES

T

CEH

T

CHS

T

CHH

T

CPH

T

CHZ

T

CLZ

T

DS

T

DH

T

HLS

T

HHS

T

HLH

T

HHH

T

HZ

T

LZ

T

OH

T

V

T

SE

T

BE

T

SCE

T

BP

Serial Clock Frequency 33 80 MHz
Serial Clock High Time 13 6 ns
Serial Clock Low Time 13 6 ns

2

Serial Clock Rise Time (Slew Rate) 0.1 0.1 V/ns
Serial Clock Fall Time (Slew Rate) 0.1 0.1 V/ns

3

CE# Active Setup Time 55ns

3

CE# Active Hold Time 55ns

3

CE# Not Active Setup Time 55ns

3

CE# Not Active Hold Time 55ns
CE# High Time 50 50 ns
CE# High to High-Z Output 15 7 ns
SCK Low to Low-Z Output 00ns
Data In Setup Time 22ns
Data In Hold Time 44ns
HOLD# Low Setup Time 55ns
HOLD# High Setup Time 55ns
HOLD# Low Hold Time 55ns
HOLD# High Hold Time 55ns
HOLD# Low to High-Z Output 77ns
HOLD# High to Low-Z Output 77ns
Output Hold from SCK Change 00ns
Output Valid from SCK 10 6 ns
Sector-Erase 25 25 ms
Block-Erase 25 25 ms
Chip-Erase 50 50 ms
Byte-Program 10 10 µs

UnitsMin Max Min Max

1. Maximum clock frequency for Read Instruction, 03H, is 33 MHz

2. Maximum Rise and Fall time may be limited by T

3. Relative to SCK.

CE#

T

CHH

SCK

SI

SO

T

CES

T

DSTDH

MSB

HIGH-Z

SCKH

and T

T

SCKR

requirements

SCKL

T

SCKF

T

CEH

LSB

HIGH-Z

T

T

CPH

CHS

25135 SerIn.0

FIGURE 5-1: SERIAL INPUT TIMING DIAGRAM

DS25135A-page 22  2012 Microchip Technology Inc.

FIGURE 5-2: SERIAL OUTPUT TIMING DIAGRAM

25135 SerOut.0

CE#

SI

SO

SCK

MSB

T

CLZ

T

V

T

SCKH

T

CHZ

T

OH

T

SCKL

LSB

T

HZ

T

LZ

T

HHH

T

HLS

T

HLH

T

HHS

25135 Hold.0

HOLD#

CE#

SCK

SO

SI

SST25PF020B

FIGURE 5-3: HOLD TIMING DIAGRAM

 2012 Microchip Technology Inc. DS25135A-page 23

SST25PF020B

Time

VDD Min

V

DD

Max

V

DD

Device fully accessible

T

PU-READ

T

PU-WRITE

Chip selection is not allowed.

Commands may not be accepted or properly

interpreted by the device.

25135 PwrUp.0

5.1 Power-Up Specifications

All functionalities and DC specifications are specified
for a V

- 3.0V in less than 300 ms). See Table 5-8 and Figure

5-4 for more information.

TABLE 5-8: RECOMMENDED SYSTEM POWER-UP TIMINGS

Symbol Parameter Minimum Units

T
T

ramp rate of greater than 1V per 100 ms (0V

DD

PU-READ
PU-WRITE

1

1

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

VDD Min to Read Operation 100 µs
VDD Min to Write Operation 100 µs

FIGURE 5-4: POWER-UP TIMING DIAGRAM

TABLE 5-9: RECOMMENDED POWER-UP/-DOWN LIMITS

Limits

Symbol Parameter

T

PF

T

PR

T

OFF

V

OFF

DS25135A-page 24  2012 Microchip Technology Inc.

VDD Falling Time 1100ms/V
VDD Rising Time 0.033 100 ms/V
VDD Off Time 100 ms
VDD Off Level 0.3 V 0V (recommended)

ConditionsMin Max Units

FIGURE 5-5: RECOMMENDED POWER-UP/-DOWN WAVEFORM

25135 F28.1

T

OFF

GND

V

OFF

V

DD

25135 IORef.0

REFERENCE POINTS OUTPUTINPUT

V

HT

V

LT

V

HT

V

LT

V

IHT

V

ILT

AC test inputs are driven at V

IHT

(0.9VDD) for a logic “1” and V

ILT

(0.1VDD) for a logic “0”. Measurement

reference points for inputs and outputs are V

HT

(0.6VDD) and VLT (0.4VDD). Input rise and fall times

Note: V

HT

- V

HIGH

Test

V

LT

- V

LOW

Test

V

IHT

- V

INPUT

HIGH Test

V

ILT

- V

INPUT

LOW Test

25135 TstLd.0

TO TESTER

TO DUT

C

L

SST25PF020B

FIGURE 5-6: AC INPUT/OUTPUT REFERENCE WAVEFORMS

FIGURE 5-7: A TEST LOAD EXAMPLE

 2012 Microchip Technology Inc. DS25135A-page 25

SST25PF020B

PART NO.

XX

XXX

Package

Endurance/

Device

Device: SST25PF020B = 2 Mbit, 2.3-3.6V, Serial Peripheral Inter-

face flash memory

Operating
Frequency:

80 = 80 MHz

Endurance: 4 = 10,000 cycles

Temperature: C = 0°C to +70°C

Package: QAE = WSON (6mm x 5mm), 8-contact

SAE = SOIC (150 mil), 8-lead
Q3AE = USON(3mm x 2mm), 8-contact

Tape and
Reel Flag:

T = Tape and Reel

Valid Combinations:

SST25PF020B-80-4C-QAE
SST25PF020B-80-4C-QAE-T
SST25PF020B-80-4C-SAE
SST25PF020B-80-4C-SAE-T
SST25PF020B-80-4C-Q3AE
SST25PF020B-80-4C-Q3AE-T

XX

Operating

Temperature

X

Tape/Reel
Indicator

Frequency

6.0 PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

DS25135A-page 26  2012 Microchip Technology Inc.

7.0 PACKAGING DIAGRAMS

08-soic-5x6-SA-8

Note: 1. Complies with JEDEC publication 95 MS-012 AA dimensions,

although some dimensions may be more stringent.

2. All linear dimensions are in millimeters (max/min).

3. Coplanarity: 0.1 mm

4. Maximum allowable mold flash is 0.15 mm at the package ends and 0.25 mm between leads.

TOP VIEW

SIDE VIEW

END VIEW

5.0

4.8

6.20

5.80

4.00

3.80

Pin #1

Identifier

0.51

0.33

1.27 BSC

0.25

0.10

1.75

1.35

7°
4 places

0.25

0.19

1.27

0.40

45°

7°

4 places

0°
8°

1mm

SST25PF020B

FIGURE 7-1: 8-LEAD SMALL OUTLINE INTEGRATED CIRCUIT (SOIC) 150MIL BODY WIDTH (5MM X 6MM)

PACKAGE CODE: SA

 2012 Microchip Technology Inc. DS25135A-page 27

SST25PF020B

TOP VIEW BOTTOM VIEW

Pin #1

Corner

5.00 ± 0.10

6.00

± 0.10

Note: 1. All linear dimensions are in millimeters (max/min).

2. Untoleranced dimensions (shown with box surround)
are nominal target dimensions.

3. The external paddle is electrically connected to the
die back-side and possibly to certain VSS leads.
This paddle can be soldered to the PC board;
it is suggested to connect this paddle to the VSS of the unit.
Connection of this paddle to any other voltage potential can
result in shorts and/or electrical malfunction of the device.

SIDE VIEW

0.2

0.05 Max

0.80

0.70

1mm

0.076

4.0

3.4

CROSS SECTION

8-wson-5x6-QA-9.0

FIGURE 7-2: 8-CONTACT VERY-VERY-THIN SMALL OUTLINE NO-LEAD (WSON)

PACKAGE CODE: QA

Pin #1

1.27 BSC

0.48

0.35

0.70

0.50

0.80

0.70

DS25135A-page 28  2012 Microchip Technology Inc.

SST25PF020B

1mm

0.60

0.45

0.08

Pin # 1

3.00

±0.10

Pin #1

(laser

engraved

see note 2)

2.00

±0.10

0.5 BSC

0.2

0.25
±0.05

8-uson-2x2-Q3A-1.1

0.05 Max

See notes

3 &4

1.60

Note: 1. Similar to JEDEC JEP95 MO-252 variant U2030D, though number of contacts and some dimensions may be different.

2. The topside pin #1 indicator is laser engraved; its approximate shape and location is as shown.

3. From the bottom view, the pin #1 indicator may be either a curved indent or a 45-degree chamfer.

4. Untoleranced dimensions are nominal target dimensions.

5. All linear dimensions are in millimeters (max/min).

6. Lead-frame nominal thickness 0.127mm or 0.15mm (supplier-dependent).

2.45

0.40
±0.05

0.35
±0.05

0.15 max

FIGURE 7-3: 8-CONTACT ULTRA-THIN SMALL OUTLINE NO-LEAD (USON)

PACKAGE CODE: Q3A

 2012 Microchip Technology Inc. DS25135A-page 29

SST25PF020B

TABLE 7-1: REVISION HISTORY

Revision Description Date

A

• Initial release of spec

Nov 2012

DS25135A-page 30  2012 Microchip Technology Inc.

SST25PF020B

THE MICROCHIP WEB SITE

Microchip provides online support via our WWW site at

www.microchip.com. This web site is used as a means

to make files and information easily available to
customers. Accessible by using your favorite Internet
browser, the web site contains the following
information:

• Product Support – Data sheets and errata,
application notes and sample programs, design
resources, user’s guides and hardware support
documents, latest software releases and archived
software

• General Technical Support – Frequently Asked
Questions (FAQs), technical support requests,
online discussion groups, Microchip consultant
program member listing

• Business of Microchip – Product selector and
ordering guides, latest Microchip press releases,
listing of seminars and events, listings of
Microchip sales offices, distributors and factory
representatives

CUSTOMER CHANGE NOTIFICATION
SERVICE

CUSTOMER SUPPORT

Users of Microchip products can receive assistance
through several channels:

• Distributor or Representative

• Local Sales Office

• Field Application Engineer (FAE)

• Technical Support

• Development Systems Information Line
Customers should contact their distributor,

representative or field application engineer (FAE) for
support. Local sales offices are also available to help
customers. A listing of sales offices and locations is
included in the back of this document.

T echnical support is available through the web site
at: http://microchip.com/support

Microchip’s customer notification service helps keep
customers current on Microchip products. Subscribers
will receive e-mail notification whenever there are
changes, updates, revisions or errata related to a
specified product family or development tool of interest.

To register, access the Microchip web site at

www.microchip.com. Under “Support”, click on

“Customer Change Notification” and follow the
registration instructions.

 2012 Microchip Technology Inc. DS25135A-page 31

Note the following details of the code protection feature on Microchip devices:

YSTEM

CERTIFIED BY DNV

== ISO/TS 16949 ==

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today , when used in the
intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.

QUALITY MANAGEMENT S

Trademarks

The Microchip name and logo, the Microchip logo, dsPIC,
FlashFlex, K
PICSTART, PIC
and UNI/O are registered trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.

FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MTP, SEEVAL and The Embedded Control Solutions
Company are registered trademarks of Microchip Technology
Incorporated in the U.S.A.

Silicon Storage Technology is a registered trademark of
Microchip Technology Inc. in other countries.

Analog-for-the-Digital Age, Application Maestro, BodyCom,
chipKIT, chipKIT logo, CodeGuard, dsPICDEM,
dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial
Programming, ICSP, Mindi, MiWi, MPASM, MPF, MPLAB
Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code
Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
PICtail, REAL ICE, rfLAB, Select Mode, SQI, Serial Quad I/O,
Total Endurance, TSHARC, UniWinDriver, WiperLock, ZENA
and Z-Scale are trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.

GestIC and ULPP are registered trademarks of Microchip
Technology Germany II GmbH & Co. & KG, a subsidiary of
Microchip Technology Inc., in other countries.

All other trademarks mentioned herein are property of their
respective companies.

© 2012, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.

Printed on recycled paper.

ISBN: 978-1-62076-678-1

Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
T empe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the desig n
and manufacture of development systems is ISO 9001:2000 certified.

EELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,

32

logo, rfPIC, SST, SST Logo, SuperFlash

®

MCUs and dsPIC® DSCs, KEELOQ

®

code hopping

 2012 Microchip Technology Inc. DS25135A-page 32

Worldwide Sales and Service

AMERICAS

Corporate Office

2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: [phone]
Fax: [phone]
Technical Support:

http://www.microchip.com/
support

Web Address:

www.microchip.com

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Tel: [phone]
Fax: [phone]

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Toronto

Mississauga, Ontario,
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ASIA/PACIFIC

Asia Pacific Office

Suites 3707-14, 37th Floor
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India - Bangalore

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Fax: [phone] or
82-2-558-5934

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Thailand - Bangkok

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EUROPE

Austria - Wels

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 2012 Microchip Technology Inc. DS25135A-page 33