Datasheet SPT9712 Datasheet (Fairchild Semiconductor)

SPT9712

12-BIT, 100 MWPS ECL D/A CONVER TER

TECHNICAL DATA

FEBRUARY 15, 2001

FEATURES

• 12-Bit, 100 MWPS digital-to-analog converter

• ECL compatibility

• Low power: 600 mW

• 1/2 LSB DNL

• 40 MHz multiplying bandwidth

• Industrial temperature range

• Superior performance over AD9712
– Improved settling time of 13 ns
– Improved glitch energy 15 pV-s
– Master-slave latches

GENERAL DESCRIPTION

The SPT9712 is a 12-bit, 100 MWPS digital-to-analog
converter designed for direct digital synthesis, high reso­lution imaging, and arbitrary wavef orm generation applica­tions.

This device is pin-for-pin compatib le with the AD9712 with
significantly improved performance. The only difference
between the SPT9712 and the AD9712 is that the Latch
Enable (LE, pin 26) for the SPT9712 is rising-edge trig-

APPLICATIONS

• Fast frequency hopping spread spectrum radios

• Direct sequence spread spectrum radios

• Microwave and satellite modems

• Test & measurement instrumentation

gered (see figure 1), whereas the Latch Enable (LE, pin

26) for the AD9712 functions in the transparent mode.
The SPT9712 is an ECL-compatible device. It features a

fast settling time of 13 ns and low glitch impulse energy of
15 pV-s, which results in excellent spurious-free dynamic
range characteristics.

The SPT9712 is available in a 28-lead PLCC package in
the industrial temperature range (–40 to +85 °C).

BLOCK DIAGRAM

R

Control Amp In

Ref Out

Latch Enable

Digital
Inputs

D1

through

D12

Set

+

Control

Amp



(MSB)

Decoders

and

Drivers

(LSB)

Internal
Voltage

Reference

Network

Latches

Switch

Control
Amp Out

Ref In

I

Out

I

Out

ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur)1 25 °C

Supply Voltages

Negative Supply Voltage (VEE) .............................. –7 V

A/D Ground Voltage Differential ...........................0.5 V

Input Voltages

Digital Input Voltage

(D1–D12, Latch Enable)............................... 0 V to V

Control Amp Input Voltage Range...............0 V to –4 V

Reference Input Voltage Range (V

) ........0 V to V

REF

Output Currents

Internal Reference Output Current.................... 500 µA

Control Amplifier Output Current.....................±2.5 mA

Temperature

Operating Temperature .......................... –40 to +85 °C

EE

Junction Temperature ...................................... +150 °C

Lead, Soldering (10 seconds) .........................+300 °C

EE

Storage ................................................ –65 to +150 °C

Note: 1. Operation at any Absolute Maximum Rating is not implied. See

Electrical Specifications for proper nominal applied conditions
in typical applications.

ELECTRICAL SPECIFICATIONS

TA = T

PARAMETERS CONDITIONS LEVEL MIN TYP MAX MIN TYP MAX UNITS
DC Performance

– T

, V

MIN

MAX

= –5.2 V, R

EE

= 7.5 kΩ, Control Amp In = Ref Out, V

Set

= 0 V, unless otherwise specified.

OUT

TEST TEST SPT9712A SPT9712B

Resolution 12 12 Bits
Differential Linearity I ±0.5 ±0.75 ±1.0 ±1.25 LSB
Differential Linearity Max at Full Temp. VI ±1.5 ±2.0 LSB
Integral Linearity Best Fit I ±0.75 ±1.0 ±1.0 ±1.5 LSB
Integral Linearity Max at Full Temp. VI ±1.75 ±2.0 LSB
Output Capacitance +25 °C V 10 10 pF
Gain Error

1

+25 °C I 1.0 5.0 1.0 5.0 % FS

Full Temp. VI 8.0 8 . 0 % FS
Gain Error Tempco Full Temp. V 150 150 PPM/°C
Zero-Scale Offset Error +25 °C I 0.5 2.5 0.5 2.5 µA

Full Temp. VI 5.0 5.0 µA
Offset Drift Coefficient Full Temp. V 0.01 0.01 µA/°C
Output Compliance Voltage +25 °C IV –1.2 +2.0 –1.2 +2.0 V
Equivalent Output Resistance +25 °C IV 0.8 1.0 1.2 0.8 1.0 1.2 kΩ

Dynamic Performance

Conversion Rate +25 °C IV 100 1 00 MWPS
Settling Time t
Output Propagation Delay t
Glitch Energy
Full Scale Output Current

2

ST

4

D

5

Spurious-Free Dynamic Range

+25 °C V 13 13 ns

3

+25 °C V 1 1 ns

+25 °C V 15 15 pV-s

+25 °C V 20.48 20.48 mA

6

+25 °C

1.23 MHz; 10 MWPS 2 MHz Span V 70 70 dBc

5.055 MHz; 20 MWPS 2 MHz Span V 68 68 dBc

10.1 MHz; 50 MWPS 2 MHz Span V 68 68 dBc
16 MHz; 40 MWPS 10 MHz Span V 68 68 d Bc

Rise Time / Fall Time R

= 50 Ω V2 2ns

L

Power Supply Requirements

Negative Supply Voltage IV –5.46 –5.2 –4.94 –5.46 –5.2 –4.94 V
Negative Supply Current (–5.2 V) +25 °C I 115 140 115 140 m A

Full Temp VI 148 148 mA
Nominal Power Dissipation V 600 600 m W
Power Supply Rejection Ratio ±5% of V

EE

I 30 100 30 100 µA/V

External Ref, +25 °C

1

Gain is measured as a ratio of the full-scale current to I

2

Measured as voltage at mid-scale transition to ±0.024%; RL=50 Ω.

3

Measured from the rising edge of Latch Enable to where the output signal has left a 1 LSB error band.

4

Glitch is measured as the largest single transient.

5

Calculated using IFS = 128 x (Control Amp In / R

6

SFDR is defined as the difference in signal energy between the fundamental and worst case spurious frequencies in the output spectrum window ,
which is centered at the fundamental frequency and covers the indicated span.

Set

. The ratio is nominally 128.

Set

)

SPT9712

2 2/15/01

ELECTRICAL SPECIFICATIONS

TA = T

MIN

– T

MAX

, V

EE

= –5.2 V, R

= 7.5 kΩ, Control Amp In = Ref Out, V

SET

= 0 V, unless otherwise specified.

OUT

TEST TEST SPT9712A SPT9712B

PARAMETERS CONDITIONS LEVEL MIN TYP MAX MIN TYP MAX UNITS
Voltage Input and Control

Reference Input Impedance +25 °C V 3 3 kΩ
Ref. Multiplying Bandwidth +25 °C V 40 40 MHz
Internal Reference Voltage VI –1.15 –1.20 –1.25 –1.15 –1.20 –1.25 V
Internal Reference Voltage Dr ift V 50 50 ppm/°C
Amplifier Input Impedance +25 °C V 3 3 MΩ
Amplifier Input Bandwidth +25 °C V 1 1 MHz

Digital Inputs

Logic 1 Voltage Full Temp. VI –1.0 –0.8 –1.0 –0.8 V
Logic 0 Voltage Full Temp. VI –1.7 –1.5 –1.7 –1.5 V
Logic 1 Current Full Temp. VI 20 20 µA
Logic 0 Current Full Temp. VI 10 10 µA
Input Capacitance +25 °C V 3 3 pF
Input Setup Time – t
Input Setup Time – t
Input Hold Time – t
Input Hold Time – t
Latch Pulse Width – t

S

S
H
H

PWL, tPWH

TEST LEVEL CODES

All electrical characteristics are subject to the
following conditions:

All parameters having min/max specifications
are guaranteed. The Test Level column indi­cates the specific device testing actually per­formed during production and Quality Assur­ance inspection. Any blank section in the data
column indicates that the specification is not
tested at the specified condition.

+25 °C IV 3 2 3 2 ns
Full Temp. IV 3.5 3.5 ns
+25 °C IV 0.5 0 0 .5 0 ns
Full Temp. IV 0.5 0.5 ns
+25 °C IV 5.0 4.0 5. 0 4.0 ns

LEVEL TEST PROCEDURE

I 100% production tested at the specified temperature.

II 100% production tested at T

specified temperatures.

III QA sample tested only at the specified temperatures.

IV Parameter is guaranteed (but not tested) by design and characteri-

zation data.

V Parameter is a typical value for information pur poses only.

VI 100% production tested at TA = +25 °C. Parameter is guaranteed

= +25 °C, and sample tested at the

A

over specified temperature range.

SPT9712

3 2/15/01

THEORY OF OPERATION

VOLT AGE REFERENCE

The SPT9712 uses a segmented architecture incorporat­ing most significant bit (MSB) decoding. The four MSBs
(D1–D4) are decoded to thermometer code lines to drive
15 discrete current sinks. For the eight least significant
bits (LSBs), D5 and D6 are binary weighted and D7–D12
are applied to the R-2R network. The 12-bit decoded data
is input to internal master/slave latches. The latched data
is input to the switching network and is presented on the
output pins as complementary current outputs.

TYPICAL INTERFACE CIRCUIT

The SPT9712 requires few external components to
achieve the stated operation and performance. Figure 2
shows the typical interface requirements when using the
SPT9712 in normal circuit operation. The following sec­tions provide descriptions of the pin functions and outline
critical performance criteria to consider for achieving opti­mal device performance.

POWER SUPPLIES AND GR OUNDING

The SPT9712 requires the use of a single –5.2 V supply.
All supplies should be treated as analog supply sources.
This means the ground returns of the device should be
connected to the analog ground plane. All supply pins
should be bypassed with .01 µF and 10 µF decoupling
capacitors as close to the device as possible.

The two grounds available on the SPT9712 are DGND
and AGND . These grounds are not tied together internal to
the device. The use of ground planes is recommended to
achieve the best perf ormance of the SPT9712. All g round,
reference and analog output pins should be tied directly to
the DAC ground plane. The DAC and system ground
planes should be separate from each other and only con­nected at a single point through a ferrite bead to reduce
ground noise pickup.

DIGITAL INPUTS AND TIMING

The SPT9712 uses single-ended, 10K ECL-compatible
inputs for data inputs D1–D12 and Latch Enable. It also
employs master/slave latches to simplify digital interface
timing requirements and reduce glitch energy by synchro­nizing the current switches. This is an improvement over
the AD9712, which typically requires external latches for
digital input synchronization.

When using the internal reference, Ref Out should be con­nected to Control Amp In and decoupled with a 0.1 µF
capacitor. Control Amp Out should be connected to Ref In
and decoupled to the analog supply. (See figure 2.)

Full-scale output current is determined by Control Amp In
and R

using the following formula:

Set

I

(FS) = (Control Amp In / R

Out

) x 128

Set

(Current Out is a constant 128 factor of the
reference current)

The internal reference is typically –1.20 V with a tolerance
of ±0.05 V and a typical drift of 50 ppm/°C. If greater accu­racy or temperature stability is required, an external refer­ence can be utilized.

OUTPUTS

The output of the SPT9712 is comprised of complemen­tary current sinks, I
at either I

Out

or I
The sum of the two is always equal to the full-scale output
current minus one LSB.

By terminating the output current through a resistive load
to ground, an associated voltage develops. The effective
resistive load (R
(R

) in parallel with the resistive load (RL). The voltage

Out

which develops can be determined using the following
formulas:

Control Amp Out = –1.2 V, and R
I

(FS) = (–1.2 V / 7.5 kΩ) x 128 = –20.48 mA

Out

RL = 51 Ω
R

= 1.0 kΩ

Out

R

= 51 Ω || 1.0 kΩ = 48.52 Ω

Eff

V

= R

Out

Eff

x I

The resistive load of the SPT9712 can be modified to in­corporate a wide variety of signal levels. Howev er , optimal
device performance is achieved when the outputs are
equivalently loaded.

and I

Out

are based upon the digital input code.

Out

) is the output resistance of the device

Eff

(FS) = 48.52 Ω x –20.48 mA

Out

. The output current levels

Out

= 7.5 kΩ

Set

= –0.994 V

Referring to figure 1, data is latched into the DAC on the
rising edge of the latch enable clock with the associated
setup and hold times. The output transition occurs after a
typical 1 ns propagation delay and settles to within ±1 LSB
in typically 13 ns. Because of the SPT9712’s rising-edge
triggering, no timing changes are required when replacing
an AD9712 operating in the transparent mode.

SPT9712

4 2/15/01

Figure 1 – Timing Diagram

Latch

Enable

1.3 V

t

PWL

t

PWH

1.3 V

OUT

OUT+

Figure 2 – Typical Interface Circuit

5.2 V

Digital Inputs

Clock
Input

System

GND

t

S

Data Inputs

10 µF

28

D1 (MSB)

1

D2

2

D3

3

D4

4

D5

5

D6

6

D7

7

D8

8

ECL Logic Drivers

D9

9

D10

10

D11

11

D12 (LSB)

26

LE

t

H

t

D

t

1/2 LSB

0.1 µF

0.001 µF

23

DV

N/C

EE

SPT9712

DGND AGND Ref GND

27 13 22

AV

Ref In

Control

Amp Out

Ref Out

Control
Amp In

ST

R

I

15,2512,21

EE

Set

Out

I

Out

0.1 µF

0.001 µF

17

18

20

19

24

R

Set

16

R

L

R

L

14

0.1 µF

20 W

1 LSB

0.1 µF

V

Out

SPT9712

5 2/15/01

PACKAGE OUTLINE

28-Lead PLCC

C

Pin 1

TOP

VIEW

A

B

H

G

I

F

E

D

INCHES MILLIMETERS

SYMBOL MIN MAX MIN MAX

A 0.452 0.456 11.48 11.58
B 0.485 0.495 12.32 12.57
C 30° 30°
D 0.170 0.179 4.32 4.55
E 0.020 0.025 0.51 0.64
F 0.031 0.035 0.79 0.89
G 0.013 0.021 0.33 0.53
H 0.048 0.052 1.22 1.32

I 0.410 0.430 10.41 10.92

Pin 1

BOTTOM

VIEW

SPT9712

6 2/15/01

PIN ASSIGNMENTS PIN FUNCTIONS

D6

D7

D8

D9

D10

D11

(LSB) D12

Latch Enable

(MSB) D1

DGND

D2

D3

D4

D5

26

27

28

1

2

3

4

25

5

6

7

8

9

10

11

12

Digital V

EE

PLCC

15

14

13

Analog Return

I

Out

Analog V

EE

I

Out

18

17

16

Ref In

Control Amp Out

Analog V

24

R

Set

23

N/C

22

Ref GND

21

Digital V

20

Ref Out

19

Control Amp In

EE

EE

Name Function

Out+ Analog Current Output
Out– Complementary Analog Current Output
D1–D12 Digital Input Bits (D12 is the LSB)
Latch Enable Latch Control Line
Ref In Voltage Reference Input
Ref Out Internal Voltage Reference Output

Normally Connected to Control Amp In

Ref GND Ground Return For Internal Voltage

Reference and Amplifier

Control Amp In Normally Connected to Ref Out If Not

Connected to External Reference

Control Amp Out Output of Internal Control Amplifier

Normally Connected to Ref In

1

R

Set

Connection for External Resistance
Reference When Using Internal Amplifier

Nominally 7.5 kΩ
Analog Return Analog Return Ground
Analog V
Digital V

EE

EE

Analog Negative Supply (–5.2 V)

Digital Negative Supply (–5.2 V)
DGND Digital Ground Return
N/C Not Connected

1Full-Scale Current Out = 128 (Control Amp In / R

Set

)

ORDERING INFORMATION

PART NUMBER DNL/INL TEMPERATURE RANGE PACKAGE

SPT9712AIP ±0.75/±1.0 –40 to +85 °C 28L PLCC
SPT9712BIP ±1.25/±1.5 –40 to +85 °C 28L PLCC

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FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO
IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR
USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR
THE RIGHTS OF OTHERS.

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WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein:

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SPT9712

7 2/15/01