Datasheet SPT9693SCC, SPT9693SCP, SPT9693SCU Datasheet (SPT)

FEATURES

SPT9693

WIDE INPUT V O LTA GE, JFET COMPARATOR

TECHNICAL DATA

MARCH 1, 2001

APPLICATIONS

• Common mode range –3.0 to +8.0 V

• Low input bias current <100 pA

• Propagation delay 1.5 ns (max)

• Low offset ±25 mV

• Low feedthrough and crosstalk

• Differential latch control

GENERAL DESCRIPTION

The SPT9693 is a high-speed, wide common mode volt­age, JFET input, dual comparator. It is designed for appli­cations that measure critical timing parameters in which
wide common mode input voltages of –3.0 to +8.0 V are
required. Propagation delays are constant for overdrives
greater than 50 mV.

JFET inputs reduce the input bias currents to the
nanoamp level, eliminating the need for input drivers and

BLOCK DIAGRAM

Q

Q

A

A

• Automated test equipment

• High-speed instrumentation

• Window comparators

• High-speed timing

• Line receivers

• High-speed triggers

• Threshold detection

• Peak detection

buffers in most applications. The device has differential
analog inputs and complementary logic outputs com­patible with ECL systems. Each comparator has a
complementary latch enable control that can be driven by
standard ECL logic.

The SPT9693 is available in 20-contact LCC and 20-lead
PLCC packages over the commercial temperature range.
It is also available in die form.

Q

Q

B

GND

B

B

AV

GND

LE

LE

N/C

EE

(A)

A

A

A

AVCC(A)

IN

+IN

A

+IN

A

IN

B

B

LE

LE

N/C

AV

AV

B

B

EE

CC

(B)

(B)

Signal Processing Technologies, Inc.

4755 Forge Road, Colorado Springs, Colorado 80907, USA

Phone: [phone] Fax: [phone] Web Site: http://www .spt.com e-mail: [e-mail]

ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur)1 25 °C

Supply Voltages (Measured to GND)

Positive Supply Voltage (AVCC) ............–0.5 to +11.0 V

Negative Supply Voltage (AVEE)........... –11.0 to +0.5 V

Input Voltages

Input Common Mode Voltage ................–6 to +AVCC+1

Differential Input Voltage ....................–12.0 to +12.0 V

Input Voltage, Latch Controls ......................–6 to 0.5 V

V

to AVCC Differential Voltage ...............–16 to +1.0 V

IN

VIN to AVEE Differential Voltage ...............+4 to +21.0 V

Output

Output Current ................................................... 30 mA

Temperature

Operating Temperature, ambient ................ 0 to +70 °C

junction......................+150 °C

Lead Temperature, (soldering 60 seconds) ..... +300 °C

Storage Temperature............................ –65 to +150 °C

Note: 1. Operation at any Absolute Maximum Rating is not implied. See

Electrical Specifications for proper nominal applied conditions
in typical applications. Application of m ultiple maximum rating
conditions at the same time may damage the device.

ELECTRICAL SPECIFICATIONS

TA = +25 °C, A VCC = +10 V, AVEE = –10.0 V, RL = 50 Ohm to –2 V, unless otherwise specified.

PARAMETERS CONDITIONS LEVEL MIN TYP MAX UNITS
DC CHARACTERISTICS

Input Offset Voltage V
Offset Voltage Tempco V 50 µV/°C

Input Bias Current T
Input Bias Current T
Input Offset Current V ±1.0 nA
Positive Supply Current (Dual) AV

Negative Supply Current (Dual) AVEE=–10.0 V I 40 55 mA
Positive Supply Voltage, AV

Negative Supply Voltage, AV
Input Common Mode Range I –3.0 +8.0 V
Latch Enable

Common Mode Range IV –2.0 0 V
Differential Voltage Range I ±10 V
Open Loop Gain V 52 dB
Differential Input Resistance V 2 GΩ
Input Capacitance V 1.0 pF
Power Supply Sensitivity V 60 dB
Common Mode Rejection Ratio I 50 60 dB

Power Dissipation Dual I 430 610 m W
Output High Level ECL 50 Ohms to –2 V I –.98 –.70 V

Output Low Level ECL 50 Ohms to –2 V I –1.95 –1.65 V

CC

TEST TEST

(Common Mode) = 0 I –25 0.0 +25 mV

IN

T

MIN<TA<TMAX

MIN<TA<TMAX

VIN (Common Mode) = –3 to +7 V

MIN<TA<TMAX

VIN (Common Mode) = +7 to +8 V
T

MIN<TA<TMAX

=10 V I 3 6 mA

CC

EE

T

MIN<TA<TMAX

IV –25 0 . 0 +25 mV

I ±10 ±100 nA
I ±50 ±150 nA

V ±10 nA

IV 9.75 10.0 10.25 V
IV –9.75 –10.0 –10.25 V

IV 45 55 dB

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SPT9693

2 3/1/01

ELECTRICAL SPECIFICATIONS

TA = +25 °C, A VCC = +10 V, AVEE = –10.0 V, RL = 50 Ohm to –2 V, unless otherwise specified.

TEST TEST

PARAMETERS CONDITIONS LEVEL MIN TYP MAX UNITS
AC ELECTRICAL PARAMETERS

Propagation Delay
Propagation Delay Tempco V 2 ps/ °C
Propagation Delay Skew (A vs B) V 100 ps
Delay Dispersion from V 50 ps

Input Direction
Delay Dispersion from V 60 ps

Input Common Mode
Latch Set-up Time V 500 ps
Latch to Output Delay 50 mV O.D. V 500 ps
Latch Pulse Width V 500 ps
Latch Hold Time V 0 ps
Rise Time 20% to 80% V 0.45 ns
Fall Time 20% to 80% V 0.45 ns
Slew Rate V 5 V/ns

1

Valid f or both high-to-low and low-to-high transitions

1

50 mV O.D., Slew 10 V/ns IV .75 1.25 1.50 n s

TEST LEVEL CODES

All electrical characteristics are subject to the
following conditions:

All parameters having min/max specifications
are guaranteed. The Test Level column indi­cates the specific device testing actually per­formed during production and Quality Assur­ance inspection. Any blank section in the data
column indicates that the specification is not
tested at the specified condition.

LEVEL TEST PROCEDURE

I 100% production tested at the specified temperature.

II 100% production tested at TA = +25 °C, and sample tested at the

specified temperatures.
III QA sample tested only at the specified temperatures.
IV Parameter is guaranteed (but not tested) by design and characteri-

zation data.

V Parameter is a typical value for information purposes only.

VI 100% production tested at TA = +25 °C. Parameter is guaranteed

over specified temperature range.

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TYPICAL PERFORMANCE CHARACTERISTICS

INPUT OFFSET VOLTAGE vs COMMON MODE VOLTAGE

(T=+25 °C)

+10.0

+6.0

+2.0

2.0

INPUT OFFSET VOLTAGE (mV)

6.0

10.0

3.0 1.6 +0.8 +3.2 +5.6 +8.0

COMMON MODE VOLTAGE (V)

PROPAGATION DELAY TIME vs TEMPERATURE

INPUT BIAS CURRENT vs COMMON MODE VOLTAGE

(+25 °C)

100

10

1.0

0.1

INPUT BIAS CURRENT (nA)

0.01

0.001
3.0 1.6 +0.8 +3.2 +5.6 +8.0

COMMON MODE VOLTAGE (V)

DELAY DISPERSION vs INPUT PULSE WIDTH

1600

1500

1400

1300

PROPAGATION DELAY TIME (ps)

1200

0 +25 +50

Slope  2 ps/ °C

+75 +100

TEMPERATURE (°C)

+125 +150

50

40

30

20

DELAY DISPERSION (ps)

10

0 500 1000 1500 2000 30002500

INPUT PULSE WIDTH (ps)

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TYPICAL PERFORMANCE CHARACTERISTICS

HYSTERESIS vs DLATCH VOLTAGE

V Hysteresis (mV)

RISE AND FALL OF OUTPUTS vs TIME CROSSOVER

.90

50

40

30

HYSTERESIS (mV)

20

10

30 20 10 0 10 3020

PROPAGATION DELAY vs INPUT

OVERDRIVE VOLTAGE

1500

1400

Input Slew Rates

= 1 V/ns

= 2 V/ns
= 5 V/ns

VLEVLE

(mV)

1.10

1.30

1.50

OUTPUT RISE & FALL (V)

1.70

1.90

1.1 1.5 1.9 2.3 2.7

TIME (ns)

PROPAGATION DELAY vs

COMMON MODE INPUT VOLTAGE

1600

1500

3.5

1300

1200

PROPAGATION DELAY TIME (ps)

1100

SPT

50 100 150 200 250 300 350 400

V

(mV)

OD

1400

1300

PROPAGATION DELAY TIME (ps)

1200

4 2 0

+2 +4

VIN, cm (V)

+6 +8

SPT9693

5 3/1/01

GENERAL INFORMATION



The SPT9693 is an ultrahigh-speed dual voltage com­parator. It offers tight absolute characteristics. The device
has differential analog inputs and complementary logic
outputs compatible with ECL systems. The output stage is
adequate for driving terminated 50 ohm transmission
lines.

Single-channel operation can be accomplished by floating

all

pins (including the ground and supply pins) of the un­used comparator. P o wer dissipation during single-channel
operation is 50% of the dissipation during dual-channel
operation.

This comparator offers the following improvements over
existing devices:

The SPT9693 has a complementary latch enable control
for each comparator. Both should be dr iven by standard
ECL logic levels.

A common mode voltage range of –3 V to +8 V is achie ved
by a proprietary JFET input design, which requires a
separate negative power supply (AV

EE

).

The dual comparators have separate AVCC, AVEE, and
grounds for each comparator to achieve high crosstalk
rejection.

Figure 1 – Internal Function Diagram

+IN

IN

+

AMP



PRE

LATCH

• Ultra low input bias current and input current offset

• Common mode voltage of –3 to +8 V

• Short propagation delays

• Excellent input and output rejection between

comparator channels

• Improved input protection reliability due to JFET input

stage design
All of these combined features produce high-performance

products with timing stability and repeatability for large
system precision.

Q

ECL

OUT

Q

REF

1

AV

EE

V

CC

GND

CLK

BUF

LE LE

REF

2

SPT9693

SPT

6 3/1/01

TYPICAL INTERFACE CIRCUIT

LE

LE

+



V

C

AV

CC

GND

AV

EE

V

IN

V

Ref

.1 µF

.1 µF

Q Output

D2

D2

D2

D2

D1

550 W

» 5 V

Notes:

1) D1 = 1N5231B or 1N751 or equivalent.

2) D2 = 1N914 or equivalent.

3) At no time should both inputs be allowed to float with power applied
to the device. At least one of the inputs should be tied to a voltage
within the common mode range (3.0 to +8.0 V) to prevent possible
damage to the device. Additional protection diodes D2 should be
used on the inputs if there is the possibility of exceeding the absolute
maximum ratings.

0.1 µF

2 V

Q Output

100 W 0 to 200 W

2 V

1.3 V

R

L

50 W

0.1 µF

R

L

50 W

The typical interface circuit using the comparator is shown
in figure 2. Although it needs few external components
and is easy to apply, there are several conditions that
should be noted to achieve optimal perf ormance. The v ery
high operating speeds of the comparator require careful
layout, decoupling of supplies , and proper design of trans­mission lines.

Since the SPT9693 comparator is a very high-frequency
and high-gain device, certain layout rules must be f ollowed
to avoid oscillations. The comparator should be soldered
to the board with component lead lengths kept as short as
possible. A ground plane should be used, while the input
impedance to the part is kept as low as possible, to de­crease parasitic feedback. If the output board traces are

techniques must be employed to prevent ringing on the
output waveform. Also, the microstriplines must be ter mi­nated at the far end with the characteristic impedance of
the line to prevent reflections. All supply voltages should
be decoupled with high-frequency capacitors as close to
the device as possible. If using the SPT9693 as a single
comparator, the outputs of the inactiv e comparator can be
grounded, left open or terminated with 50 ohms to –2 V . All
outputs on the active comparator, whether used or un­used, should have identical terminations to minimize
ground current switching transients.

All ground pins should be connected to the same ground
plane to further improve noise immunity and shielding.
Unused outputs must be terminated with 50 ohms to
ground.

longer than approximately half an inch, microstripline

Figure 2 – SPT9693 Typical Interface Circuit Figure 3 – SPT9693 Typical Interface Circuit

with Hysteresis

EE

CC

AV

AV

GND

D2

D2

V

IN

D2

V

Ref

D1

550 W

Notes:

1) D1 = 1N5231B or 1N751 or equivalent.

2) D2 = 1N914 or equivalent.

3) At no time should both inputs be allowed to float with power applied

D2

V

» 5 V

C

to the device. At least one of the inputs should be tied to a voltage
within the common mode range (3.0 to +8.0 V) to prevent possible
damage to the device. Additional protection diodes D2 should be used
on the inputs if there is the possibility of exceeding the absolute
maximum ratings.

.1 µF

.1 µF

+

LE



LE

50 W

R

L

2 V

R

L

50 W

Q Output

Q Output

.1 µF

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SPT9693

7 3/1/01

TIMING INFORMATION

The timing diagram for the comparator is shown in figure

4. If LE is high and LE low in the SPT9693, the compar ator
tracks the input difference voltage. When LE is driven low
and LE high, the comparator outputs are latched into their
existing logic states.

The leading edge of the input signal (which consists of a
150 mV overdrive voltage) changes the comparator out­put after a time of t
must be maintained for a time tS (set-up time) before the
LE falling edge and LE rising edge and held for time t

Figure 4 – Timing Diagram

or t

pdL

Latch Enable

Latch Enable

Differential

Input Voltage

Output Q

(Q or Q). The input signal

pdH

t

S

V

OD

V

IN

t

H

t

pdL

after the falling edge for the comparator to accept data.
After tH, the output ignores the input status until the latch
is strobed again. A minimum latch pulse width of tpL is
needed for strobe operation, and the output transitions
occur after a time of t

pLOH

or t

pLOL

.

The set-up and hold times are a measure of the time
required for an input signal to propagate through the first
stage of the comparator to reach the latching circuitry.
Input signals occurring before t

will be detected and held;

S

those occurring after tH will not be detected. Changes
between tS and tH may not be detected.

H

50%

t

pL

V

±V

Ref

OS

t

pLOH

50%

Output Q

t

pdH

SWITCHING TERMS (Refer to figure 4)

t

INPUT TO OUTPUT HIGH DELAY – The propaga-

pdH

tion delay measured from the time the input signal
reaches the reference voltage (± the input offset
voltage) to the 50% point of an output LOW to HIGH
transition.

t

INPUT TO OUTPUT LOW DELAY – The propaga-

pdL

tion delay measured from the time the input signal
reaches the reference voltage (± the input offset
voltage) to the 50% point of an output HIGH to LOW
transition.

t

LATCH ENABLE TO OUTPUT HIGH DELAY – The

pLOH

propagation delay measured from the 50% point of
the Latch Enable signal LOW to HIGH transition to
50% point of an output LOW to HIGH transition.

t

LATCH ENABLE TO OUTPUT LOW DELAY – The

pLOL

propagation delay measured from the 50% point of
the Latch Enable signal LOW to HIGH transition to
the 50% point of an output HIGH to LOW transition.

t

pLOL

VIN+ = 300 mV, VOD= 150 mV

t

MINIMUM HOLD TIME – The minimum time after

H

the negative transition of the Latch Enable signal
that the input signal must remain unchanged in order
to be acquired and held at the outputs.

t

MINIMUM LATCH ENABLE PULSE WIDTH – The

pL

minimum time that the Latch Enable signal must be
HIGH in order to acquire an input signal change.

t

MINIMUM SET-UP TIME – The minimum time

S

before the negative transition of the Latch Enable
signal that an input signal change must be present in
order to be acquired and held at the outputs.

VODVOLTAGE OVERDRIVE – The difference between

the differential input and reference input voltages.

50%

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SPT9693

8 3/1/01

PACKAGE OUTLINES

20-Contact Leadless Chip Carrier (LCC)

A

H

INCHES MILLIMETERS

SYMBOL MIN MAX MIN MAX

A .040 typ 1.02 typ

G

B .050 typ 1.27 typ
C 0.045 0.055 1.14 1.40

B

View

Bottom

Pin 1

D 0.345 0.360 8.76 9.14
E 0.054 0.066 1.37 1.68
F .020 typ 0.51 typ

C

D

F

E

G 0.022 0.028 0.56 0.71
H 0.075 1.91

20-Lead Plastic Leadless Chip Carrier (PLCC)

A

B

Pin 1

TOP

VIEW

C

D

Pin 1

BOTTOM

VIEW

E

F

G

INCHES MILLIMETERS

SYMBOL MIN MAX MIN MAX

A .045 typ 1.14 typ

N

B .045 typ 1.14 typ
C 0.350 0.356 8.89 9.04

M

O

D 0.385 0.395 9.78 10.03
E 0.350 0.356 8.89 9.04

L

F 0.385 0.395 9.78 10.03
G 0.042 0.056 1.07 1.42
H 0.165 0.180 4.19 4.57

K

J

I

H

I 0.085 0.110 2.16 2.79

J 0.025 0.040 0.64 1.02

K 0.015 0.025 0.38 0.64

L 0.026 0.032 0.66 0.81

M 0.013 0.021 0.33 0.53

N 0.050 1.27
O 0.290 0.330 7.37 8.38

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PIN ASSIGNMENTS PIN FUNCTIONS

A

NAME FUNCTION

Q

A

Q

A

GND
LE

A

LE

A

AVCC(A) Positive Supply Voltage (+10 V)
AVEE(A) Negative Supply Voltage (–10 V)
AVCC(B) Positive Supply Voltage (+10 V)
AVEE(B) Negative Supply Voltage (–10 V)
–IN

A

+IN

A

+IN

B

–IN

B

LE

B

LE

B

GND
Q

B

Q

B

N/C Not Connected

Output A
Inverted Output A
Ground A

A

Inverted Latch Enable A
Latch Enable A

Inverting Input A
Noninverting Input A
Noninverting Input B
Inverting Input B
Inverted Latch Enabled B
Latch Enable B
Ground B

B

Inverted Output B
Output B

GND

LE

LE

N/C

VEE(A)

A

A

A

Q

A

A

B

QBGND

Q

Q

3212019

4

5

6

TOP VIEW

LCC/PLCC

7

8

91011

AVCC(A)

IN

A

+IN

12

+IN

A

B

18

LE

B

LE

17

16

15

14

N/C

AV

AV

B

EE

CC

(B)

(B)

13

IN

B

B

ORDERING INFORMATION

PART NUMBER TEMPERATURE RANGE PACKAGE TYPE

SPT9693SCC 0 to +70 °C LCC
SPT9693SCP 0 to +70 °C PLCC
SPT9693SCU +25 °CDie*

*Please see the die specification for guaranteed electrical performance.

Signal Processing Technologies, Inc. reserves the right to change products and specifications without notice. Permission is hereby
expressly granted to copy this literature for informational purposes only. Copying this material for any other use is strictly prohibited.

WARNING – LIFE SUPPORT APPLICATIONS POLICY – SPT products should not be used within Life Support Systems without
the specific written consent of SPT. A Life Support System is a product or system intended to support or sustain life which, if it fails,
can be reasonably expected to result in significant personal injury or death.

Signal Processing Technologies believes that ultrasonic cleaning of its products may damage the wire bonding, leading to device
failure. It is therefore not recommended, and exposure of a device to such a process will void the product warranty.

SPT

10 3/1/01

SPT9693