Datasheet SPT9691SCC, SPT9691SCN, SPT9691SCP, SPT9691SCU Datasheet (SPT)

SPT9691

WIDE INPUT VOLTAGE, JFET COMPARATOR

FEATURES

• Common Mode Range -4.0 to +8.0 V

• Low Input Bias Current <100 pA

• Propagation Delay 2.5 ns (max)

• Low Offset ±25 mV

• Low Feedthrough and Crosstalk

• Differential Latch Control

GENERAL DESCRIPTION

The SPT9691 is a high-speed, wide common mode voltage,
JFET input, dual comparator. It is designed for applications
that measure critical timing parameters in which wide com­mon mode input voltages of -4.0 to +8.0 V are required.
Propagation delays are constant for overdrives greater than
200 mV.

JFET inputs reduce the input bias currents to the nanoamp
level, eliminating the need for input drivers and buffers in

BLOCK DIAGRAM

Q

A

APPLICATIONS

• Automated Test Equipment

• High-Speed Instrumentation

• Window Comparators

• High-Speed Timing

• Line Receivers

• High-Speed Triggers

• Threshold Detection

• Peak Detection

most applications. The device has differential analog inputs
and complementary logic outputs compatible with ECL sys­tems. Each comparator has a complementary latch enable
control that can be driven by standard ECL logic.

The SPT9691 is available in 20-lead PLCC, 20-lead plastic
DIP and 20-contact LCC packages over the commercial
temperature range. It is also available in die form.

Q

B

Q

GNDA

LEA
LEA

DVEE(A)

AV

EE(A)

AVCC(A)

-INA

+IN

A

A

A

B

Q

B

GND
LE

DV (B)
AV (B)

LE

B

B

B

EE

EE

AVCC (B)

-IN

B

+IN

B

Signal Processing Technologies, Inc.

4755 Forge Road, Colorado Springs, Colorado 80907, USA

Phone: [phone] FAX: [phone] Website: http://www.spt.com E-Mail: [e-mail]

ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur)1 25°C

Supply Voltages (Measured to GND)

Positive Supply Voltage (AVCC)..............-0.5 to +11.0 V

Negative Supply Voltage (AVEE) ............-11.0 to +0.5 V

Negative Supply Voltage (DVEE) ..............-6.0 to +0.5 V

Input Voltages

Input Common Mode Voltage ........ DVEE-1 to +AVCC+1

Differential Input Voltage ......................-12.0 to +12.0 V

Input Voltage, Latch Controls .................. DVEE to 0.5 V

VIN to AVCC Differential Voltage ................-16 to +1.0 V

VIN to AVEE Differential Voltage................+4 to +21.0 V

Note: 1. Operation at any Absolute Maximum Rating is not implied. See Electrical Specifications for proper nominal applied

conditions in typical applications. Application of multiple maximum rating conditions at the same time may damage
the device.

Output

Output Current .......................................................30 mA

Temperature

Operating Temperature, ambient.................. 0 to +70 °C

junction ....................... +150 °C

Lead Temperature, (soldering 60 seconds)........ +300 °C

Storage Temperature................................-65 to +150 °C

ELECTRICAL SPECIFICATIONS

T A = +25 °C, AVCC = +10 V, AVEE=-10.0 V, DVEE=-5.2 V, RL = 50 Ohm to -2V, unless otherwise specified.

TEST TEST

PARAMETERS CONDITIONS LEVEL MIN TYP MAX UNITS

DC ELECTRICAL CHARACTERISTICS
Input Offset Voltage V

Offset Voltage Tempco V 50 µV/°C
Input Bias Current I ±0.1 ±10 nA
Input Bias Current T
Input Offset Current V ±1.0 nA
Input Offset Current T
Positive Supply Current (Dual) AVcc=10 V I 25 33 mA
Negative Supply Current (Dual) AVEE=-10.0 V I 15 20 mA
Negative Supply Current (Dual) DVEE=-5.2 V I 55 70 mA
Positive Supply Voltage, AV
Negative Supply Voltage, AV
Negative Supply Voltage, DV
Input Common Mode Range I -4.0 +8.0 V
Latch Enable
Common Mode Range IV -2.0 0 V
Differential Voltage Range I ±10 V
Open Loop Gain V 60 dB
Differential Input Resistance V 2 GΩ
Input Capacitance LCC Package 1.0 pF

Power Supply Sensitivity V 60 dB
Common Mode Rejection Ratio I 50 60 dB

CC

EE
EE

=0 I -25 0.0 +25 mV

IN,CM

T

< TA<T

MIN

<TA<T

MIN

<TA<T

MIN

PLCC Package 1.0 pF
PDIP 2.9 pF

T

< TA<T

MIN

MAX

MAX

MAX

MAX

IV -25 0.0 +25 mV

IV ±2.0 ±100 nA

V ±10 nA

IV 9.75 10.0 10.25 V
IV -9.75 -10.0 -10.25 V
IV -4.95 -5.2 -5.45 V

IV 45 55 dB

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ELECTRICAL SPECIFICATIONS

T A = +25 °C, AVCC = +10 V, AVEE=-10.0 V, DVEE=-5.2 V, RL = 50 Ohm to -2V, unless otherwise specified.

TEST TEST

PARAMETERS CONDITIONS LEVEL MIN TYP MAX UNITS

DC ELECTRICAL CHARACTERISTICS
Power Dissipation Dual I 700 895 mW
Output High Level ECL 50 Ohms to -2V I -.98 -.70 V
Output Low Level ECL 50 Ohms to -2V I -1.95 -1.65 V
AC ELECTRICAL CHARACTERISTICS
Propagation Delay
Propagation Delay TEMPCO V 2 ps/ °C
Propagation Delay Skew (A vs B) V 100 ps
Propagation Delay Dispersion
Latch Set-up Time V 1.7 ns
Latch to Output Delay 150 mV O.D. V 0.8 ns
Latch Pulse Width V 2 ns
Latch Hold Time V -1.9 ns
Rise Time 20% to 80% V 0.4 ns
Fall Time 20% to 80% V 0.4 ns
Slew Rate V 3 V/ns

1

2

150 mV O.D. IV 1.5 2.0 2.5 ns

150 mV Overdrive Min. V 200 ps

NOTES:

1

Valid for both high-to-low and low-to-high transitions.

2

Dispersion is the change in propagation delay due to changes in slew rate, overdrive, and common mode level.

TEST LEVEL CODES

All electrical characteristics are subject to the
following conditions:

All parameters having min/max specifications
are guaranteed. The Test Level column indi­cates the specific device testing actually per­formed during production and Quality Assur­ance inspection. Any blank section in the data
column indicates that the specification is not
tested at the specified condition.

TEST LEVEL

I

II

III

IV

V

VI

TEST PROCEDURE

100% production tested at the specified temperature.
100% production tested at TA=25 °C, and sample

tested at the specified temperatures.
QA sample tested only at the specified temperatures.
Parameter is guaranteed (but not tested) by design

and characterization data.
Parameter is a typical value for information purposes

only.
100% production tested at TA = 25 °C. Parameter is

guaranteed over specified temperature range.

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TIMING INFORMATION

The timing diagram for the comparator is shown in figure 1.
If LE is high and LE low in the SPT9691, the comparator

tracks the input difference voltage. When LE is driven low
and LE high, the comparator outputs are latched into their

existing logic states.

Figure 1 - Timing Diagram

Latch Enable

Latch Enable

Differential

Input Voltage

Output Q

t

H

t

S

V

OD

t

pdL

The leading edge of the input signal (which consists of a
150 mV overdrive voltage) changes the comparator output
after a time of t
maintained for a time ts (set-up time) before the LE falling

pdL

or t

(Q or Q). The input signal must be

pdH

edge and LE rising edge and held for time tH after the falling
edge for the comparator to accept data. After tH , the output
ignores the input status until the latch is strobed again. A
minimum latch pulse width of tpL is needed for strobe opera­tion, and the output transitions occur after a time of t
t

.

pLOL

50%

tpL

V

Ref ± VOS

t

pLOH

50%

pLOH

or

Output Q

+=300 mV, =150 mV

V

IN

The set-up and hold times are a measure of the time required for an input signal to propagate through the
first stage of the comparator to reach the latching circuitry. Input signals occurring before ts will be detected
and held; those occurring after tH will not be detected. Changes between tS and tH may not be detected.

SWITCHING TERMS (Refer to figure 1)

t

INPUT TO OUTPUT HIGH DELAY - The propagation

pdH

delay measured from the time the input signal crosses
the reference voltage (± the input offset voltage) to the
50% point of an output LOW to HIGH transition.

t

INPUT TO OUTPUT LOW DELAY - The propagation

pdL

delay measured from the time the input signal crosses
the reference voltage (± the input offset voltage) to the
50% point of an output HIGH to LOW transition.

t

LATCH ENABLE TO OUTPUT HIGH DELAY - The

pLOH

propagation delay measured from the 50% point of the
Latch Enable signal LOW to HIGH transition to 50%
point of an output LOW to HIGH transition.

t

LATCH ENABLE TO OUTPUT LOW DELAY - The

pLOL

propagation delay measured from the 50% point of the
Latch Enable signal LOW to HIGH transition to the 50%
point of an output HIGH to LOW transition.

50%

t

pdH

V

OD

t

pLOL

t

MINIMUM HOLD TIME - The minimum time after the

H

negative transition of the Latch Enable signal that the
input signal must remain unchanged in order to be
acquired and held at the outputs.

t

MINIMUM LATCH ENABLE PULSE WIDTH - The

pL

minimum time that the Latch Enable signal must be
HIGH in order to acquire an input signal change.

t

MINIMUM SET-UP TIME - The minimum time before

S

the negative transition of the Latch Enable signal that
an input signal change must be present in order to be
acquired and held at the outputs.

V

VOLTAGE OVERDRIVE - The difference between the

OD

differential input and reference input voltages.

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TYPICAL PERFORMANCE CURVES

INPUT OFFSET VOLTAGE VS COMMON MODE VOLTAGE

+10.0

+6.0

+2.0

-2.0

INPUT OFFSET VOLTAGE (mV)

-6.0

-10.0

-4.0 -1.6 +0.8 +3.2 +5.6 +8.0

(T=+25 °C)

COMMON MODE VOLTAGE (V)

PROPOGA TION DELAY TIME VS TEMPERATURE

(V =150 mV)

2.4

2.2

OD

INPUT BIAS CURRENT VS COMMON MODE VOLTAGE

100

10

1.0

0.1

INPUT BIAS CURRENT (nA)

0.01

0.001

-4.0 -1.6 +0.8 +3.2 +5.6 +8.0

(+25 °C)

COMMON MODE VOLTAGE (V)

PROPAGATION DELAY TIME VS OVERDRIVE (mV)

3.0

2.8

2.6

2.0

1.8

PROPAGATION DELAY TIME (ns)

1.6

1.4
0 +25 +50

RISE AND FALL OF OUTPUTS VS TIME CROSSOVER

-.90

-1.10

-1.30

-1.50

OUTPUT RISE AND FALL (V)

-1.70

TEMPERA TURE (°C)

+75 +100

2.4

2.2

PROPAGATION DELAY TIME (ns)

2.0

1.8

0 50 100 150 200 250 300 350

OVERDRIVE (mV)

HYSTERESIS VS ∆LATCH

20

15

VIN (CM) = 0.0 V

10

HYSTERESIS (mV)

5

-1.90

SPT

1.1 1.5 1.9 2.3 2.7

TIME (ns)

0

3.5

-20 0 204060

∆LATCH = (VLE - VLE) mV

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GENERAL INFORMATION

The SPT9691 is an ultrahigh-speed dual voltage compara­tor. It offers tight absolute characteristics. The device has
differential analog inputs and complementary logic outputs
compatible with ECL systems. The output stage is adequate
for driving terminated 50 ohm transmission lines.

The SPT9691 has a complementary latch enable control for
each comparator. Both should be driven by standard ECL
logic levels.

Figure 2 - Internal Function Diagram

A common mode voltage range of -4 V to +8 V is achieved by
a proprietary JFET input design which requires a separate
negative power supply (AVEE).

The dual comparators have separate AV

CC,

AV

EE, DVEE,

and
grounds for each comparator to achieve high crosstalk rejec­tion. Single channel operation can be accomplished by float­ing all pins (including the ground and supply pins) of the
unused comparator. Power dissipation during single channel
operation is 50% of the dissipation during dual channel
operation.

+IN

- IN

AV

EE

DV

EE

REF

1

+

-

V

PRE

AMP

CC

REF

2

GND

LATCH

CLK
BUF

LE LE

Q

ECL

OUT

Q

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TYPICAL INTERFACE CIRCUIT

The typical interface circuit using the comparator is shown in
figure 3. Although it needs few external components and is
easy to apply, there are several conditions that should be
noted to achieve optimal performance. The very high operat­ing speeds of the comparator require careful layout, decou­pling of supplies, and proper design of transmission lines.

Since the SPT9691 comparator is a very high frequency and
high gain device, certain layout rules must be followed to
avoid oscillations. The comparator should be soldered to the
board with component lead lengths kept as short as possible.
A ground plane should be used, while the input impedance to
the part is kept as low as possible, to decrease parasitic
feedback. If the output board traces are longer than approxi­mately half an inch, microstripline techniques must be em­ployed to prevent ringing on the output waveform. Also, the
microstriplines must be terminated at the far end with the
characteristic impedance of the line to prevent reflections. All
supply voltage pins should be decoupled with high frequency
capacitors as close to the device as possible. All ground pins
should be connected to the same ground plane to further
improve noise immunity and shielding. If using the SPT9691
as a single comparator, the outputs of the inactive compara­tor can be grounded, left open or terminated with 50 Ohms to

-2 V. All outputs on the active comparator, whether used or
unused, should have identical terminations to minimize
ground current switching transients.

Diode D1 connected between AVCC and GND is recom­mended to prevent possible damage to the device in case
the AVCC supply is disconnected. The diode should be a
1N914 or equivalent. If AVCC is disconnected with this diode
in place, there will be approximately a 6 mA current draw
from both AVEE and DVEE. Diode D2 connected between
AVEE and DVEE is necessary to avoid power supply se­quence latch-up. This diode keeps AVEE (also the substrate)
less than a silicon diode drop away from the most negative
circuit potential if DVEE is powered up first. This diode should
be a 1N5817 (Schottky) or equivalent.

Note: At no time should both inputs be allowed to float with
power applied to the device. At least one of the inputs should
be tied to a voltage within the common mode range (-4.0 to
+8.0 V) to prevent possible damage to the device. To prevent
possible latch-up during initial power up, the input voltages
should not exceed ±1 V. Additional protection diodes D3-D6
should be used on the inputs if there is the possibility of
exceeding the absolute maximum ratings of the inputs with
respect to AVCC and DVEE (1N914 or equivalent). NOTE: For
ease of implementation, all diodes (D1 - D6) can be 1N5817
(Schottky) or equivalent.

Figure 3 - SPT9691 Typical Interface Circuit

D3

V

IN

V

REF

AVEEDVEEAV

D4 D5

Noninverting Input

Inverting Input

GND

CC

CC

AV

GND

D1

.1 µF

.1 µF

D6

+

-

LE

LE

ECL

= Represents line termination.

EE

AV

.1 µF

EE

DV

D2

R

L

50 Ω

-2 V

R

50 Ω

L

Q Output

Q Output

.1 µF

Figure 4 - SPT9691 Typical Interface Circuit With

Hysteresis

EE

EE

GND

.1 µF

LE

= Represents line termination.

AV

.1 µF

DV

D2

R

L

50 Ω

-2 V

50 Ω

-2 V

R

L

.1 µF

D3

V

IN

V

REF

AVEEDVEEAV

D4

Noninverting Input

Inverting Input

GND

CC

CC

AV

D1

.1 µF

D6

D5

+

-

LE

-1.3 V

100 Ω

.1 µF

Q Output

Q Output

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20

PACKAGE OUTLINES

20-Lead Plastic DIP

INCHES MILLIMETERS

SYMBOL MIN MAX MIN MAX

A 0.300 7.62

B 0.014 0.026 0.36 0.66
C .100 typ 2.54
D .010 typ 0.25

G

1

E 1.20 typ 30.48

F 0.290 0.330 7.37 8.38
G 0.246 0.254 6.25 6.45
H 1.010 1.030 25.65 26.16

H

A

D

B

C

F

E

20-Lead Plastic Leaded Chip Carrier (PLCC)

A

B

Pin 1

TOP

VIEW

C
D

Pin 1

BOTTOM

VIEW

F

E

G

INCHES MILLIMETERS

SYMBOL MIN MAX MIN MAX

N

M

O

A .045 typ 1.14
B

C 0.350 0.356 8.89 9.04

L

D 0.385 0.395 9.78 10.03

E 0.350 0.356 8.89 9.04
F 0.385 0.395 9.78 10.03

K
J
I

H

G 0.042 0.056 1.07 1.42
H 0.165 0.180 4.19 4.57

I 0.085 0.110 2.16 2.79

J 0.025 0.040 0.64 1.02
K 0.015 0.025 0.38 0.64
L 0.026 0.032 0.66 0.81

M 0.013 0.021 0.33 0.53
N 0.050 1.27
O 0.290 0.330 7.37 8.38

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PACKAGE OUTLINES

20-Contact Leadless Chip Carrier (LCC)

A

Bottom

B

C

View

H

G

Pin 1

F

INCHES MILLIMETERS

SYMBOL MIN MAX MIN MAX

A .040 typ 1.02

B .050 typ 1.27
C 0.045 0.055 1.14 1.40
D 0.345 0.360 8.76 9.14

E 0.054 0.066 1.37 1.68

F .020 typ 0.51
G 0.022 0.028 0.56 0.71
H 0.075 1.91

D

E

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PIN ASSIGNMENTS

PIN FUNCTIONS

GND

LE
LE

DVEE(A)

EE

AV

CC

AV

-IN
+IN

LE

LE

DVEE(A)

Q
Q

(A)
(A)

A

A

A

1

A

2

A

3

A

4

A

5

A

DIP/PDIP

6
7
8

A

9

A

10

Q

Q

Q

A

3

4GND

5

6

7

B

A

1

2

TOP VIEW

LCC/PLCC

20

Q

B

19

Q

B

18

GND

B

17

LE

B

16

LE

B

15

DV (B)

EE

14

AV (B)

EE

13

CC

(B)

AV

12

-IN

B

11

+IN

B

GND

Q

20

B

B

19

LE

B

18

LE

B

17

DVEE(B)

16

EE

(B)

AV

15

NAME FUNCTION

Q

A

Q

A

GND

LE

A

LE

A

A

Output A
Inverted Output A

Ground A
Inverted Latch Enable A

Latch Enable A
AVCC(A) Positive Supply Voltage (+10 V)
AVEE(A) Negative Supply Voltage (-10 V)
DVEE(A) Negative Supply Voltage (-5.2 V)
AVCC(B) Positive Supply Voltage (+10 V)
AVEE(B) Negative Supply Voltage (-10 V)
DVEE(B) Negative Supply Voltage (-5.2 V)

-IN

A

+IN
+IN

-IN

B

LE

B

LE

B

GND

Q

B

Q

B

A
B

B

Inverting Input A

Noninverting Input A

Noninverting Input B

Inverting Input B

Inverted Latch Enabled B

Latch Enable B

Ground B

Inverted Output B

Output B

EE

(A)

AV

AV

8

9

CC

(A)

10 11

-IN

A

+IN

12

B

A

+IN

13

-IN

14

CC

(B)

AV

B

ORDERING INFORMATION

PART NUMBER TEMPERATURE RANGE PACKAGE TYPE

SPT9691SCC 0 to +70 °C 20C LCC
SPT9691SCN 0 to +70 °C 20L Plastic DIP
SPT9691SCP 0 to +70 °C 20L Plastic Leaded Chip Carrier (PLCC)
SPT9691SCU +25 °C Die*

*Please see the die specification for guaranteed electrical performance.

Signal Processing Technologies, Inc. reserves the right to change products and specifications without notice. Permission is hereby expressly
granted to copy this literature for informational purposes only. Copying this material for any other use is strictly prohibited.

WARNING - LIFE SUPPORT APPLICATIONS POLICY - SPT products should not be used within Life Support Systems without the specific
written consent of SPT. A Life Support System is a product or system intended to support or sustain life which, if it fails, can be reasonably
expected to result in significant personal injury or death.

Signal Processing Technologies believes that ultrasonic cleaning of its products may damage the wire bonding, leading to device
failure. It is therefore not recommended, and exposure of a device to such a process will void the product warranty.

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