Datasheet SP3222ECA, SP3222ECP, SP3222ECT, SP3222ECY, SP3222EEA Datasheet (Sipex Corporation)

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Page 1

SP3222E/3232E

True +3.0V to +5.5V RS-232 Transceivers

■ Meets true EIA/TIA-232-F Standards from a +3.0V to +5.5V power supply

■ 235KBps Transmission Rate Under Load

■ 1µA Low-Power Shutdown with Receivers

Active (SP3222E)

■ Interoperable with RS-232 down to +2.7V power source

■ Enhanced ESD Specifications:

±15kV Human Body Model ±15kV IEC1000-4-2 Air Discharge ±8kV IEC1000-4-2 Contact Discharge

DESCRIPTION

The SP3222E/3232E series is an RS-232 transceiver solution intended for portable or hand- held applications such as notebook or palmtop computers. The SP3222E/3232E series has a high-efficiency, charge-pump power supply that requires only 0.1µF capacitors in 3.3V operation. This charge pump allows the SP3222E/3232E series to deliver true RS-232 performance from a single power supply ranging from +3.3V to +5.0V. The SP3222E/3232E are 2-driver/2-receiver devices. This series is ideal for portable or hand-held applications such as notebook or palmtop computers. The ESD tolerance of the SP3222E/3232E devices are over ±15kV for both Human Body Model and IEC1000-4-2 Air discharge test methods. The SP3222E device has a low-power shutdown mode where the devices' driver outputs and charge pumps are disabled. During shutdown, the supply current falls to less than 1µA.

SELECTION TABLE

LEDOMseilppuSrewoP

2223PS 2323PS

V5.5+otV0.3+224seYseY02,81 V5.5+otV0.3+224oNoN61

232-SR srevirDsrevirD

srevirDsrevirD

srevirD

232-SR

srevieceRsrevieceR

srevieceR

lanretxE

stnenopmoCstnenopmoC

stnenopmoC

nwodtuhS

LTT

etatS-3etatS-3

etatS-3

fo.oN

sniPsniP

sniP

Page 2

ABSOLUTE MAXIMUM RATINGS

These are stress ratings only and functional operation of the device at these ratings or any other above those indicated in the operation sections of the specifications below is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability and cause permanent damage to the device.

VCC................................................................-0.3V to +6.0V

V+ (NOTE 1)................................................-0.3V to +7.0V

V- (NOTE 1)................................................+0.3V to -7.0V

V+ + |V-| (NOTE 1)....................................................+13V

ICC (DC VCC or GND current).................................±100mA

Input Voltages

TxIN, EN .....................................................-0.3V to +6.0V

RxIN.............................................................................±25V

Output Voltages

TxOUT.....................................................................±13.2V

RxOUT..............................................-0.3V to (VCC + 0.3V)

Short-Circuit Duration

TxOUT...............................................................Continuous

Storage Temperature.................................-65°C to +150°C

Power Dissipation Per Package

20-pin SSOP (derate 9.25mW/oC above +70oC).......750mW

18-pin PDIP (derate 15.2mW/oC above +70oC)......1220mW

18-pin SOIC (derate 15.7mW/oC above +70oC)......1260mW

20-pin TSSOP (derate 11.1mW/oC above +70oC).....890mW

16-pin SSOP (derate 9.69mW/oC above +70oC).......775mW

16-pin PDIP (derate 14.3mW/oC above +70oC)......1150mW

16-pin Wide SOIC (derate 11.2mW/oC above +70oC)....900mW

16-pin TSSOP (derate 10.5mW/oC above +70oC).....850mW

NOTE 1: V+ and V- can have maximum magnitudes of 7V, but their absolute difference cannot exceed 13V.

SPECIFICATIONS

Unless otherwise noted, the following specifications apply for VCC = +3.0V to +5.0V with T

RETEMARAP.NIM.PYT.XAMSTINUSNOITIDNOC

SCITSIRETCARAHCCD

tnerruCylppuS3.00.1AmT,daolon

tnerruCylppuSnwodtuhS0.101µA,DNG=NDHST

STUPTUOREVIECERDNASTUPNICIGOL

AMB

BMA

= T

to T

MIN

52+=

V,C

52+=

BMA

MAX

V,C

V3.3=

V3.3+=

WOLdlohserhTcigoLtupnI8.0V 2etoN,NDHS,NE,NIxT

HGIHdlohserhTcigoLtupnI0.2

4.2

tnerruCegakaeLtupnI10.0±0.1±µA,NDHS,NE,NIxTT

2etoN,V3.3= 2etoN,V0.5=

52+=

BMA

tnerruCegakaeLtuptuO50.0±01±µAdelbasidsreviecer

WOLegatloVtuptuO4.0VI

HGIHegatloVtuptuOV

6.0-VCC1.0-VI

TUO

Am6.1=

Am0.1-=

STUPTUOREVIRD

gniwSegatloVtuptuO0.5±4.5±Vk3Ω ,stuptuorevirdllatadnuorgotdaol

ecnatsiseRtuptuO003ΩV

tnerruCtiucriC-trohStuptuO53±

07±

06±

001±

tnerruCegakaeLtuptuO52±µAV

52+=

BMA

T,V0=-V=+V=

V0=

TUO

=+ V51

TUO

=+ V,V21

TUO

=+ V2

TUO

delbasidsrevird,V5.5otV0=

Page 3

SPECIFICATIONS (continued)

Unless otherwise noted, the following specifications apply for VCC = +3.0V to +5.0V with T Typical Values apply at VCC = +3.3V or +5.0V and T

RETEMARAP.NIM.PYT.XAMSTINUSNOITIDNOC

STUPNIREVIECER

egnaRegatloVtupnI51-51+V

AMB

= 25oC.

AMB

= T

MIN

to T

MAX

WOLdlohserhTtupnI6.0

HGIHdlohserhTtupnI5.1

2.1

8.0

5.1

8.1

4.2

V3.3= V0.5=

siseretsyHtupnI3.0V

ecnatsiseRtupnI357kΩ

SCITSIRETCARAHCGNIMIT

etaRataDmumixaM021532spbkR

yaleDnoitagaporPrevirD0.1

0.1

yaleDnoitagaporPrevieceR3.0

µs µs

µst

3.0

k3=ΩC,

t t

HLP

K3=ΩC,

LHP

K3=ΩC,

LHP

emiTelbanEtuptuOrevieceR002sn

emiTelbasiDtuptuOrevieceR002sn

wekSrevirD001005snt|

wekSrevieceR0020001snt|

etaRwelSnoigeR-noitisnarT03/VµsV

LHP

HLP

T,|

BMA

R,V3.3=

V0.3-otV0.3+ro

L L

Fp0001= Fp0001=

C,TUOxRotNIxR, C,TUOxRotNIxR,

L L

Fp051= Fp051=

52=oC

K3=ΩT,

BMA

52=o,C

gnihctiwsrevirdeno,Fp0001=

V0.3+otV0.3-morfnekatstnemerusaem

NOTE 2: Driver input hysteresis is typically 250mV.

Page 4

TYPICAL PERFORMANCE CHARACTERISTICS

Unless otherwise noted, the following performance characteristics apply for VCC = +3.3V, 235kbps data rates, all drivers loaded with 3kΩ, 0.1µF charge pump capacitors, and T

= +25°C.

AMB

Transmitter Output Voltage [V]

-2

-4

-6

500

1000

Load Capacitance [pF]

1500

2000

Figure 1. Transmitter Output Voltage VS. Load Capacitance for the SP3222 and the SP3232

0 500

118KHz 60KHz 10KHz

1000

Load Capacitance [pF]

1500

2000

Supply Current [mA]

Vout+ Vout-

2330

Slew Rate [V/µs]

0 500

1000

Load Capacitance [pF]

1500

2000

+Slew

-Slew

Figure 2. Slew Rate VS. Load Capacitance for the SP3222 and the SP3232

2330

Figure 3. Supply Current VS. Load Capacitance when Transmitting Data for the SP3222 and the SP3232

Page 5

REBMUNNIP

EMANNOITCNUF

.noitarepolamronrofWOLcigolylppA.elbanErevieceR

.)etatsZ-hgih(stuptuoreviecerehtelbasidotHGIHcigolylppA

E2223PS

OS/PID

-/POSS

POSSTPOSST

POSST

11 -

+1C.roticapacpmup-egrahcrelbuodegatlovehtfolanimretevitisoP 22 1

+V.pmupegrahcehtybdetarenegV5.5+ 33 2

-1C.roticapacpmup-egrahcrelbuodegatlovehtfolanimretevitageN 44 3

+2C.roticapacpmup-egrahcgnitrevniehtfolanimretevitisoP 55 4

-2C.roticapacpmup-egrahcgnitrevniehtfolanimretevitageN 66 5

-V.pmupegrahcehtybdetarenegV5.5- 77 6 TUO1T.tuptuorevird232-SR 517141 TUO2T.tuptuorevird232-SR 88 7

NI1R.tupnireviecer232-SR 416131 NI2R.tupnireviecer232-SR 99 8

TUO1R.tuptuoreveicerSOMC/LTT 315121

TUO2R.tuptuoreveicerSOMC/LTT 01019 NI1T.tupnirevirdSOMC/LTT 213111 NI2T.tupnirevirdSOMC/LTT 112101 DNG.dnuorG 618151

egatlovylppusV5.5+otV0.3+ 719161

.noitarepoecivedlamronrofHGIHevirD.tupnIlortnoCnwodtuhS

NDHS

-noehtdna)tuptuoZ-hgih(srevirdehtnwodtuhsotWOLevirD

8102-

.ylppusrewopdraob

.C.N.tcennoCoN -41,11-

Table 1. Device Pin Description

E2323PS

Page 6

C1+

V+

C1-

C2+

C2-

1 2 3 4 5 6

SP3222E

20 19 18 17

SHDN

V GND T1OUT

R1IN R1OUT

C1+

V+

C1-

C2+

C2-

1 2

3 4 5 6

SP3222E

17 16 15

SHDN

GND T1OUT

R1IN

R1OUT

V-

T2OUT

R2IN

R2OUT

Figure 4. Pinout Configurations for the SP3222E

8 9

SSOP/TSSOP

13 12 11

C1+

V+

C1-

C2+

C2-

N.C. T1IN

T2IN

N.C.

1 2 3 4 5

T2OUT

SP3232E

V-

R2IN

16 15 14 13

7 8

DIP/SO

GND T1OUT

R1IN

R1OUT

T1IN

T2IN R2OUT

V-

T2OUT

R2IN

Figure 5. Pinout Configuration for the SP3232E

7 8

T1IN

T2IN

R2OUT

Page 7

LOGIC

INPUTS

0.1µF

C1+

C1C2+

C2-

T1IN T2IN

SP3222E

SSOP

TSSOP

T1OUT T2OUT

V+

V-

0.1µF

*C3

0.1µF

RS-232

OUTPUTS

4 5

13 12

LOGIC

INPUTS

0.1µF

4 5

12 11

C1+

C1C2+

C2-

T1IN T2IN

VCC

SP3222E

DIP/SO

T1OUT T2OUT

V+

V-

0.1µF

*C3

0.1µF

RS-232

OUTPUTS

R1IN

R2IN

SHDN

*can be returned to either VCC or GND

LOGIC

OUTPUTS

R1OUT

5kΩ

R2OUT

5kΩ

GND

Figure 6. SP3222E Typical Operating Circuits

0.1µF

LOGIC

INPUTS

R1IN

R2IN

SHDN

RS-232 INPUTS

*can be returned to either VCC or GND

RS-232 INPUTS

LOGIC

OUTPUTS

R1OUT

R2OUT

5kΩ

GND

C1+

C1-

C2+

C2-

T1IN

T2IN

SP3232E

V+

T1OUT T2OUT

V-

14 7

*C3

RS-232 OUTPUTS

0.1µF

R1IN

R2IN

RS-232

INPUTS

LOGIC

OUTPUTS

R1OUT

5kΩ

R2OUT

5kΩ

GND

*can be returned to either VCC or GND

Figure 7. SP3232E Typical Operating Circuit

Page 8

DESCRIPTION

The SP3222E/3232E transceivers meet the EIA/ TIA-232 and V.28/V.24 communication protocols and can be implemented in battery-powered, portable, or hand-held applications such as notebook or palmtop computers. The SP3222E/ 3232E devices all feature Sipex's proprietary on-board charge pump circuitry that generates 2 x VCC for RS-232 voltage levels from a single +3.0V to +5.5V power supply. This series is ideal for +3.3V-only systems, mixed +3.3V to +5.5V systems, or +5.0V-only systems that require true RS-232 performance. The SP3222E/ 3232E series have drivers that operate at a typical data rate of 235Kbps fully loaded.

The SP3222E and SP3232E are 2-driver/2-receiver devices ideal for portable or hand-held applications. The SP3222E features a 1µA shutdown mode that reduces power consumption and extends battery life in portable systems. Its receivers remain active in shutdown mode, allowing external devices such as modems to be monitored using only 1µA supply current.

THEORY OF OPERATION

The SP3222E/3232E series are made up of three basic circuit blocks: 1. Drivers, 2. Receivers, and 3. the Sipex proprietary charge pump.

The slew rate of the driver output is internally limited to a maximum of 30V/µs in order to meet the EIA standards (EIA RS-232D 2.1.7, Paragraph 5). The transition of the loaded output from HIGH to LOW also meets the monotonicity requirements of the standard.

The SP3222E/3232E drivers can maintain high data rates up to 240Kbps fully loaded. Figure 8 shows a loopback test circuit used to test the RS-232 drivers. Figure 9 shows the test results of the loopback circuit with all drivers active at 120Kbps with RS-232 loads in parallel with 1000pF capacitors. Figure 10 shows the test results where one driver was active at 235Kbps and all drivers loaded with an RS-232 receiver in parallel with a 1000pF capacitor. A solid RS-232 data transmission rate of 120Kbps provides compatibility with many designs in personal computer peripherals and LAN applications.

The SP3222E driver's output stages are turned off (tri-state) when the device is in shutdown mode. When the power is off, the SP3222E device permits the outputs to be driven up to ±12V. The driver's inputs do not have pull-up resistors. Designers should connect unused inputs to VCC or GND.

Drivers

The drivers are inverting level transmitters that convert TTL or CMOS logic levels to ±5.0V EIA/TIA-232 levels inverted relative to the input logic levels. Typically, the RS-232 output voltage swing is ±5.5V with no load and at least ±5V minimum fully loaded. The driver outputs are protected against infinite short-circuits to ground without degradation in reliability. Driver outputs will meet EIA/TIA-562 levels of ±3.7V with supply voltages as low as 2.7V.

In the shutdown mode, the supply current falls to less than 1µA, where SHDN = LOW. When the SP3222E device is shut down, the device's driver outputs are disabled (tri-stated) and the charge pumps are turned off with V+ pulled down to VCC and V- pulled to GND. The time required to exit shutdown is typically 100µs. Connect SHDN to VCC if the shutdown mode is not used. SHDN has no effect on RxOUT or RxOUTB. As they become active, the two driver outputs go to opposite RS-232 levels where one

driver input is HIGH and the other LOW. Note The drivers typically can operate at a data rate of 235Kbps. The drivers can guarantee a data

that the drivers are enabled only when the

magnitude of V- exceeds approximately 3V. rate of 120Kbps fully loaded with 3KΩ in parallel with 1000pF, ensuring compatibility with PC-to-PC communication software.

Page 9

LOGIC

INPUTS

0.1µF

C1+

C1-

C2+

C2TxIN

SP3222E SP3232E

V+

V-

TxOUT

0.1µF

LOGIC

OUTPUTS

RxOUT

Figure 8. SP3222E/3232E Driver Loopback Test Circuit

Ch2

5.00V M 5.00µs

Ch1

T1 IN

T1 OUT

R1 OUT

[]

5.00V

Ch1

Ch3

5.00V

GND

RxIN

5kΩ

*SHDN

* SP3222 only

T1 IN

T1 OUT

R1 OUT

1000pF

Ch2

5.00V M 2.50µs

Ch1

[]

5.00V

Ch1

Ch3

5.00V

Figure 9. Driver Loopback Test Results at 120kbps

Figure 10. Driver Loopback Test Results at 235kbps

Page 10

Receivers

The receivers convert EIA/TIA-232 levels to TTL or CMOS logic output levels. All receivers have an inverting tri-state output. These receiver outputs (RxOUT) are tri-stated when the enable control EN = HIGH. In the shutdown mode, the receivers can be active or inactive. EN has no effect on TxOUT. The truth table logic of the SP3222E/3232E driver and receiver outputs can be found in Table 2.

Since receiver input is usually from a transmission line where long cable lengths and system interference can degrade the signal, the inputs have a typical hysteresis margin of 300mV. This ensures that the receiver is virtually immune to noisy transmission lines. Should an input be left unconnected, a 5kΩ pulldown resistor to ground will commit the output of the receiver to a HIGH state.

Charge Pump

The charge pump is a Sipex–patented design (5,306,954) and uses a unique approach compared to older less–efficient designs. The charge pump still requires four external capacitors, but uses a four–phase voltage shifting technique to attain symmetrical 5.5V power supplies. The internal power supply consists of a regulated dual charge pump that provides output voltages

5.5V regardless of the input voltage (VCC) over the +3.0V to +5.5V range.

NDHSNETUOxTTUOxR

00 etats-irTevitcA 01 etats-irTetats-irT 10 evitcAevitcA 11 evitcAetats-irT

Table 2. Truth Table Logic for Shutdown and Enable Control

In most circumstances, decoupling the power

supply can be achieved adequately using a 0.1µF

bypass capacitor at C5 (refer to Figures 6 and 7).

In applications that are sensitive to power-sup-

ply noise, decouple VCC to ground with a capaci-

tor of the same value as charge-pump capacitor

C1. Physically connect bypass capacitors as

close to the IC as possible.

The charge pumps operate in a discontinuous

mode using an internal oscillator. If the output

voltages are less than a magnitude of 5.5V, the

charge pumps are enabled. If the output voltage

exceed a magnitude of 5.5V, the charge pumps

are disabled. This oscillator controls the four

phases of the voltage shifting. A description of

each phase follows.

Phase 1

— VSS charge storage — During this phase of

the clock cycle, the positive side of capacitors C

and C2 are initially charged to VCC. C

switched to GND and the charge in C

ferred to C

–

. Since C

is connected to VCC, the

is then

–

is trans-

voltage potential across capacitor C2 is now 2

times VCC.

Phase 2

— VSS transfer — Phase two of the clock con-

nects the negative terminal of C2 to the V

storage capacitor and the positive terminal of C

to GND. This transfers a negative generated

voltage to C3. This generated voltage is regu-

lated to a minimum voltage of -5.5V. Simulta-

neous with the transfer of the voltage to C3, the

positive side of capacitor C1 is switched to V

and the negative side is connected to GND.

Phase 3

— VDD charge storage — The third phase of the

clock is identical to the first phase — the charge

transferred in C1 produces –VCC in the negative

terminal of C1, which is applied to the negative

side of capacitor C2. Since C

is at VCC, the

voltage potential across C2 is 2 times VCC.

Page 11

Phase 4

— VDD transfer — The fourth phase of the clock connects the negative terminal of C2 to GND, and transfers this positive generated voltage across C2 to C4, the VDD storage capacitor. This voltage is regulated to +5.5V. At this voltage, the internal oscillator is disabled. Simultaneous with the transfer of the voltage to C4, the positive side of capacitor C1 is switched to VCC and the negative side is connected to GND, allowing the charge pump cycle to begin again. The charge pump cycle will continue as long as the operational conditions for the internal oscillator are present.

Since both V+ and V– are separately generated from VCC; in a no–load condition V+ and V– will be symmetrical. Older charge pump approaches that generate V– from V+ will show a decrease in the magnitude of V– compared to V+ due to the inherent inefficiencies in the design.

The clock rate for the charge pump typically operates at 250kHz. The external capacitors can be as low as 0.1µF with a 16V breakdown voltage rating.

potential to store electro-static energy and discharge it to an integrated circuit. The simulation is performed by using a test model as shown in Figure 17. This method will test the IC’s capability to withstand an ESD transient during normal handling such as in manufacturing areas where the ICs tend to be handled frequently.

The IEC-1000-4-2, formerly IEC801-2, is generally used for testing ESD on equipment and systems. For system manufacturers, they must guarantee a certain amount of ESD protection since the system itself is exposed to the outside environment and human presence. The premise with IEC1000-4-2 is that the system is required to withstand an amount of static electricity when ESD is applied to points and surfaces of the equipment that are accessible to personnel during normal usage. The transceiver IC receives most of the ESD current when the ESD source is applied to the connector pins. The test circuit for IEC1000-4-2 is shown on Figure 18. There are two methods within IEC1000-4-2, the Air Discharge method and the Contact Discharge method.

ESD Tolerance

With the Air Discharge Method, an ESD voltage is applied to the equipment under

The SP3222E/3232E series incorporates ruggedized ESD cells on all driver output and receiver input pins. The ESD structure is improved over our previous family for more rugged applications and environments sensitive to electro-static discharges and associated transients. The improved ESD tolerance is at least ±15kV without damage nor latch-up.

test (EUT) through air. This simulates an electrically charged person ready to connect a cable onto the rear of the system only to find an unpleasant zap just before the person touches the back panel. The high energy potential on the person discharges through an arcing path to the rear panel of the system before he or she even touches the system. This

energy, whether discharged directly or through There are different methods of ESD testing applied:

a) MIL-STD-883, Method 3015.7 b) IEC1000-4-2 Air-Discharge c) IEC1000-4-2 Direct Contact

air, is predominantly a function of the discharge

current rather than the discharge voltage.

Variables with an air discharge such as

approach speed of the object carrying the ESD

potential to the system and humidity will tend to

change the discharge current. For example, the The Human Body Model has been the generally accepted ESD testing method for semiconduc-

rise time of the discharge current varies with

the approach speed. tors. This method is also specified in MIL-STD883, Method 3015.7 for ESD testing. The premise of this ESD test is to simulate the human body’s

Page 12

VCC = +5V

Figure 12. Charge Pump — Phase 1

Figure 13. Charge Pump — Phase 2

+6V

a) C

GND GND

b) C2-

+5V

––

–5V –5V

VCC = +5V

––

–10V

T[]

–

Storage Capacitor

–

Storage Capacitor

–

Storage Capacitor

–

Storage Capacitor

-6V

Ch1 2.00V Ch2 2.00V M 1.00µs Ch1 5.48V

Figure 14. Charge Pump Waveforms

VCC = +5V

+5V

–5V

––

–5V

–

Storage Capacitor

–

Storage Capacitor

Figure 15. Charge Pump — Phase 3

= +5V

+10V

––

–

Storage Capacitor

–

Storage Capacitor

Figure 16. Charge Pump — Phase 4

Page 13

SW1

SW1SW1

DC Power Source

Figure 17. ESD Test Circuit for Human Body Model

The Contact Discharge Method applies the ESD current directly to the EUT. This method was devised to reduce the unpredictability of the ESD arc. The discharge current rise time is constant since the energy is directly transferred without the air-gap arc. In situations such as hand held systems, the ESD charge can be directly discharged to the equipment from a person already holding the equipment. The current is transferred on to the keypad or the serial port of the equipment directly and then travels through the PCB and finally to the IC.

SW2

SW2SW2

Device Under Test

The circuit models in Figures 17 and 18

represent the typical ESD testing circuits used

for all three methods. The CS is initially charged

with the DC power supply when the first

switch (SW1) is on. Now that the capacitor is

charged, the second switch (SW2) is on while

SW1 switches off. The voltage stored in the

capacitor is then applied through RS, the current

limiting resistor, onto the device under test

(DUT). In ESD tests, the SW2 switch is pulsed

so that the device under test receives a duration

of voltage.

Contact-Discharge Module

Contact-Discharge ModuleContact-Discharge Module

SW1

SW1SW1

DC Power Source

Figure 18. ESD Test Circuit for IEC1000-4-2

RS and RV add up to 330Ω for IEC1000-4-2.

andand RR

S S

SW2

SW2SW2

add up to 330add up to 330ΩΩ f for IEC1000-4-2.or IEC1000-4-2.

V V

Device Under Test

Page 14

For the Human Body Model, the current limiting resistor (RS) and the source capacitor (CS) are 1.5kΩ an 100pF, respectively. For

I ➙

30A

IEC-1000-4-2, the current limiting resistor (RS) and the source capacitor (CS) are 330Ω an 150pF, respectively.

15A

The higher CS value and lower RS value in the IEC1000-4-2 model are more stringent than the Human Body Model. The larger storage capacitor injects a higher voltage to the test

point when SW2 is switched on. The lower current limiting resistor increases the current

charge onto the test point.

t=0ns

t ➙

Figure 19. ESD Test Waveform for IEC1000-4-2

t=30ns

Device Pin Human Body IEC1000-4-2

Tested Model Air Discharge Direct Contact Level

Driver Outputs ±15kV ±15kV ±8kV 4 Receiver Inputs ±15kV ±15kV ±8kV 4

Table 3. Transceiver ESD Tolerance Levels

Page 15

PACKAGE: PLASTIC SHRINK

SMALL OUTLINE (SSOP)

DIMENSIONS (Inches)

Minimum/Maximum

(mm) A

16–PIN

0.068/0.078 (1.73/1.99)

0.002/0.008 (0.05/0.21)

0.010/0.015 (0.25/0.38)

0.239/0.249 (6.07/6.33)

0.205/0.212 (5.20/5.38)

0.0256 BSC (0.65 BSC)

0.301/0.311 (7.65/7.90)

0.022/0.037 (0.55/0.95)

0°/8°

(0°/8°)

20–PIN

0.068/0.078 (1.73/1.99)

0.002/0.008 (0.05/0.21)

0.010/0.015 (0.25/0.38)

0.278/0.289 (7.07/7.33)

0.205/0.212 (5.20/5.38)

0.0256 BSC (0.65 BSC)

0.301/0.311 (7.65/7.90)

0.022/0.037 (0.55/0.95)

0°/8°

(0°/8°)

24–PIN

0.068/0.078 (1.73/1.99)

0.002/0.008 (0.05/0.21)

0.010/0.015 (0.25/0.38)

0.317/0.328 (8.07/8.33)

0.205/0.212 (5.20/5.38)

0.0256 BSC (0.65 BSC)

0.301/0.311 (7.65/7.90)

0.022/0.037 (0.55/0.95)

0°/8°

(0°/8°)

28–PIN

0.068/0.078 (1.73/1.99)

0.002/0.008 (0.05/0.21)

0.010/0.015 (0.25/0.38)

0.397/0.407

(10.07/10.33)

0.205/0.212 (5.20/5.38)

0.0256 BSC (0.65 BSC)

0.301/0.311 (7.65/7.90)

0.022/0.037 (0.55/0.95)

0°/8°

(0°/8°)

Page 16

D1 = 0.005" min.

(0.127 min.)

e = 0.100 BSC

(2.540 BSC)

ALTERNATE

END PINS

(BOTH ENDS)

PACKAGE: PLASTIC

DUAL–IN–LINE (NARROW)

A1 = 0.015" min.

(0.381min.)

A = 0.210" max.

(5.334 max).

eA = 0.300 BSC

(7.620 BSC)

DIMENSIONS (Inches)

Minimum/Maximum

(mm)

16–PIN

0.115/0.195

(2.921/4.953)

0.014/0.022

(0.356/0.559)

0.045/0.070

(1.143/1.778)

0.008/0.014

(0.203/0.356)

0.780/0.800

(19.812/20.320)

0.300/0.325

(7.620/8.255)

0.240/0.280

(6.096/7.112)

0.115/0.150

(2.921/3.810)

0°/ 15°

(0°/15°)

18–PIN

0.115/0.195

(2.921/4.953)

0.014/0.022

(0.356/0.559)

0.045/0.070

(1.143/1.778)

0.008/0.014

(0.203/0.356)

0.880/0.920

(22.352/23.368)

0.300/0.325

(7.620/8.255)

0.240/0.280

(6.096/7.112)

0.115/0.150

(2.921/3.810)

0°/ 15°

(0°/15°)

Page 17

PACKAGE: PLASTIC

SMALL OUTLINE (SOIC)

DIMENSIONS (Inches)

Minimum/Maximum

(mm) A

16–PIN

0.090/0.104 (2.29/2.649)

0.004/0.012

(0.102/0.300)

0.013/0.020

(0.330/0.508)

0.398/0.413

(10.10/10.49)

0.291/0.299

(7.402/7.600)

0.050 BSC

(1.270 BSC)

0.394/0.419

(10.00/10.64)

0.016/0.050

(0.406/1.270)

0°/8°

(0°/8°)

18–PIN

0.090/0.104

(2.29/2.649))

0.004/0.012

(0.102/0.300)

0.013/0.020

(0.330/0.508)

0.447/0.463

(11.35/11.74)

0.291/0.299

(7.402/7.600)

0.050 BSC

(1.270 BSC)

0.394/0.419

(10.00/10.64)

0.016/0.050

(0.406/1.270)

0°/8°

(0°/8°)

Page 18

P ACKA GE: PLASTIC THIN SMALL

OUTLINE (TSSOP)

DIMENSIONS

in inches (mm)

Minimum/Maximum

16–PIN

- /0.043 (- /1.10)

0.002/0.006 (0.05/0.15)

0.007/0.012 (0.19/0.30)

0.193/0.201 (4.90/5.10)

0.169/0.177 (4.30/4.50)

0.026 BSC (0.65 BSC)

0.126 BSC (3.20 BSC)

0.020/0.030 (0.50/0.75)

0°/8°

20–PIN

- /0.043 (- /1.10)

0.002/0.006 (0.05/0.15)

0.007/0.012 (0.19/0.30)

0.252/0.260 (6.40/6.60)

0.169/0.177 (4.30/4.50)

0.026 BSC (0.65 BSC)

0.126 BSC (3.20 BSC)

0.020/0.030 (0.50/0.75)

0°/8°

Page 19

ORDERING INFORMATION

Model Temperature Range Package Type

SP3222ECA ............................................. 0˚C to +70˚C .......................................... 20-Pin SSOP

SP3222ECP ............................................. 0˚C to +70˚C ............................................18-Pin PDIP

SP3222ECT ............................................. 0˚C to +70˚C ........................................... 18-Pin SOIC

SP3222ECY ............................................. 0˚C to +70˚C ........................................ 20-Pin TSSOP

SP3222EEA ............................................ -40˚C to +85˚C ........................................ 20-Pin SSOP

SP3222EEP ............................................ -40˚C to +85˚C ..........................................18-Pin PDIP

SP3222EET ............................................ -40˚C to +85˚C ......................................... 18-Pin SOIC

SP3222EEY ............................................ -40˚C to +85˚C ...................................... 20-Pin TSSOP

SP3232ECA............................................. 0˚C to +70˚C .......................................... 16-Pin SSOP

SP3232ECP............................................. 0˚C to +70˚C ............................................16-Pin PDIP

SP3232ECT ............................................. 0˚C to +70˚C .................................. 16-Pin Wide SOIC

SP3232ECY ............................................. 0˚C to +70˚C ........................................ 16-Pin TSSOP

SP3232EEA ............................................ -40˚C to +85˚C ........................................ 16-Pin SSOP

SP3232EEP ............................................ -40˚C to +85˚C ..........................................16-Pin PDIP

SP3232EET ............................................ -40˚C to +85˚C ................................ 16-Pin Wide SOIC

SP3232EEY ............................................ -40˚C to +85˚C ...................................... 16-Pin TSSOP

Please consult the factory for pricing and availability on a Tape-On-Reel option.

Corporation

SIGNAL PROCESSING EXCELLENCE

Sipex Corporation Headquarters and

Sales Office

22 Linnell Circle Billerica, MA 01821 TEL: (978) 667-8700 FAX: (978) 670-9001 e-mail: sales@sipex.com

Sales Office

233 South Hillview Drive Milpitas, CA 95035 TEL: (408) 934-7500 FAX: (408) 935-7600

Sipex Corporation reserves the right to make changes to any products described herein. Sipex does not assume any liability arising out of the application or use of any product or circuit described hereing; neither does it convey any license under its patent rights nor the rights of others.

Datasheet SP3222ECA, SP3222ECP, SP3222ECT, SP3222ECY, SP3222EEA Datasheet (Sipex Corporation)

Specifications and Main Features

Frequently Asked Questions

User Manual