Datasheet SP3239E Datasheet (Sipex)

T4IN

1

2

3

4

25

26

27

28

5

6

7

24

23

22

SHUTDOWN

C2-

V-

R1IN

R2IN

R3IN

NC

C2+

C1-

GND

V

CC

V+

T1IN

8

9

10

11

18

19

20

21

12

13

14

17

16

15

T1OUT

T2OUT

T3OUT

T3IN

T2IN

T5IN

R3OUT

R2OUT

R1OUT

SP3239E

C1+

T4OUT

T5OUT

NC

®

SP3239E

Intelligent +3.0V to +5.5V RS-232 Transceivers

FEATURES

■ Meets true EIA/TIA-232-F Standards from a +3.0V to +5.5V power supply

■ Interoperable with EIA/TIA-232 and adheres to EIA/TIA-562 down to a +2.7V power source

■ Minimum 250Kbps data rate under load

■ Regulated Charge Pump Yields Stable

RS-232 Outputs Regardless of V Variations

■ Enhanced ESD Specifications:

+15KV Human Body Model +15KV IEC1000-4-2 Air Discharge +8KV IEC1000-4-2 Contact Discharge

The SP3239E device is an RS-232 transceiver solution intended for portable or hand-held applications such as notebook and palmtop computers. The SP3239E uses an internal high-efficiency, charge-pump power supply that requires only 0.1µF capacitors in 3.3V operation. This charge pump and Sipex's driver architecture allow the SP3239E device to deliver compliant RS-232 performance from a single power supply ranging from +3.0V to +5.0V. The SP3239E is a 5-driver/3-receiver device, ideal for laptop/notebook computer and PDA applications. The SP3239E includes one complementary receiver that remains alert to monitor an external device's Ring Indicate signal while the device is shutdown.

eciveDseilppuSrewoP232-SR

E3223PS V5.5+otV0.3+22sroticapac4SEYSEY02

Applicable U.S. Patents - 5,306,954; and other patents pending.

E3423PS V5.5+otV0.3+35sroticapac4SEYSEY82

E8323PS V5.5+otV0.3+53sroticapac4SEYSEY82

E9323PS V5.5+otV0.3+53sroticapac4ONSEY82

E9423PS V5.5+otV0.3+53sroticapac4ONON42

CC

Now Available in Lead Free Packaging

DESCRIPTION

SELECTION TABLE

srevirD

srevieceR

232-SR

lanretxE

stnenopmoC

®

ENIL-NOOTUA

yrtiucriC

1

etatS-3LTTfo.oN

sniP

ABSOLUTE MAXIMUM RATINGS

These are stress ratings only and functional operation of the device at these ratings or any other above those indicated in the operation sections of the specifications below is not implied. Exposure to absolute maximum

Power Dissipation per package 28-pin SSOP (derate 11.2mW/ 28-pin TSSOP (derate 13.2mW/

o

C above +70oC).................900mW

o

C above +70oC)...............1100mW

rating conditions for extended periods of time may affect reliability and cause permanent damage to the device. V

...................................................... -0.3V to +6.0V

CC

V+ (NOTE 1) ...................................... -0.3V to +7.0V

V- (NOTE 1) ....................................... +0.3V to -7.0V

V+ + |V-| (NOTE 1) ........................................... +13V

ICC (DC VCC or GND current) ......................... +100mA

Input Voltages

SHUTDOWN, .................................... .-0.3V to +6.0V

RxIN .................................................................. +25V

Output Voltages

TxOUT ........................................................... +13.2V

RxOUT ..................................... -0.3V to (VCC + 0.3V)

Short-Circuit Duration

TxOUT .................................................... Continuous

Storage Temperature ...................... -65°C to +150°C

Note 1: V+ and V- can have maximum magnitudes of 7V, but their absolute difference cannot exceed 13V.

VCC = +3.0 to +5.5, C1 -C4 = 0.1µF (tested at 3.3V + 5%), C1-C4 = 0.22µF (tested at 3.3V + 10%), C1 = 0.047µF, and C2-C4 = 0.33µF (tested at 5.0V

ELECTRICAL CHARACTERISTICS

+ 10%), TA = T

to T

, unless otherwise noted. Typical values are at TA = +25°C.)

MIN

MAX

RETEMARAP.NIM.PYT.XAMSTINUSNOITIDNOC

SCITSIRETCARAHCCD

nwodtuhS,tnerruCylppuS0.101

tnerruCylppuS3.00.1

µA

Am

STUPTUOREVIECERDNASTUPNICIGOL

dlohserhTcigoLtupnI

8.0V

4.2

tnerruCegakaeLtupnI+

10.0+0.1

tnerruCegakaeLtuptuO+50.0+01

µA

WOLegatloVtuptuO4.0VI

HGIHegatloVtuptuOV

6.0-VCC1.0-VI

CC

,DNG=NWODTUHS

VroDNG=NIxT

CC

V=NWODTUHS

,

daolon

V

CC

NIxT,V0.5+roV3.3+=

NWODTUHS

NWODTUHS,NIxT

T

C°52=

A

delbasiDsrevieceR

Am6.1=

TUO

Am0.1-=

2

VCC = +3.0 to +5.5, C1 -C4 = 0.1µF (tested at 3.3V + 5%), C1-C4 = 0.22µF (tested at 3.3V + 10%), C1 = 0.047µF, and C2-C4 = 0.33µF (tested at 5.0V

ELECTRICAL CHARACTERISTICS

+ 10%), TA = T

to T

, unless otherwise noted. Typical values are at TA = +25°C.)

MIN

MAX

RETEMARAP.NIM.PYT.XAMSTINUSNOITIDNOC

STUPTUOREVIRD

gniwSegatloVtuptuO0.5±4.5±V K3htiwdedaolstuptuorevirdllA Ω

ecnatsiseRtuptuO003

Ω

tnerruCtiucriC-trohStuptuO53±06±AmV

STUPNIREVIECER

egnaRegatloVtupnI52-52V

WOLdlohserhTtupnI6.02.1VV

WOLdlohserhTtupnI8.05.1VV

HGIHdlohserhTtupnI5.14.2VV

HGIHdlohserhTtupnI8.14.2VV

siseretsyHtupnI5.0V

ecnatsiseRtupnI357kΩ

SCITSIRETCARAHCGNIMIT

etaRataDmumixaM052spbkR

DNGot

V

CC

DNG=

TUO

V3.3=

CC

V0.5=

CC

V3.3=

CC

V0.5=

CC

k3= ,Ω C

L

gnihctiws

V,V0=-V=+V=

V2±=

TUO

revirdeno,Fp0001=

yaleDnoitagaporPrevieceR

t

LHP

t

HLP

51.0

µS

C

Fp051=

L

,tuptuoreviecerottupnirevieceR

emiTelbanEtuptuOrevieceR002snnoitarepolamroN

emiTelbasiDtuptuOrevieceR002snnoitarepolamroN

wekSrevirD001sntI

wekSrevieceR05sntI

etaRwelSnoigeR-noitisnarT03/V µsV

t-

T,I

HLP

LHP

t-

HLP

LHP

CC

52=OC

A

I

R,V3.3=

k3= ,Ω T

L

O

52=

BMA

otV0.3-morfnekatstnemerusaem

V0.3-otV0.3+roV0.3+

3

,C

Unless otherwise noted, the following perfomance characteristics apply for VCC = +3.3V, 250kbps data rate, all drivers loaded with 3kΩ, 0.1µF charge

TYPICAL PERFOMANCE CHARACTERISTICS

pump capacitors, and T

TRANSMITTER OUTPUT vs. LOAD CAPACITANCE

6

4

2

0

0 1000 2000 3000 4000 5000

-2

-4

-6

60

50

40

30

20

10

0

0 1000 2000 3000 4000 5000

Figure 3. Supply Current VS. Load Capacitance when Transmitting Data

= +25°C.

AMB

pF

SUPPLY CURRENT vs LOAD CAPACITANCE

pF

VOH VOL

250Kbps 120Kbps 20Kbps

SLEW RATE vs. LOAD CAPACITANCE

25

20

15

10

5

0

0 1000 2000 3000 4000 5000

pF

POS. SR NEG SR

4

PIN DESCRIPTION

EMANNOITCNUF

+2C .2Croticapacpmup-egrahclacirtemmysehtfolanimretevitisoP 1

DNG.dnuorG 2

-2C .2Croticapacpmup-egrahclacirtemmysehtfolanimretevitageN 3

-V.pmupegrahcehtybdetarenegtuptuoV5.5-detalugeR 4

TUO.tuptuorevird232-SR 5

T

1

T

TUO.tuptuorevird232-SR 6

2

TUO.tuptuorevird232-SR 7

T

3

R

NI.tupnireviecer232-SR 8

1

NI.tupnireviecer232-SR 9

R

2

T

TUO.tuptuorevird232-SR 01

4

NI.tupnireviecer232-SR 11

R

3

T

TUO.tuptuorevird232-SR 21

5

CN.tcennocoN 31

NWODTUHS.pmupegrahcdnasrevirdnwodtuhsotWOLcigolylppA 41

NIP

.ON

CN.noitarepolamronrofHGIHeitrotcennoCoN 51

TUO.nwodtuhsnievitca,tuptuo1-reviecergnitrevni-noN 61

R

1

NI.tupnirevirdSOMC/LTT 71

T

5

TUO.tuptuoreviecerSOMC/LTT 81

R

3

T

NI.tupnirevirdSOMC/LTT 91

4

TUO.tuptuoreviecerSOMC/LTT 02

R

2

R

TUO.tuptuoreviecerSOMC/LTT 12

1

NI.tupnirevirdSOMC/LTT 22

T

3

T

NI.tupnirevirdSOMC/LTT 32

2

NI.tupnirevirdSOMC/LTT 42

T

1

-1C .1Croticapacpmup-egrahclacirtemmysehtfolanimretevitageN 52

V

CC

.egatlovylppusV5.5+otV0.3+ 62

+V.pmupegrahcehtybdetarenegtuptuoV5.5+detalugeR 72

+1C 1Croticapacpmup-egrahcrelbuodegatlovehtfolanimretevitisoP 82

Table 1. Device Pin Description

5

SHUTDOWN

Figure 4. SP3239E Pinout Configuration

C2+

GND

C2-

T1OUT

T2OUT

T3OUT

R1IN

R2IN

T4OUT

R3IN

T5OUT

NC

1

2

3

4

V-

5

SP3239E

6

7

8

9

10

11

12

13

14

28

C1+

V+

27

V

CC

26

25

C1-

24

T1IN

T2IN

23

22

T3IN

R1OUT

21

20

R2OUT

T4IN

19

18

R3OUT

T5IN

17

16

R1OUT

15

NC

V

CC

C5

C1

C2

TTL/CMOS

INPUTS

TTL/CMOS

OUTPUTS

+

0.1µF

VCC

28

C1+

25

C1-

1

C2+

3

C2-

T1IN

24

T2IN

23

T

22

T4IN

19

T

17

R1OUT

16

R1OUT

21

R

20

R

18

14

SHUTDOWN

3

5

IN

OUT

2

3

OUT

26

CC

V

SP3239E

5kΩ

GND

2

V+

T

OUT

1

T

OUT

2

T

OUT

3

T4OUT

T

OUT

5

R

1

R2IN

R

3

27

4

V-

C3

C4

+

0.1µF

5

6

7

RS-232 OUTPUTS

10

12

IN

8

9

RS-232 INPUTS

IN

11

Figure 5. SP3239E Typical Operating Circuit

6

DESCRIPTION

The SP3239E device meets the EIA/TIA-232 and ITU-T V.28/V.24 communication protocols and can be implemented in battery-powered, portable, or hand-held applications such as notebook or palmtop computers. The SP3239E device features Sipex's proprietary and patented (U.S. #5,306,954) on-board charge pump circuitry that generates ±5.5V RS-232 voltage levels from a single +3.0V to +5.5V power supply. The SP3239E device can guarantee a data rate of 250kbps fully loaded.

The SP3239E is a 5-driver/3-receiver device, ideal for portable or hand-held applications. The SP3239E includes one complementary always-active receiver that can monitor an external device (such as a modem) in shutdown. This aids in protecting the UART or serial controller IC by preventing forward biasing of the protection diodes where VCC may be disconnected.

V

28

25

1

3

24

23

22

19

17

16

21

20

18

14

C1+

C1-

C2+

C2-

T1IN

T2IN

T

IN

3

T4IN

T

IN

5

R1OUT

R

OUT

1

OUT

R

2

R

OUT

3

SHUTDOWN

CC

26

V

CC

SP3239E

GND

2

27

V+

+

0.1µF

C3

4

V-

0.1µF

C4

+

OUT

T

5

1

OUT

T

6

2

T

OUT

7

3

RS-232 OUTPUTS

T4OUT

10

T

OUT

12

5

R

IN

1

8

5kΩ

R

IN

9

2

RS-232

5kΩ

INPUTS

R

IN

11

3

+

0.1µF

C5

+

0.1µF

C1

+

C2

0.1µF

RxD

CTS

DSR

DCD

RI

TxD

RTS

DTR

V

CC

V

IN

RESET

UART

or

Serial µC

µP

Supervisor

IC

Figure 6. Interface Circuitry Controlled by Microprocessor Supervisory Circuit

The SP3239E device is an ideal choice for power sensitive designs.

THEORY OF OPERATION

The SP3239E device is made up of four basic circuit blocks: 1. Drivers, 2. Receivers,

3. the Sipex proprietary charge pump, and

Drivers

The drivers are inverting level transmitters that convert TTL or CMOS logic levels to 5.0V EIA/ TIA-232 levels with an inverted sense relative to the input logic levels. Typically, the RS-232 output voltage swing is +5.4V with no load and +5V minimum fully loaded. The driver outputs are protected against infinite short-circuits to ground without degradation in reliability. These drivers comply with the EIA-TIA-232F and all previous RS-232 versions. All unused driver inputs must be connected to V

or GND.

CC

The drivers can guarantee a data rate of 250kbps fully loaded with 3kΩ in parallel with 1000pF, ensuring compatibility with PC-to-PC communication software.

The slew rate of the driver output is internally limited to a maximum of 30V/µs in order to meet the EIA standards (EIA RS-232D 2.1.7, Paragraph 5). The transition of the loaded output from HIGH to LOW also meets the monotonicity requirements of the standard.

Figure 7 shows a loopback test circuit used to test the RS-232 Drivers. Figure 8 shows the test results of the loopback circuit with all five drivers active at 120kbps with typical RS-232 loads in parallel with 1000pF capacitors. Figure 6 shows the test results where one driver was active at 250kbps and all five drivers loaded with an RS232 receiver in parallel with a 1000pF capacitor. A solid RS-232 data transmission rate of 120kbps provides compatibility with many designs in personal computer peripherals and LAN applications.

7

Receivers

The receivers convert ±5.0V EIA/TIA-232 levels to TTL or CMOS logic output levels.

The truth table logic of the driver and receiver outputs can be found in Table 2.

The SP3239E includes an additional noninverting receiver with an output R1OUT. R1OUT is an extra output that remains active and monitors activity while the other receiver outputs are forced into high impedance. This allows Ring Indicator (RI) from a peripheral to be monitored without forward biasing the TTL/CMOS inputs of the other devices connected to the receiver outputs.

C5

C1

C2

LOGIC

INPUTS

LOGIC

OUTPUTS

+

0.1µF

V

CC

C1+

C1-

C2+

SP3239E

C2-

TxIN

RxOUT

SHUTDOWN

V

GND

CC

5kΩ

TxOUT

RxIN

V+

V-

C3

C4

+

0.1µF

+

1000pF

Since receiver input is usually from a transmission line where long cable lengths and system interference can degrade the signal, the inputs have a typical hysteresis margin of 500mV. This ensures that the receiver is virtually immune to noisy transmission lines. Should an input be left unconnected, an internal 5kΩ pulldown resistor to ground will commit the output of the receiver to a HIGH state.

Charge Pump

The charge pump is a Sipex–patented design (U.S. #5,306,954) and uses a unique approach compared to older less–efficient designs. The

Figure 7. Loopback Test Circuit for RS-232 Driver Data Transmission Rates

charge pump still requires four external capacitors, but uses a four–phase voltage shifting technique to attain symmetrical 5.5V power supplies. The internal power supply consists of a regulated dual charge pump that provides output voltages 5.5V regardless of the input voltage (VCC) over the +3.0V to +5.5V range. This is important to maintain compliant RS-232 levels regardless of power supply fluctuations.

The charge pump operates in a discontinuous mode using an internal oscillator. If the output

Figure 8. Loopback Test Circuit Result at 120kbps (All Drivers Fully Loaded)

Figure 9. Loopback Test Circuit result at 250kbps (All Drivers Fully Loaded)

8

voltages are less than a magnitude of 5.5V, the charge pump is enabled. If the output voltages exceed a magnitude of 5.5V, the charge pump is disabled. This oscillator controls the four phases of the voltage shifting (Figure 12). A description of each phase follows.

Phase 1 (Figure 10)

— VSS charge storage — During this phase of the clock cycle, the positive side of capacitors C1 and C2 are initially charged to VCC. C then switched to GND and the charge in C transferred to C

–

. Since C

2

+

is connected to

2

+

is

l

–

is

1

VCC, the voltage potential across capacitor C2 is now 2 times VCC.

Phase 4 (Figure 14)

— VDD transfer — The fourth phase of the clock connects the negative terminal of C2 to GND, and transfers this positive generated voltage across C2 to C4, the VDD storage capacitor. This voltage is regulated to +5.5V. At this voltage, the internal oscillator is disabled. Simultaneous with the transfer of the voltage to C4, the positive side of capacitor C1 is switched to V

CC

and the negative side is connected to GND, allowing the charge pump cycle to begin again. The charge pump cycle will continue as long as the operational conditions for the internal oscillator are present.

Phase 2 (Figure 11)

— VSS transfer — Phase two of the clock connects the negative terminal of C2 to the V

SS

storage capacitor and the positive terminal of C to GND. This transfers a negative generated voltage to C3. This generated voltage is regulated to a minimum voltage of -5.5V. Simultaneous with the transfer of the voltage to C3, the positive side of capacitor C1 is switched to VCC and the negative side is connected to GND.

Phase 3 (Figure 13)

— VDD charge storage — The third phase of the clock is identical to the first phase — the charge transferred in C1 produces –VCC in the negative terminal of C1, which is applied to the negative side of capacitor C2. Since C

+

is at VCC, the

2

voltage potential across C2 is 2 times VCC.

Since both V+ and V– are separately generated from VCC, in a no–load condition V+ and V– will be symmetrical. Older charge pump approaches that generate V– from V+ will show a decrease in

2

the magnitude of V– compared to V+ due to the inherent inefficiencies in the design.

The clock rate for the charge pump typically operates at 500kHz. The external capacitors can be as low as 0.1µF with a 16V breakdown voltage rating.

9

VCC = +5V

–5V

+5V

–5V

V

SS

Storage Capacitor

V

DD

Storage Capacitor

C

1

C

2

C

3

C

4

+

++

–

––

VCC = +5V

–10V

V

SS

Storage Capacitor

V

DD

Storage Capacitor

C

1

C

2

C

3

C

4

+

++

–

––

VCC = +5V

–5V –5V

+5V

V

SS

Storage Capacitor

V

DD

Storage Capacitor

C

1

C

2

C

3

C

4

+

++

–

––

Figure 10. Charge Pump — Phase 1

Figure 11. Charge Pump — Phase 2

a) C

T[]

+6V

2+

1

2

T

0V

b) C2-

T

Ch1 2.00V Ch2 2.00V M 1.00µs Ch1 1.96V

-6V

Figure 12. Charge Pump Waveforms

Figure 13. Charge Pump — Phase 3

VCC = +5V

+10V

++

C

Figure 14. Charge Pump — Phase 4

1

C

10

2

––

C

4

+

–

Storage Capacitor

V

DD

+

–

V

C

3

Storage Capacitor

SS

+

C5

+

C1

+

C2

0.1µF

To µP Supervisor

Circuit

0.1µF

28

0.1µF

C1+

25

C1-

1

C2+

3

C2-

R1OUT

16

R1OUT

21

R

20

R

18

T1IN

24

T2IN

23

T

22

T4IN

19

T

17

V

CC

14

SHUTDOWN

13

ONLINE

15

STATUS

DB-9 Connector Pins:

1. Received Line Signal Detector

2. Received Data

3. Transmitted Data

4. Data Terminal Ready

5. Signal Ground (Common)

2

3

5

OUT

IN

V

CC

26

V

CC

SP3238

GND

2

5kΩ

27

V+

4

V-

R

IN

8

1

R2IN

9

IN

R

11

3

OUT

T

5

1

OUT

T

6

2

T

OUT

7

3

T4OUT

10

T

OUT

12

5

6. DCE Ready

7. Request to Send

8. Clear to Send

9. Ring Indicator

+

0.1µF

C3

0.1µF

C4

+

DB-9

Connector

6 7 8 9

1 2 3 4 5

Figure 15. Circuit for the connectivity of the SP3239E with a DB-9 connector

NWODTUHS

TUPNI

TALANGIS232-SR

T

TUORXTUOR1TUO

X

TUPNIREVIECER

REVIECSNART

SUTATS

HGIHSEYevitcAevitcAevitcAnoitarepOlamroN

WOLSEYZ-hgiHZ-hgiHevitcAnwodtuhS

WOLONZ-hgiHZ-hgiHevitcAnwodtuhS

Table 2. Shutdown Logic

11

ESD TOLERANCE

The SP3239E device incorporates ruggedized ESD cells on all driver output and receiver input pins. The ESD structure is improved over our previous family for more rugged applications and environments sensitive to electro-static discharges and associated transients. The improved ESD tolerance is at least +15kV without damage nor latch-up.

There are different methods of ESD testing applied:

a) MIL-STD-883, Method 3015.7 b) IEC1000-4-2 Air-Discharge c) IEC1000-4-2 Direct Contact

The Human Body Model has been the generally accepted ESD testing method for semiconductors. This method is also specified in MIL-STD-883, Method 3015.7 for ESD testing. The premise of this ESD test is to simulate the human body’s potential to store electro-static energy and discharge it to an integrated circuit. The simulation is performed by using a test model as shown in Figure 19. This method will test the IC’s capability to withstand an ESD transient during normal handling such as in manufacturing areas where the ICs tend to be handled frequently.

The IEC-1000-4-2, formerly IEC801-2, is generally used for testing ESD on equipment and systems. For system manufacturers, they must guarantee a certain amount of ESD protection since the system itself is exposed to the outside environment and human presence. The premise with IEC1000-4-2 is that the system is required to withstand an amount of static electricity when ESD is applied to points and surfaces of the equipment that are accessible to personnel during

normal usage. The transceiver IC receives most of the ESD current when the ESD source is applied to the connector pins. The test circuit for IEC1000-4-2 is shown on Figure 20. There are two methods within IEC1000-4-2, the Air Discharge method and the Contact Discharge method.

With the Air Discharge Method, an ESD voltage is applied to the equipment under test (EUT) through air. This simulates an electrically charged person ready to connect a cable onto the rear of the system only to find an unpleasant zap just before the person touches the back panel. The high energy potential on the person discharges through an arcing path to the rear panel of the system before he or she even touches the system. This energy, whether discharged directly or through air, is predominantly a function of the discharge current rather than the discharge voltage. Variables with an air discharge such as approach speed of the object carrying the ESD potential to the system and humidity will tend to change the discharge current. For example, the rise time of the discharge current varies with the approach speed.

The Contact Discharge Method applies the ESD current directly to the EUT. This method was devised to reduce the unpredictability of the ESD arc. The discharge current rise time is constant since the energy is directly transferred without the air-gap arc. In situations such as hand held systems, the ESD charge can be directly discharged to the equipment from a person already holding the equipment. The current is transferred on to the keypad or the serial port of the equipment directly and then travels through the PCB and finally to the IC.

R

C

SW1

DC Power Source

Figure 16. ESD Test Circuit for Human Body Model

R

S

SW2

C

S

Device Under Test

12

Contact-Discharge Module

R

C

R

S

R

V

S

V

SW1

DC Power Source

Figure 17. ESD Test Circuit for IEC1000-4-2

The circuit model in Figures 19 and 20 represent the typical ESD testing circuit used for all three methods. The CS is initially charged with the DC power supply when the first switch (SW1) is on. Now that the capacitor is charged, the second switch (SW2) is on while SW1 switches off. The voltage stored in the capacitor is then applied through RS, the current limiting resistor, onto the device under test (DUT). In ESD tests, the SW2 switch is pulsed so that the device under test receives a duration of voltage.

For the Human Body Model, the current limiting resistor (RS) and the source capacitor (CS) are

1.5kΩ and 100pF, respectively. For IEC-10004-2, the current limiting resistor (RS) and the source capacitor (CS) are 330Ω and 150pF, respectively.

SW2

C

S

and RV add up to 330Ω for IEC1000-4-2.

R

RS and RV add up to 330Ω for IEC1000-4-2.

S

i ➙

30A

15A

0A

t=0ns t=30ns

Figure 18. ESD Test Waveform for IEC1000-4-2

t ➙

Device Under Test

The higher CS value and lower RS value in the IEC1000-4-2 model are more stringent than the Human Body Model. The larger storage capacitor injects a higher voltage to the test point when SW2 is switched on. The lower current limiting resistor increases the current charge onto the test

DEVICE PIN HUMAN BODY IEC1000-4-2 TESTED MODEL Air Discharge Direct Contact Level

Driver Outputs ±15kV ±15kV ±8kV 4 Receiver Inputs ±15kV ±15kV ±8kV 4

Table 3. Transceiver ESD Tolerance Levels

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PACKAGE: 28 PIN SSOP

N

1

INDEX AREA

D

x

2

D

E1

2

E1

2

28 Pin SSOP JEDEC MO-150 (AH) Variation

SYMBOL

MIN NOM MAX

A--2 A1 0.05 - A2 1.65 1.75 1.85

b 0.22 - 0.38

c 0.09 - 0.25

D 9.9 10.2 10.5

E 7.4 7.8 8.2

E1 5 5.3 5.6

L 0.55 0.75 0.95

L1

1.25 REF

ø0º4º8º

SEE DETAIL “A”

E

2 NX R R1

Gauge Plane

Seaing Plane

L1

A

L

Ø

DETAIL A

A2

A

Seating Plane

b

WITH LEAD FINISH

A1

Note: Dimensions in (mm)

c

BASE METAL

b

Section A-A

14

PACKAGE: 28 PIN TSSOP

D

e

Ø2

E

E1

12

INDEX AREA

D

E1

x

2

b

28 Pin TSSOP JEDEC MO-153 (AE)

Variation

SYMBOL

MIN NOM MAX

A--1.2 A1 0.05 - 0.15 A2 0.8 1 1.05

b 0.19 - 0.3

c 0.09 - 0.2

D 9.6 9.7 9.8

e

E

0.65 BSC

6.40 BSC

E1 4.3 4.4 4.5

L 0.45 0.6 0.75

L1

1.00 REF Ø1 0º - 8º Ø2 Ø3

12º REF 12º REF

Note: Dimensions in (mm)

A2

A1

A

Seating Plane

Seaing Plane

Ø3

L

L1

Ø1

DETAIL A

SEE DETAIL “A”

B

b

C

Section B-B

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ORDERING INFORMATION

Model Temperature Range Package Types SP3239ECA 0°C to +70°C 28-pin SSOP SP3239ECA/TR 0°C to +70°C 28-pin SSOP SP3239ECY 0°C to +70°C 28-pin TSSOP SP3239ECY/TR 0°C to +70°C 28-pin TSSOP

○○○○○○○○○○○○○○○

○○○○○○○○○○○○○

○○○○○○○○○○○○○○○

○ ○○○○○○○○○○○○

○○○○○○○○○○○○○○○

○○○○○○○○○○○○○○

○○○○○○○○○○○○○

SP3239EEA -40°C to +85°C 28-pin SSOP SP3239EEA/TR -40°C to +85°C 28-pin SSOP SP3239EEY -40°C to +85°C 28-pin TSSOP SP3239EEY/TR -40°C to +85°C 28-pin TSSOP

○○○○○○○○○○○○○○○

○○○○○○○○○○○○○

○○○○○○○○○○○○○○○

○○○○○○○○○○○○○

Available in lead free packaging. To order add “-L” suffix to part number.

Example: SP3239EEA/TR = standard; SP3239EEA-L/TR = lead free

/TR = Tape and Reel

Pack quantity is 1,500 for SSOP or TSSOP

CLICK HERE TO ORDER SAMPLES

Corporation

ANALOG EXCELLENCE

Sipex Corporation

Headquarters and Sales Office

233 South Hillview Drive Milpitas, CA 95035 TEL: (408) 934-7500 FAX: (408) 935-7600

Sipex Corporation reserves the right to make changes to any products described herein. Sipex does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others.

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