Datasheet SP3243ECA, SP3243ECT, SP3243EEA, SP3243EET, SP3223ECA Datasheet (Sipex Corporation)

®

SP3223E/3243E

Intelligent +3.0V to +5.5V RS-232 Transceivers

■ Meets true EIA/TIA-232-F Standards from a +3.0V to +5.5V power supply

■ Interoperable with EIA/TIA-232 and adheres to EIA/TIA-562 down to a +2.7V power source

■

Auto-Online

wakes up from a 1µA shutdown

■ Minimum 120Kbps data rate under load

■ Regulated Charge Pump Yields Stable

RS-232 Outputs Regardless of V Variations

■ Enhanced ESD Specifications:

+15KV Human Body Model +15KV IEC1000-4-2 Air Discharge +8KV IEC1000-4-2 Contact Discharge

DESCRIPTION

The SP3223E and 3243E products are RS-232 transceiver solutions intended for portable or hand-held applications such as notebook and palmtop computers. The SP3223E and 3243E use an internal high-efficiency, charge-pump power supply that requires only 0.1µF capacitors in 3.3V operation. This charge pump and Sipex's driver architecture allow the SP3223E/ 3243E series to deliver compliant RS-232 performance from a single power supply ranging from +3.3V to +5.0V. The SP3223E is a 2-driver/2-receiver device, and the SP3243E is a 3-driver/5-receiver device ideal for laptop/notebook computer and PDA applications. The SP3243E includes one complementary receiver that remains alert to monitor an external device's Ring Indicate signal while the device is shutdown.

™

circuitry automatically

CC

The

Auto-Online

feature allows the device to automatically "wake-up" during a shutdown state when an RS-232 cable is connected and a connected peripheral is turned on. Otherwise, the device automatically shuts itself down drawing less than 1µA.

SELECTION TABLE

eciveDseilppuSrewoP232-SR

srevirD E3223PSV5.5+otV0.3+22sroticapac4SEYSEY02 E3423PSV5.5+otV0.3+35sroticapac4SEYSEY82

Applicable U.S. Patents - 5,306,954; and other patents pending.

232-SR

srevieceR

1

lanretxE

stnenopmoC

enilnO-otuA

yrtiucriC

etatS-3LTTfo.oN

sniP

ABSOLUTE MAXIMUM RATINGS

These are stress ratings only and functional operation of the device at these ratings or any other above those indicated in the operation sections of the specifications below is not implied. Exposure to absolute maximum rating conditions for extended periods of time may

Power Dissipation per package

28-pin PDIP (derate 16.0mW/oC above+70oC).....1300mW

20-pin SSOP (derate 9.25mW/oC above +70oC)....750mW

20-pin TSSOP (derate 11.1mW/oC above +70oC)..900mW 28-pin SOIC (derate 12.7mW/oC above +70oC)...1000mW

28-pin SSOP (derate 11.2mW/oC above +70oC)....900mW

affect reliability and cause permanent damage to the device.

VCC.......................................................-0.3V to +6.0V

V+ (NOTE 1).......................................-0.3V to +7.0V

V- (NOTE 1)........................................+0.3V to -7.0V

V+ + |V-| (NOTE 1)...........................................+13V

ICC (DC VCC or GND current).........................+100mA

Input Voltages

TxIN, ONLINE,

SHUTDOWN, EN (SP3223E).................-0.3V to +6.0V

RxIN...................................................................+15V

Output Voltages

TxOUT...............................................................+15V

RxOUT, STATUS.......................-0.3V to (VCC + 0.3V)

Short-Circuit Duration

TxOUT.....................................................Continuous

Storage Temperature......................-65°C to +150°C

NOTE 1: V+ and V- can have maximum magnitudes of 7V, but their absolute difference cannot exceed 13V.

SPECIFICATIONS

Unless otherwise noted, the following specifications apply for VCC = +3.0V to +5.5V with T Typical values apply at VCC = +3.3V or +5.0V and T

AMB

= 25°C.

RETEMARAP.NIM.PYT.XAMSTINUSNOITIDNOC

AMB

= T

MIN

to T

MAX

.

SCITSIRETCARAHCCD

µA

V

CC

µA

V

CC

,

V=NWODTUHS

CC

T,V3.3+=

BMA

C°52+=

,DNG=NWODTUHS

,DNG=ENILNO,nepoNIxRllA

T,V3.3+=

BMA

V,daolon

CC

C°52+=

,

CC

T,V3.3+=

BMA

C°52+=

delbasiD

,tnerruCylppuS

enilnO-otuA

0.101

nwodtuhS,tnerruCylppuS0.101

enilnO-otuA

3.00.1AmV=NWODTUHS=ENILNO

STUPTUOREVIECERDNASTUPNICIGOL

dlohserhTcigoLtupnI

WOL

8.0V

HGIH0.2

tnerruCegakaeLtupnI10.0±0.1±

tnerruCegakaeLtuptuO50.0±01±

WOLegatloVtuptuO4.0VI

HGIHegatloVtuptuOV

6.0-VCC1.0-VI

CC

V

CC

(NEE3223PS,ENILNO,)

µA

T

BMA

µA

TUO

NWODTUHS

C°52+=

Am6.1=

Am0.1-=

NIxT,V0.5+roV3.3+=,

,NWODTUHS,ENILNO,NE,NIxT

delbasidsrevieceR

2

SPECIFICATIONS (continued)

Unless otherwise noted, the following specifications apply for VCC = +3.0V to +5.5V with T Typical values apply at VCC = +3.3V or +5.0V and T

AMB

= 25°C.

RETEMARAP.NIM.PYT.XAMSTINUSNOITIDNOC

STUPTUOREVIRD

AMB

= T

MIN

to T

MAX

.

gniwSegatloVtuptuO0.5±4.5±V K3htiwdedaolstuptuorevirdllA Ω

T,DNGot

BMA

ecnatsiseRtuptuO003ΩV

tnerruCtiucriC-trohStuptuO53±

07±

06±

001±

tnerruCegakaeLtuptuO52±µAV

CC

V0=

V

Am

TUO

V

=V51±

TUO

CC

V

TUO

C°52+=

V,V0=-V=+V=

TUO

,V5.5otV0.3roV0=

STUPNIREVIECER

egnaRegatloVtupnI51-51V WOLdlohserhTtupnI6.02.1VV WOLdlohserhTtupnI8.05.1VV

HGIHdlohserhTtupnI5.14.2VV HGIHdlohserhTtupnI8.14.2VV

V3.3=

CC

V0.5=

CC

V3.3=

CC

V0.5=

CC

siseretsyHtupnI3.0V

ecnatsiseRtupnI357kΩ

enilnO-otuA

WOLegatloVtuptuOSUTATS4.0VI

HGIHegatloVtuptuOSUTATSV

CC

6.0-VI

V=NWODTUHS,DNG=ENILNO(SCITSIRETCARAHCYRTIUCRIC

)

CC

Am6.1=

TUO

Am0.1-=

V2±=

delbasidsrevirD,V21±=

)

t(delbanE

ENILNO

evitageNroevitisoPrevieceR

srevirDotdlohserhTrevieceR

002µS51erugiF

5.0 µS51erugiF

HGIHSUTATSotdlohserhT

t(

)

HSTS

evitageNroevitisoPrevieceR

02 µS51erugiF

WOLSUTATSotdlohserhT

t(

)

LSTS

3

SPECIFICATIONS (continued)

Unless otherwise noted, the following specifications apply for VCC = +3.0V to +5.5V with T Typical values apply at VCC = +3.3V or +5.0V and T

RETEMARAP.NIM.PYT.XAMSTINUSNOITIDNOC

SCITSIRETCARAHCGNIMIT

AMB

= 25°C.

AMB

= T

MIN

to T

MAX

.

etaRataDmumixaM021532spbkR

L

K3=ΩC,

L

evitcarevirdeno,Fp0001=

yaleDnoitagaporPrevieceR

t

LHP

t

HLP

3.0

µsC,tuptuorevieceRottupnirevieceR

L

emiTelbanEtuptuOrevieceR002snnoitarepolamroN

emiTelbasiDtuptuOrevieceR002snnoitarepolamroN

t-

T,|

wekSrevirD001005snt|

wekSrevieceR0020001snt|

etaRwelSnoigeR-noitisnarT03/VµsV

LHP

CC

HLP

t-

|

HLP

52=oC

BMA

R,V3.3=

L

K3=ΩT,

BMA

52=o,C

V0.3-otV0.3+

TYPICAL PERFORMANCE CHARACTERISTICS

Unless otherwise noted, the following performance characteristics apply for VCC = +3.3V, 235Kbps data rate, all drivers loaded with 3KΩ, 0.1µF charge pump capacitors, and T

6

4

1500

Vout+ Vout-

Transmitter Output Voltage [V]

2

0

-2

-4

-6

500

1000

Load Capacitance [pF]

Figure 1. Transmitter Output Voltage VS. Load Capacitance for the SP3223E

= +25°C.

AMB

14

12

10

8

6

Slew Rate [V/µs]

4

2

0

0 500

1000

Load Capacitance [pF]

1500

+Slew

-Slew

Figure 2. Slew Rate VS. Load Capacitance for the SP3223E

Fp051=

roV0.3+otV0.3-morfnekatstnemerusaem

2000

4

TYPICAL PERFORMANCE CHARACTERISTICS (continued)

Unless otherwise noted, the following performance characteristics apply for VCC = +3.3V, 235Kbps data rate, all drivers loaded with 3KΩ, 0.1µF charge pump capacitors, and T

40

35

118KHz 60KHz 10KHz

30

25

20

15

Supply Current [mA]

10

5

0

0 500

1000

Load Capacitance [pF]

1500

Figure 3. Supply Current VS. Load Capacitance when Transmitting Data for the SP3223E

2000

= +25°C.

AMB

6

4

2

0

500

1000

1500

2000

2500

-2

-4

Transmitter Output Voltage [V]

-6 Load Capacitance [pF]

Figure 4. Transmitter Output Voltage VS. Load Capacitance for the SP3243E

Vout+ Vout-

16

14

12

10

8

Slew Rate [V/µs]

6

4

2

0

0 500

1000

2000

1500

Load Capacitance [pF]

2500

+ Slew

- Slew

Figure 5. Slew Rate VS. Load Capacitance for the SP3243E

3000

80

118KHz 60KHz

70

10KHz

60

50

40

30

20

Supply Current [mA]

10

0

0 500

1000

1500

Load Capacitance [pF]

2000

2500

Figure 6. Supply Current VS. Load Capacitance when Transmitting Data for the SP3243E

3000

5

EMANNOITCNUF

REBMUNNIP

E3223PSE3423PS

NE

.)etatsZ-hgih(stuptuoreviecerehtelbasidot

HGIHcigolylppA.noitarepolamronrofWOLcigolylppA.elbanErevieceR

1-

+1C .roticapacpmup-egrahcrelbuodegatlovehtfolanimretevitisoP 282

+V.pmupegrahcehtybdetarenegtuptuoV5.5+detalugeR 372

-1C .roticapacpmup-egrahcrelbuodegatlovehtfolanimretevitageN 442

+2C.roticapacpmup-egrahcgnitrevniehtfolanimretevitisoP 51

-2C.roticapacpmup-egrahcgnitrevniehtfolanimretevitageN 62

-V.pmupegrahcehtybdetarenegtuptuoV5.5-detalugeR 73 NI.tupnireviecer232-SR 614

R

1

NI.tupnireviecer232-SR 95

R

2

R

NI.tupnireviecer232-SR -6

3

NI.tupnireviecer232-SR -7

R

4

R

NI.tupnireviecer232-SR -8

5

R

TUO.tuptuoreviecerSOMC/LTT 5191

1

TUO.tuptuoreviecerSOMC/LTT 0181

R

2

R

TUO.nwodtuhsnievitca,tuptuo2-reviecergnitrevni-noN -02

2

TUO.tuptuoreviecerSOMC/LTT -71

R

3

R

TUO.tuptuoreviecerSOMC/LTT -61

4

R

TUO.tuptuoreviecerSOMC/LTT -51

5

SUTATS.sutatsnwodtuhsdnaenilnognitacidnituptuOSOMC/LTT 1112

NI.tupnirevirdSOMC/LTT 3141

T

1

NI.tupnirevirdSOMC/LTT 2131

T

2

T

NI.tupnirevirdSOMC/LTT -21

3

ENILNO

TUO.tuptuorevird232-SR 719

T

1

TUO.tuptuorevird232-SR 801

T

2

T

TUO.tuptuorevird232-SR -11

3

edirrevootHGIHcigolylppA

enilnO-otuA

.)2elbaTotrefer,HGIHcigoleboslatsumNWODTUHS(

evitcasrevirdgnipeekyrtiucric

4132

DNG.dnuorG 8152

V

CC

NWODTUHS

enilnO-otuA

.egatlovylppusV5.5+otV0.3+ 9162

llasedirrevosihT.pmupegrahcdnasrevirdnwodtuhsotWOLcigolylppA

.)2elbaTotrefer(ENILNOdnayrtiucric

0222

Table 1. Device Pin Description

6

EN

C1+

V+

C1-

C2+

C2-

V-

1

2

3

4

5

6

7

SP3223E

20

SHUTDOWN

V

CC

19

GND

18

T1OUT

17

16

R

1

15

R

1

14

ONLINE

IN

OUT

T

2

R

OUT

R

2

Figure 7. SP3223E Pinout Configuration

R

R4IN

R

T

OUT

1

OUT

T

2

OUT

T

3

T

T2IN

T

IN

2

C2+

C2-

V-

IN

1

IN

2

IN

3

IN

5

IN

3

IN

1

8

9

10

1

2

3

4

5

6

7

8

9

10

11

12

13

14

SP3243E

13

T

1

12

IN

T

2

STATUS

11

28

C1+

V+

27

CC

V

26

25

GND

24

C1-

23

ONLINE

22

SHUTDOWN

21

STATUS

R

20

2

R

19

1

18

R

2

17

R

3

16

R

4

15

R

5

IN

OUT

Figure 8. SP3243E Pinout Configuration

7

+3V to +5V

+

C5

+

C1

+

C2

TTL/CMOS

INPUTS

TTL/CMOS

OUTPUTS

0.1µF

13

12

15

10

2

4 5

6

C1+

C1C2+

C2-

IN

T

1

T

IN

2

OUT

R

1

OUT

R

2

19

V

CC

SP3223E

5KΩ

T

OUT

1

OUT

2

R

1

R

2

V+

V-

IN

3

7

17

8

16

9

+

C3

C4

0.1µF

+

RS-232 OUTPUTS

RS-232 INPUTS

5KΩ

1

V

CC

EN

20

SHUTDOWN

14

ONLINE

To µP Supervisor

Circuit

11

STATUS

GND

18

Figure 9. SP3223E Typical Operating Circuit

8

C5

C1

+

0.1µF

+

0.1µF

28

24

C1+

C1-

V

CC

26

V

CC

27

V+

C3

+

0.1µF

C2

TTL/CMOS

INPUTS

TTL/CMOS

OUTPUTS

+

0.1µF

14

13

1

2

C2+

C2-

T1IN T2IN

SP3243E

T

OUT

1

OUT

2

V-

3

9

10

C4

RS-232

0.1µF

+

OUTPUTS

T

12

20

19

IN

T

3

R2OUT R

OUT

1

OUT

3

R1IN

11

4

5KΩ

IN

18

R

OUT

2

R

5

2

5KΩ

IN

17

16

R

OUT

3

OUT

4

5KΩ

R

6

3

RS-232 INPUTS

IN

R

4

7

5KΩ

R

OUT

5

15

V

CC

22

SHUTDOWN

23

ONLINE

5KΩ

IN

R

5

8

To µP Supervisor

Circuit

21

STATUS

GND

25

Figure 10. SP3243E Typical Operating Circuit

9

DESCRIPTION

The SP3223E and SP3243E transceivers meet the EIA/TIA-232 and ITU-T V.28/V.24 communication protocols and can be implemented in battery-powered, portable, or hand-held applications such as notebook or palmtop computers. The SP3223E and SP3243E devices feature Sipex's proprietary and patented (U.S.-5,306,954) on-board charge pump circuitry that generates ±5.5V RS-232 voltage levels from a single +3.0V to +5.5V power supply. The SP3223E and SP3243E devices can operate at a typical data rate of 235kbps fully loaded.

The SP3223E is a 2-driver/2-receiver device, and the SP3243E is a 3-driver/5-receiver device ideal for portable or hand-held applications. The SP3243E includes one complementary always-active receiver that can monitor an external device (such as a modem) in shutdown. This aids in protecting the UART or serial controller IC by preventing forward biasing of the protection diodes where VCC may be disconnected.

V

28

C1+

24

C1-

1

C2+

2

C2-

14

13

12

20

R

19

18

17

16

15

22

23

21

T1IN T2IN T

IN

3

R2OUT

OUT

1

OUT

R

2

R

OUT

3

R

OUT

4

R

OUT

5

SHUTDOWN ONLINE

STATUS

CC

26

V

CC

SP3243E

GND

25

27

V+

+

0.1µF

C3

3

V-

0.1µF

C4

+

OUT

T

9

1

OUT

T

10

2

RS-232 OUTPUTS

T

OUT

11

3

R1IN

4

5KΩ

R

IN

5

2

5KΩ

R

IN

6

3

RS-232

5KΩ

INPUTS

R

IN

4

7

R

IN

5

8

+

0.1µF

C5

+

0.1µF

C1

+

C2

0.1µF

TxD

RTS

DTR

RESET

UART

or

Serial µC

µP

Supervisor

IC

RxD

CTS

DSR

DCD

RI

V

CC

V

IN

Figure 11. Interface Circuitry Controlled by Microprocessor Supervisory Circuit

The SP3223E and SP3243E series is an ideal choice for power sensitive designs. The SP3223E and SP3243E devices feature Auto-Online circuitry which reduces the power supply drain to a 1µA supply current. In many portable or hand-held applications, an RS-232 cable can be disconnected or a connected peripheral can be turned off. Under these conditions, the internal charge pump and the drivers will be shut down. Otherwise, the system automatically comes online. This feature allows design engineers to address power saving concerns without major design changes.

THEORY OF OPERATION

The SP3223E and SP3243E series is made up of four basic circuit blocks: 1. Drivers,

2. Receivers, 3. the Sipex proprietary charge pump, and 4. Auto-Online circuitry.

Drivers

The drivers are inverting level transmitters that convert TTL or CMOS logic levels to 5.0V EIA/ TIA-232 levels with an inverted sense relative to the input logic levels. Typically, the RS-232 output voltage swing is +5.4V with no load and +5V minimum fully loaded. The driver outputs are protected against infinite short-circuits to ground without degradation in reliability. These drivers comply with the EIA-TIA-232F and all previous RS-232 versions.

The drivers typically can operate at a data rate of 235Kbps. The drivers can guarantee a data rate of 120Kbps fully loaded with 3KΩ in parallel with 1000pF, ensuring compatibility with PC-to-PC communication software.

The slew rate of the driver output is internally limited to a maximum of 30V/µs in order to meet the EIA standards (EIA RS-232D 2.1.7, Paragraph 5). The transition of the loaded output from HIGH to LOW also meets the monotonicity requirements of the standard.

10

E3223PS:ECIVED

NWODTUHSNET

TUOR

X

TUO

00 ZhgiHevitcA

01 ZhgiHZhgiH

10 evitcAevitcA

C5

C1

C2

TTL/CMOS

INPUTS

+3V to +5V

+

0.1µF

+

0.1µF

+

0.1µF

19

CC

V

2

C1+

4

C1-

5

SP3223E

C2+

SP3243E

6

C2-

IN

T

1

IN

T

X

3

V+

+

0.1µF

C3

7

V-

OUT

T

1

T

OUT

X

0.1µF

C4

+

11 evitcAZhgiH

E3423PS:ECIVED

NWODTUHST

TUOR

X

TUOR2TUO

X

0ZhgiHZhgiHevitcA

1evitcAevitcAevitcA

Table 2. SHUTDOWN and EN Truth Tables Note: In Auto-Online Mode where ONLINE = GND and SHUTDOWN = VCC, the device will shut down if there is no activity present at the Receiver inputs.

The SP3223E and SP3243E drivers can maintain high data rates up to 240Kbps fully loaded. Figure 12 shows a loopback test circuit used to test the RS-232 Drivers. Figure 13 shows the test results of the loopback circuit with all three drivers active at 120Kbps with typical RS-232 loads in parallel with 1000pF capacitors. Figure 14 shows the test results where one driver was active at 235Kbps and all three drivers loaded

IN

GND

R

1

5KΩ

IN

R

X

5KΩ

18

1000pF

TTL/CMOS

OUTPUTS

V

CC

To µP Supervisor Circuit

R

1

R

1

EN

20

SHUTDOWN

14

ONLINE

11

STATUS

OUT

X

Figure 12. Loopback Test Circuit for RS-232 Driver Data Transmission Rates

with an RS-232 receiver in parallel with a 1000pF capacitor. A solid RS-232 data transmission rate of 120Kbps provides compatibility with many designs in personal computer peripherals and LAN applications.

Receivers

The receivers convert ±5.0V EIA/TIA-232 levels to TTL or CMOS logic output levels. All receivers have an inverting output that can be disabled by using the EN pin.

[]

T1 IN

1

2

T1 OUT

3

R1 OUT

5.00V

Ch1

Ch3

5.00V

Figure 13. Loopback Test Circuit Result at 120Kbps (All Drivers Fully Loaded)

Ch2

5.00V M 5.00µs

T

Ch1

0V

T1 IN

T1 OUT

R1 OUT

1

2

3

[]

5.00V

Ch1

Ch3

5.00V

Ch2

5.00V M 2.50µs

T

Ch1

0V

Figure 14. Loopback Test Circuit result at 235Kbps (All Drivers Fully Loaded)

11

Receivers are active when the Auto-Online circuitry is enabled or when in shutdown. During the shutdown, the receivers will continue to be active. If there is no activity present at the receivers for a period longer than 100µs or when SHUTDOWN is enabled, the device goes into a standby mode where the circuit draws 1µA. Driving EN to a logic HIGH forces the outputs of the receivers into high-impedance. The truth table logic of the SP3223E and SP3243E driver and receiver outputs can be found in Table 2.

The SP3243E includes an additional non-invert- ing receiver with an output R2OUT. R2OUT is an extra output that remains active and monitors activity while the other receiver outputs are forced into high impedance. This allows Ring Indicator (RI) from a peripheral to be monitored without forward biasing the TTL/CMOS inputs of the other devices connected to the receiver outputs.

Since receiver input is usually from a transmission line where long cable lengths and system interference can degrade the signal, the inputs have a typical hysteresis margin of 300mV. This ensures that the receiver is virtually immune to noisy transmission lines. Should an input be left unconnected, an internal 5KΩ pulldown resistor to ground will commit the output of the receiver to a HIGH state.

Charge Pump

The charge pump is a Sipex–patented design (U.S. 5,306,954) and uses a unique approach compared to older less–efficient designs. The charge pump still requires four external capacitors, but uses a four–phase voltage shifting technique to attain symmetrical 5.5V power supplies. The internal power supply consists of a regulated dual charge pump that provides output voltages 5.5V regardless of the input voltage (VCC) over the +3.0V to +5.5V range. This is important to maintain compliant RS-232 levels regardless of power supply fluctuations.

The charge pump operates in a discontinuous mode using an internal oscillator. If the output voltages are less than a magnitude of 5.5V, the charge pump is enabled. If the output voltages exceed a magnitude of 5.5V, the charge pump is disabled. This oscillator controls the four phases of the voltage shifting. A description of each phase follows.

Phase 1

— VSS charge storage — During this phase of the clock cycle, the positive side of capacitors C1 and C2 are initially charged to VCC. C then switched to GND and the charge in C transferred to C VCC, the voltage potential across capacitor C2 is

–

. Since C

2

+

is connected to

2

+

is

l

–

is

1

now 2 times VCC.

Phase 2

— VSS transfer — Phase two of the clock connects the negative terminal of C2 to the V storage capacitor and the positive terminal of C

SS

to GND. This transfers a negative generated voltage to C3. This generated voltage is regulated to a minimum voltage of -5.5V. Simultaneous with the transfer of the voltage to C3, the positive side of capacitor C1 is switched to VCC and the negative side is connected to GND.

Phase 3

— VDD charge storage — The third phase of the clock is identical to the first phase — the charge transferred in C1 produces –VCC in the negative terminal of C1, which is applied to the negative side of capacitor C2. Since C voltage potential across C2 is 2 times VCC.

+

is at VCC, the

2

Phase 4

— VDD transfer — The fourth phase of the clock connects the negative terminal of C2 to GND, and transfers this positive generated voltage across C2 to C4, the VDD storage capacitor. This voltage is regulated to +5.5V. At this voltage, the internal oscillator is disabled. Simultaneous with the transfer of the voltage to C4, the positive side of capacitor C1 is switched to V and the negative side is connected to GND,

CC

allowing the charge pump cycle to begin again. The charge pump cycle will continue as long as the operational conditions for the internal oscillator are present.

2

12

Since both V+ and V– are separately generated from VCC, in a no–load condition V+ and V– will be symmetrical. Older charge pump approaches that generate V– from V+ will show a decrease in the magnitude of V– compared to V+ due to the inherent inefficiencies in the design.

RECEIVER

RS-232 INPUT

VOLTAGES

STATUS

+2.7V

0V

-2.7V

V

CC

0V

t

STSL

The clock rate for the charge pump typically operates at 250kHz. The external capacitors can be as low as 0.1µF with a 16V breakdown voltage rating.

S H U

T

D O W N

t

STSH

t

ONLINE

DRIVER

RS-232 OUTPUT

VOLTAGES

+5V

0V

-5V

Figure 15. Auto-Online Timing Waveforms

13

V

= +5V

CC

Figure 16. Charge Pump — Phase 1

C

Figure 17. Charge Pump — Phase 2

a) C

1

2

+5V

++

C

1

–5V –5V

C

2

––

C

4

+

–

C

VCC = +5V

++

1

C

2

––

–10V

T[]

2+

T

–

Storage Capacitor

V

DD

+

V

Storage Capacitor

SS

3

C

4

+

–

Storage Capacitor

V

DD

+

–

V

Storage Capacitor

SS

C

3

+6V

0V 0V

b) C2-

T

Ch1 2.00V Ch2 2.00V M 1.00µs Ch1 1.96V

-6V

Figure 18. Charge Pump Waveforms

VCC = +5V

+5V

++

C

1

–5V

C

2

––

–5V

C

4

+

–

Storage Capacitor

V

DD

+

–

V

Storage Capacitor

SS

C

3

Figure 19. Charge Pump — Phase 3

VCC = +5V

+10V

++

C

1

C

2

––

C

4

+

–

Storage Capacitor

V

DD

+

–

V

Storage Capacitor

SS

C

3

Figure 20. Charge Pump — Phase 4

14

6

4

1.82

2.67

Vout+ Vout-

3.46

4.93

Transmitter Output Voltage [V]

2

0

0.62

-2

-4

-6

1.02

1.12

1.23

0.869

0.939

Load Current Per Transmitter [mA]

1.38

1.57

Figure 21. SP3243E Driver Output Voltages vs. Load Current per Transmitter

+

0.1µF

C5

28

0.1µF

V

CC

C1+

24

C1-

1

C2+

2

C2-

T1IN

14

T2IN

13

T

12

3

R2OUT

20

R

19

1

R

18

2

R

3

17

R

4

16

R

15

22

SHUTDOWN

23

ONLINE

21

STATUS

IN

OUT

5

+

C1

+

C2

To µP Supervisor

Circuit

DB-9 Connector Pins:

1. Received Line Signal Detector

2. Received Data

3. Transmitted Data

4. Data Terminal Ready

5. Signal Ground (Common)

SP3243E

OUT

26

CC

V

GND

5KΩ

25

8.6

V

CC

27

V+

C3

3

V-

C4

OUT

T

9

1

T

OUT

10

2

T

OUT

11

3

R1IN

4

R

IN

5

2

R

IN

6

3

R

IN

4

7

IN

R

5

8

6. DCE Ready

7. Request to Send

8. Clear to Send

9. Ring Indicator

+

0.1µF

DB-9

Connector

6 7 8 9

1 2 3 4 5

Figure 22. Circuit for the connectivity of the SP3243E with a DB-9 connector

15

LANGIS232-SR

REVIECERTA

TUPNI

NWODTUHS

TUPNI

TUPNIENILNOTUPTUOSUTATS

REVIECSNART

SUTATS

SEYHGIH-HGIH

ONHGIHHGIHWOL

ONHGIHWOLWOL

SEYWOL-HGIH

ONWOL-WOL

Table 3. Auto-Online Logic

RXIN

Inactive Detection Block

RS-232

Receiver Block

RXINACT

RXOUT

noitarepOlamroN

nwodtuhS

(

enilnO-otuA

)

nwodtuhS

Figure 23. Stage I of Auto-Online Circuitry

Delay

Stage

R1INACT

Delay

Stage

R2INACT

Delay

Stage

R3INACT

Delay

Stage

R4INACT

Delay Stage

R5INACT

STATUS

SHUTDOWN

Figure 24. Stage II of Auto-Online Circuitry

16

Auto-Online Circuitry

The SP3223E and SP3243E devices have a patent pending Auto-Online circuitry on board that saves power in applications such as laptop computers, palmtop (PDA) computers, and other portable systems.

The SP3223E and SP3243E devices incorporate an Auto-Online circuit that automatically enables itself when the external transmitters are enabled and the cable is connected. Conversely, the Auto-Online circuit also disables most of the internal circuitry when the device is not being used and goes into a standby mode where the device typically draws 1µA. This function can also be externally controlled by the ONLINE pin. When this pin is tied to a logic LOW, the Auto-Online function is active. Once active, the device is enabled until there is no activity on the receiver inputs. The receiver input typically sees at least ±3V, which are generated from the transmitters at the other end of the cable with a ±5V minimum. When the external transmitters are disabled or the cable is disconnected, the receiver inputs will be pulled down by their internal 5kΩ resistors to ground. When this occurs over a period of time, the internal transmitters will be disabled and the device goes into a shutdown or standy mode. When ONLINE is HIGH, the Auto-Online mode is disabled.

The Auto-Online circuit has two stages:

1) Inactive Detection

2) Accumulated Delay

The first stage, shown in Figure 23, detects an inactive input. A logic HIGH is asserted on RXINACT if the cable is disconnected or the external transmitters are disabled. Otherwise, RXINACT will be at a logic LOW. This circuit is duplicated for each of the other receivers.

The second stage of the Auto-Online circuitry, shown in Figure 24, processes all the receiver's RXINACT signals with an accumulated delay that disables the device to a 1µA supply current. The STATUS pin goes to a logic LOW when the cable is disconnected, the external transmitters are disabled, or the SHUTDOWN pin is invoked. The typical accumulated delay is around 20µs.

When the SP3223E and SP3243E drivers or internal charge pump are disabled, the supply current is reduced to 1µA. This can commonly occur in hand-held or portable applications where the RS-232 cable is disconnected or the RS-232 drivers of the connected peripheral are turned off.

The Auto-Online mode can be disabled by the SHUTDOWN pin. If this pin is a logic LOW, the Auto-Online function will not operate regardless of the logic state of the ONLINE pin. Table 3 summarizes the logic of the Auto-Online operating modes. The truth table logic of the SP3223E and SP3243E driver and receiver outputs can be found in Table 2.

The STATUS pin outputs a logic LOW signal if the device is shutdown. This pin goes to a logic HIGH when the external transmitters are enabled and the cable is connected.

When the SP3223E and SP3243E devices are shut down, the charge pumps are turned off. V+ charge pump output decays to VCC, the V- output decays to GND. The decay time will depend on the size of capacitors used for the charge pump. Once in shutdown, the time required to exit the shut down state and have valid V+ and V- levels is typically 200µs.

For easy programming, the STATUS can be used to indicate DTR or a Ring Indicator signal. Tying ONLINE and SHUTDOWN together will bypass the Auto-Online circuitry so this connection acts like a shutdown input pin.

17

ESD TOLERANCE

The SP3223E/3243E series incorporates ruggedized ESD cells on all driver output and receiver input pins. The ESD structure is improved over our previous family for more rugged applications and environments sensitive to electro-static discharges and associated transients. The improved ESD tolerance is at least +15kV without damage nor latch-up.

There are different methods of ESD testing applied:

a) MIL-STD-883, Method 3015.7 b) IEC1000-4-2 Air-Discharge

c) IEC1000-4-2 Direct Contact

The Human Body Model has been the generally accepted ESD testing method for semiconductors. This method is also specified in MIL-STD-883, Method 3015.7 for ESD testing. The premise of this ESD test is to simulate the human body’s potential to store electro-static energy and discharge it to an integrated circuit. The simulation is performed by using a test model as shown in Figure 25. This method will test the IC’s capability to withstand an ESD transient during normal handling such as in manufacturing areas where the ICs tend to be handled frequently.

The IEC-1000-4-2, formerly IEC801-2, is generally used for testing ESD on equipment and systems. For system manufacturers, they must guarantee a certain amount of ESD protection since the system itself is exposed to the outside environment and human presence. The premise with IEC1000-4-2 is that the system is required to withstand an amount of static electricity when ESD is applied to points and surfaces of the equipment that are accessible to personnel during

normal usage. The transceiver IC receives most of the ESD current when the ESD source is applied to the connector pins. The test circuit for IEC1000-4-2 is shown on Figure 26. There are two methods within IEC1000-4-2, the Air Discharge method and the Contact Discharge method.

With the Air Discharge Method, an ESD voltage is applied to the equipment under test (EUT) through air. This simulates an electrically charged person ready to connect a cable onto the rear of the system only to find an unpleasant zap just before the person touches the back panel. The high energy potential on the person discharges through an arcing path to the rear panel of the system before he or she even touches the system. This energy, whether discharged directly or through air, is predominantly a function of the discharge current rather than the discharge voltage. Variables with an air discharge such as approach speed of the object carrying the ESD potential to the system and humidity will tend to change the discharge current. For example, the rise time of the discharge current varies with the approach speed.

The Contact Discharge Method applies the ESD current directly to the EUT. This method was devised to reduce the unpredictability of the ESD arc. The discharge current rise time is constant since the energy is directly transferred without the air-gap arc. In situations such as hand held systems, the ESD charge can be directly discharged to the equipment from a person already holding the equipment. The current is transferred on to the keypad or the serial port of the equipment directly and then travels through the PCB and finally to the IC.

R

RR

C

CC

SW1

SW1SW1

DC Power Source

Figure 25. ESD Test Circuit for Human Body Model

RR

S

SS

SW2

SW2SW2

C

CC

S

SS

Device Under Test

18

Contact-Discharge Module

Contact-Discharge ModuleContact-Discharge Module

R

RR

C

CC

RR

S

R

RR

V

SS

VV

SW1

SW1SW1

DC Power Source

Figure 26. ESD Test Circuit for IEC1000-4-2

The circuit model in Figures 25 and 26 represent the typical ESD testing circuit used for all three methods. The CS is initially charged with the DC power supply when the first switch (SW1) is on. Now that the capacitor is charged, the second switch (SW2) is on while SW1 switches off. The voltage stored in the capacitor is then applied through RS, the current limiting resistor, onto the device under test (DUT). In ESD tests, the SW2 switch is pulsed so that the device under test receives a duration of voltage.

For the Human Body Model, the current limiting resistor (RS) and the source capacitor (CS) are

1.5kΩ an 100pF, respectively. For IEC-1000-42, the current limiting resistor (RS) and the source capacitor (CS) are 330Ω an 150pF, respectively.

SW2

SW2SW2

C

CC

S

SS

RS and RV add up to 330Ω for IEC1000-4-2.

RR

andand RR

add up to 330add up to 330ΩΩ f for IEC1000-4-2.or IEC1000-4-2.

S S

V V

i ➙

30A

15A

0A

t=0ns t=30ns

Figure 27. ESD Test Waveform for IEC1000-4-2

t ➙

Device Under Test

The higher CS value and lower RS value in the IEC1000-4-2 model are more stringent than the Human Body Model. The larger storage capacitor injects a higher voltage to the test point when SW2 is switched on. The lower current limiting resistor increases the current charge onto the test point.

DEVICE PIN HUMAN BODY IEC1000-4-2 TESTED MODEL Air Discharge Direct Contact Level

Driver Outputs ±15kV ±15kV ±8kV 4 Receiver Inputs ±15kV ±15kV ±8kV 4

Table 4. Transceiver ESD Tolerance Levels

19

D1 = 0.005" min.

(0.127 min.)

D

e = 0.100 BSC

(2.540 BSC)

B1

B

ALTERNATE

END PINS

(BOTH ENDS)

PACKAGE: PLASTIC

DUAL–IN–LINE (NARROW)

E1

E

A1 = 0.015" min.

(0.381min.)

A = 0.210" max.

(5.334 max).

A2

L

C

Ø

eA = 0.300 BSC

(7.620 BSC)

DIMENSIONS (Inches)

Minimum/Maximum

(mm) A2

B

B1

C

D

E

E1

L

Ø

16–PIN

0.115/0.195

(2.921/4.953)

0.014/0.022

(0.356/0.559)

0.045/0.070

(1.143/1.778)

0.008/0.014

(0.203/0.356)

0.780/0.800

(19.812/20.320)

0.300/0.325

(7.620/8.255)

0.240/0.280

(6.096/7.112)

0.115/0.150

(2.921/3.810)

0°/ 15°

(0°/15°)

20–PIN

0.115/0.195

(2.921/4.953)

0.014/0.022

(0.356/0.559)

0.045/0.070

(1.143/1.778)

0.008/0.014

(0.203/0.356)

0.980/1.060

(24.892/26.924)

0.300/0.325

(7.620/8.255)

0.240/0.280

(6.096/7.112)

0.115/0.150

(2.921/3.810)

0°/ 15°

(0°/15°)

28–PIN

0.068/0.078 (1.73/1.99)

0.002/0.008 (0.05/0.21)

0.010/0.015 (0.25/0.38)

0.397/0.407

(10.07/10.33)

0.205/0.212 (5.20/5.38)

0.0256 BSC (0.65 BSC)

0.301/0.311

(7.65/7.90)

0.022/0.037

(0.55/0.95)

0°/8°

(0°/8°)

20

PACKAGE: PLASTIC SHRINK

SMALL OUTLINE (SSOP)

EH

D

A

Ø

Be

A1

L

DIMENSIONS (Inches)

Minimum/Maximum

(mm)

A

A1

B

D

E

e

H

L

Ø

16–PIN

0.068/0.078 (1.73/1.99)

0.002/0.008 (0.05/0.21)

0.010/0.015 (0.25/0.38)

0.239/0.249 (6.07/6.33)

0.205/0.212 (5.20/5.38)

0.0256 BSC (0.65 BSC)

0.301/0.311 (7.65/7.90)

0.022/0.037 (0.55/0.95)

0°/8°

(0°/8°)

20–PIN

0.068/0.078 (1.73/1.99)

0.002/0.008 (0.05/0.21)

0.010/0.015 (0.25/0.38)

0.278/0.289 (7.07/7.33)

0.205/0.212 (5.20/5.38)

0.0256 BSC (0.65 BSC)

0.301/0.311 (7.65/7.90)

0.022/0.037 (0.55/0.95)

0°/8°

(0°/8°)

24–PIN

0.068/0.078 (1.73/1.99)

0.002/0.008 (0.05/0.21)

0.010/0.015 (0.25/0.38)

0.317/0.328 (8.07/8.33)

0.205/0.212 (5.20/5.38)

0.0256 BSC (0.65 BSC)

0.301/0.311 (7.65/7.90)

0.022/0.037 (0.55/0.95)

0°/8°

(0°/8°)

28–PIN

0.068/0.078 (1.73/1.99)

0.002/0.008 (0.05/0.21)

0.010/0.015 (0.25/0.38)

0.397/0.407

(10.07/10.33)

0.205/0.212 (5.20/5.38)

0.0256 BSC

(0.65 BSC)

0.301/0.311 (7.65/7.90)

0.022/0.037 (0.55/0.95)

0°/8°

(0°/8°)

21

PACKAGE: PLASTIC

SMALL OUTLINE (SOIC) (WIDE)

EH

D

A

Ø

Be

A1

L

DIMENSIONS (Inches)

Minimum/Maximum

(mm) A

A1

B

D

E

e

H

L

Ø

28–PIN

0.093/0.104

(2.352/2.649)

0.004/0.012

(0.102/0.300)

0.013/0.020

(0.330/0.508)

0.697/0.713

(17.70/18.09)

0.291/0.299

(7.402/7.600)

0.050 BSC

(1.270 BSC)

0.394/0.419

(10.00/10.64)

0.016/0.050

(0.406/1.270)

0°/8°

(0°/8°)

22

P ACKA GE: PLASTIC THIN SMALL

OUTLINE (TSSOP)

E2

E

D

A

Ø

Be

A1

DIMENSIONS

in inches (mm)

Minimum/Maximum

A

A1

B

D

E

e

E2

L

Ø

20–PIN

- /0.043

(- /1.10)

0.002/0.006 (0.05/0.15)

0.007/0.012 (0.19/0.30)

0.252/0.260 (6.40/6.60)

0.169/0.177 (4.30/4.50)

0.026 BSC

(0.65 BSC)

0.126 BSC

(3.20 BSC)

0.020/0.030 (0.50/0.75)

0°/8°

L

23

ORDERING INFORMATION

Model Temperature Range Package Types

SP3223ECP 0°C to +70°C 20-pin PDIP SP3223ECA 0°C to +70°C 20-pin SSOP SP3223ECY 0ºC to +70ºC 20-pin TSSOP SP3223EEP -40°C to +85°C 20-pin PDIP SP3223EEA -40°C to +85°C 20-pin SSOP SP3223EEY -40°C to +85°C 20-pin TSSOP

SP3243ECT 0°C to +70°C 28-pin Wide SOIC SP3243ECA 0°C to +70°C 28-pin SSOP SP3243EET -40°C to +85°C 28-pin Wide SOIC SP3243EEA -40°C to +85°C 28-pin SSOP

Please consult the factory for pricing and availability on a Tape-On-Reel option.

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○○○○○○○○○○○○○○○

○○○○○○○○○○○○○○

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○○○○○○○○○○○○○○

○○○○○○○○○○○○○

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Corporation

SIGNAL PROCESSING EXCELLENCE

Sipex Corporation Headquarters and

Sales Office

22 Linnell Circle Billerica, MA 01821 TEL: (978) 667-8700 FAX: (978) 670-9001 e-mail: sales@sipex.com

Sales Office

233 South Hillview Drive Milpitas, CA 95035 TEL: (408) 934-7500 FAX: (408) 935-7600

Sipex Corporation reserves the right to make changes to any products described herein. Sipex does not assume any liability arising out of the application or use of any product or circuit described hereing; neither does it convey any license under its patent rights nor the rights of others.

24

Datasheet SP3243ECA, SP3243ECT, SP3243EEA, SP3243EET, SP3223ECA Datasheet (Sipex Corporation)

Specifications and Main Features

Frequently Asked Questions

User Manual