Datasheet SP3232EHCA, SP3232EHCP, SP3232EHCT, SP3232EHCY, SP3222EHCA Datasheet (Sipex Corporation)

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Page 1

SP3222EH/3232EH

3.3V, 460 Kbps RS-232 Transceivers

■ Meets true EIA/TIA-232-F Standards from a +3.0V to +5.5V power supply

■ Interoperable with RS-232 down to +2.7V power source

■ 1µA Low-Power Shutdown with Receivers Active (SP3222EH)

■ Enhanced ESD Specifications:

+15kV Human Body Model +15kV IEC1000-4-2 Air Discharge +8kV IEC1000-4-2 Contact Discharge

■ 460Kbps Minimum Transmission Rate

■ Ideal for Handheld, Battery Operated

Applications

DESCRIPTION

The SP3222EH and the 3232EH are 2 driver/2 receiver RS-232 transceiver solutions intended for portable or hand-held applications such as notebook or palmtop computers. Their data transmission rate of 460Kbps meeting the demands of high speed RS-232 applications. Both ICS have a high-efficiency, charge-pump power supply that requires only

0.1µF capacitors for 3.3V operation. The charge pump allows the SP3222EH and the 3232EH series to deliver true RS-232 performance from a single power supply ranging from +3.3V to +5.0V. The ESD tolerance of the SP3222EH/3232EH devices exceeds +15kV for both Human Body Model and IEC1000-4-2 Air discharge test methods.

The SP3222EH device has a low-power shutdown mode where the devices' driver outputs and charge pumps are disabled. During shutdown, the supply current is less than 1µA.

SELECTION TABLE

LEDOMseilppuSrewoP

HE2223PS HE2323PS

V5.5+otV0.3+224seYseY02,81 V5.5+otV0.3+224oNoN61

232-SR srevirD

232-SR

srevieceR

lanretxE

stnenopmoC

nwodtuhS

LTT

etatS-3

sniP

fo.oN

Page 2

ABSOLUTE MAXIMUM RATINGS

These are stress ratings only and functional operation of the device at these ratings or any other above those indicated in the operation sections of the specifications below is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability and cause permanent damage to the device.

VCC................................................................-0.3V to +6.0V

V+ (NOTE 1)................................................-0.3V to +7.0V

V- (NOTE 1)................................................+0.3V to -7.0V

V+ + |V-| (NOTE 1)...................................................+13V

ICC (DC VCC or GND current).................................+100mA

Electrostatic Discharge

HBM ......................................................................15kV

IEC1000-4-2-AirDischarge....................................15kV

IEC1000-4-2 Direct Contact....................................8kV

Input Voltages

TxIN, EN .....................................................-0.3V to +6.0V

RxIN.............................................................................±25V

Output Voltages

TxOUT.....................................................................±13.2V

RxOUT..............................................-0.3V to (VCC + 0.3V)

Short-Circuit Duration

TxOUT...............................................................Continuous

Storage Temperature.................................-65°C to +150°C

Power Dissipation Per Package

20-pin SSOP (derate 9.25mW/oC above +70oC).......750mW

18-pin PDIP (derate 15.2mW/oC above +70oC)......1220mW

18-pin SOIC (derate 15.7mW/oC above +70oC)......1260mW

20-pin TSSOP (derate 11.1mW/oC above +70oC).....890mW

16-pin SSOP (derate 9.69mW/oC above +70oC).......775mW

16-pin PDIP (derate 14.3mW/oC above +70oC)......1150mW

16-pin Wide SOIC (derate 11.2mW/oC above +70oC)....900mW

16-pin TSSOP (derate 10.5mW/oC above +70oC).....850mW

NOTE 1: V+ and V- can have maximum magnitudes of 7V, but their absolute difference cannot exceed 13V.

SPECIFICATIONS

Unless otherwise noted, the following specifications apply for VCC = +3.0V to +5.0V with T

RETEMARAP.NIM.PYT.XAMSTINUSNOITIDNOC

SCITSIRETCARAHCCD

tnerruCylppuS3.00.1AmT,daolon

tnerruCylppuSnwodtuhS0.101

µA

STUPTUOREVIECERDNASTUPNICIGOL

= T

AMB

BMA

,DNG=NDHST

to T

MIN

52+=

V,C

52+=

BMA

MAX

V3.3+=

V,C

V3.3+=

WOLdlohserhTcigoLtupnI8.0V 2etoN,NDHS,NE,NIxT

HGIHdlohserhTcigoLtupnI0.2

4.2

tnerruCegakaeLtupnI10.0±0.1±

tnerruCegakaeLtuptuO50.0±01±

WOLegatloVtuptuO4.0VI

HGIHegatloVtuptuOV

6.0-VCC1.0-VI

µA µA

TUO

2etoN,V3.3= 2etoN,V0.5=

,NDHS,NE,NIxTT

BMA

delbasidsreviecer

Am6.1=

Am0.1-=

52+=

STUPTUOREVIRD

gniwSegatloVtuptuO+

ecnatsiseRtuptuO003

tnerruCegakaeLtuptuO+

0.5+4.5Vk3Ω ,stuptuorevirdllatadnuorgotdaol T

Ω

tnerruCtiucriC-trohStuptuO+

53 07

001

µA

52+=

BMA

V0=

TUO

=+ V51

TUO

=+ V,V21

TUO

T,V0=-V=+V=

=+ V2

TUO

delbasidsrevird,V5.5otV0=

Page 3

SPECIFICATIONS (continued)

Unless otherwise noted, the following specifications apply for VCC = +3.0V to +5.0V with T Typical values apply at VCC = +3.3V or +5.0V and T

RETEMARAP.NIM.PYT.XAMSTINUSNOITIDNOC

STUPNIREVIECER

egnaRegatloVtupnI51-51+V

AMB

= 25oC.

AMB

= T

MIN

to T

MAX

WOLdlohserhTtupnI6.0

HGIHdlohserhTtupnI5.1

2.1

8.0

5.1

8.1

4.2

V3.3= V0.5=

siseretsyHtupnI3.0V

ecnatsiseRtupnI357kΩ

SCITSIRETCARAHCGNIMIT

etaRataDmumixaM064spbKR

yaleDnoitagaporPrevirD0.1

0.1

yaleDnoitagaporPrevieceR3.0

µs µs

µst

3.0

k3=ΩC,

t t

HLP

K3=ΩC,

LHP

K3=ΩC,

LHP

emiTelbanEtuptuOrevieceR002sn

emiTelbasiDtuptuOrevieceR002sn

wekSrevirD001005snt|

wekSrevieceR0020001snt|

etaRwelSnoigeR-noitisnarT06/VµsV

LHP

HLP

R,V3.3=

V0.3-otV0.3+ro

L L

Fp0001= Fp0001=

C,TUOxRotNIxR, C,TUOxRotNIxR,

K3=ΩT,

L L

BMA

Fp051= Fp051=

52=o,C

gnihctiwsrevirdeno,Fp0001=

V0.3+otV0.3-morfnekatstnemerusaem

Page 4

TYPICAL PERFORMANCE CHARACTERISTICS

Unless otherwise noted, the following performance characteristics apply for VCC = +3.3V, 1Mbps data rates, all drivers loaded with 3kΩ, 0.1µF charge pump capacitors, and T

= +25°C.

AMB

2000

Vout+ Vout-

Transmitter Output Voltage [V]

-2

-4

-6

500

1000

Load Capacitance [pF]

1500

Figure 1. Transmitter Output Voltage VS. Load Capacitance for the SP3222EH and the SP3232EH

0 500

118KHz 60KHz 10KHz

1000

Load Capacitance [pF]

1500

2000

Supply Current [mA]

2330

Slew Rate [V/µs]

0 500

1000

Load Capacitance [pF]

1500

2000

+Slew

-Slew

Figure 2. Slew Rate VS. Load Capacitance for the SP3222EH and the SP3232EH

2330

Figure 3. Supply Current VS. Load Capacitance when Transmitting Data for the SP3222EH and the SP3232EH

Page 5

REBMUNNIP

EMANNOITCNUF

.noitarepolamronrofWOLcigolylppA.elbanErevieceR

.)etatsZ-hgih(stuptuoreviecerehtelbasidotHGIHcigoLylppA

11 -

HE2223PS

OS/PID

-/POSS

POSST

HE2323PS

+1C.roticapacpmup-egrahcrelbuodegatlovehtfolanimretevitisoP221

+V.pmupegrahcehtybdetarenegV5.5+ 33 2

-1C.roticapacpmup-egrahcrelbuodegatlovehtfolanimretevitageN443

+2C.roticapacpmup-egrahcgnitrevniehtfolanimretevitisoP554

-2C.roticapacpmup-egrahcgnitrevniehtfolanimretevitageN665

-V.pmupegrahcehtybdetarenegV5.5- 77 6 TUO1T.tuptuorevird232-SR 517141 TUO2T.tuptuorevird232-SR887

NI1R.tupnireviecer232-SR 416131 NI2R.tupnireviecer232-SR998

TUO1R.tuptuoreviecerSOMC/LTT 315121

TUO2R.tuptuoreviecerSOMC/LTT 01019 NI1T.tupnirevirdSOMC/LTT 213111 NI2T.tupnirevirdSOMC/LTT 112101 DNG.dnuorG 618151

egatlovylppusV5.5+otV0.3+ 719161

.noitarepoecivedlamronrofHGIHevirD.tupnIlortnoCnwodtuhS

NDHS

ehtdna)tuptuoZ-hgih(srevirdehtnwodtuhsotWOLevirD

8102-

.ylppusrewopdraob-no

CN.tcennoCoN -41,11-

Table 1. Device Pin Description

Page 6

1 2

C1+

V+

C1-

SP3222EH

C2+

C2-

V-

T2OUT

R2IN

R2OUT

Figure 4. Pinout Configurations for the SP3222EH

8 9

SSOP/TSSOP

20 19 18 17

15 14 13

12 11

SHDN

V GND T1OUT R1IN R1OUT

NC T1IN

T2IN NC

C1+

V+

C1-

C2+

C2-

V-

T2OUT

R2IN

1 2 3 4

SP3222EH

5 6 7

DIP/SO

18 17 16 15

SHDN

GND T1OUT

R1IN R1OUT

T1IN

T2IN R2OUT

16 15 14 13

GND T1OUT

R1IN R1OUT

T1IN

T2IN

R2OUT

V+

C1-

C2-

V-

1 2 3

SP3232EH

4 5 6

7 8

C1+

C2+

T2OUT

R2IN

Figure 5. Pinout Configuration for the SP3232EH

Page 7

LOGIC

INPUTS

0.1µF

C1+

C1-

C2+

C2-

T1IN T2IN

SP3222EH

SSOP

TSSOP

T1OUT

T2OUT

VCC

0.1µF

V+

V-

0.1µF

*C3

0.1µF

RS-232

OUTPUTS

LOGIC

INPUTS

0.1µF

C1+

C1-

C2+

C2-

T1IN

12 11

T2IN

SP3222EH

DIP/SO

T1OUT T2OUT

V+

V-

0.1µF

*C3

0.1µF

RS-232

OUTPUTS

R1IN

R2IN

SHDN

*can be returned to either VCC or GND

LOGIC

OUTPUTS

R1OUT

R2OUT

5kΩ

GND

Figure 6. SP3222EH Typical Operating Circuits

0.1µF

LOGIC

INPUTS

11 10

3 4

C1+

C1-

C2+

C2-

T1IN

T2IN

RS-232 INPUTS

SP3232EH

LOGIC

OUTPUTS

T1OUT T2OUT

V+

R1OUT

R2OUT

*C3

V-

GND

0.1µF

RS-232 OUTPUTS

5kΩ

R1IN

R2IN

SHDN

RS-232 INPUTS

*can be returned to either VCC or GND

R1IN

R2IN

RS-232 INPUTS

LOGIC

OUTPUTS

R1OUT

5kΩ

R2OUT

5kΩ

GND

*can be returned to either VCC or GND

Figure 7. SP3232EH Typical Operating Circuit

Page 8

DESCRIPTION

The SP3222EH and SP3232EH are 2-driver/ 2-receiver devices ideal for portable or hand-held applications. The SP3222EH features a 1µA shutdown mode that reduces power consumption and extends battery life in portable systems. Its receivers remain active in shutdown mode, allowing external devices such as modems to be monitored using only 1µA supply current.

The SP3222EH/3232EH transceivers meet the EIA/TIA-232 and V.28/V.24 communication protocols. They feature Sipex's proprietary on-board charge pump circuitry that generates 2 x VCC for RS-232 voltage levels from a single +3.0V to +5.5V power supply. The SP3222EH/ 3232EH drivers operate at a minimum data rate of 460Kbps.

THEORY OF OPERATION

The SP3222EH/3232EH are made up of three basic circuit blocks: 1. Drivers, 2. Receivers, and 3. the Sipex proprietary charge pump.

Drivers

The drivers are inverting level transmitters that convert TTL or CMOS logic levels to +5.0V EIA/TIA-232 levels inverted relative to the input logic levels. Typically, the RS-232 output voltage swing is +5.5V with no load and at least +5V minimum fully loaded. The driver outputs are protected against infinite short-circuits to ground without degradation in reliability. Driver outputs will meet EIA/TIA-562 levels of +3.7V with supply voltages as low as 2.7V.

The drivers have a minimum data rate of 460Kbps fully loaded with 3KΩ in parallel with 1000pF, ensuring compatibility with PC-to-PC communication software.

The slew rate of the driver output is internally limited to a maximum of 30V/µs in order to meet the EIA standards (EIA RS-232D 2.1.7, Paragraph 5). The transition of the loaded output from HIGH to LOW also meets the monotonicity requirements of the standard.

The SP3222EH/3232EH drivers can maintain high data rates up to 240Kbps when fully loaded. Figure 8 shows a loopback circuit used to test the RS-232 drivers. Figure 9 shows the test results of the loopback circuit with all drivers active at 120Kbps and RS-232 loads in parallel with 1000pF capacitors. Figure 10 shows the test results where one driver is active at 235Kbps and all drivers are loaded with an RS-232 receiver in parallel with a 1000pF capacitor.

The SP3222EH driver's output stages are tri-stated in shutdown mode. When the power is off, the SP3222EH device permits the outputs to be driven up to +12V. Because the driver's inputs do not have pull-up resistors, unused inputs should be connected to VCC or GND.

In the shutdown mode, the supply current is less than 1µA, where SHDN = LOW. When the SP3222EH device is shut down, the device's driver outputs are disabled (tri-stated) and the charge pumps are turned off with V+ pulled down to VCC and V- pulled to GND. The time required to exit shutdown is typically 100µs. SHDN is connected to VCC if the shutdown mode is not used. SHDN has no effect on RxOUT or RxOUTB. As they become active, the two driver outputs go to opposite RS-232 levels: one driver input is HIGH and the other LOW. Note that the drivers are enabled only when the magnitude of V- exceeds approximately 3V.

Page 9

LOGIC

INPUTS

0.1µF

C1+

C1C2+

C2TxIN

SP3222EH SP3232EH

V+

V-

TxOUT

0.1µF

LOGIC

OUTPUTS

RxOUT

Figure 8. SP3222EH/3232EH Driver Loopback Test Circuit

Ch2

5.00V M 5.00µs

Ch1

T1 IN

T1 OUT

R1 OUT

[]

5.00V

Ch1

Ch3

5.00V

GND

RxIN

5kΩ

*SHDN

* SP3222 only

T1 IN

T1 OUT

R1 OUT

1000pF

Ch2

5.00V M 2.50µs

Ch1

[]

5.00V

Ch1

Ch3

5.00V

Figure 9. Driver Loopback Test Results at 1Mbps

Figure 10. Driver Loopback Test Results at 1Mbps

Page 10

Receivers

The receivers convert EIA/TIA-232 levels to TTL or CMOS logic output levels. All receivers have an inverting tri-state output. Receiver outputs (RxOUT) are tri-stated when the enable control EN = HIGH. In the shutdown mode, the receivers can be active or inactive. EN has no effect on TxOUT. The truth table logic of the SP3222EH/3232EH driver and receiver outputs can be found in Table 2.

Since receiver input is usually from a transmission line where long cable lengths and system interference can degrade the signal and inject noise, the inputs have a typical hysteresis margin of 300mV. Should an input be left unconnected, a 5kΩ pulldown resistor to ground forces the output of the receiver HIGH.

Charge Pump

The Sipex patented charge pump (5,306,954) uses a four–phase voltage shifting technique to attain symmetrical 5.5V power supplies and requires four external capacitors. The internal power supply consists of a regulated dual charge pump that provides an output voltage of 5.5V regardless of the input voltage (VCC) over the +3.0V to +5.5V range.

In most circumstances, decoupling the power supply can be achieved adequately using a

0.1µF bypass capacitor at C5 (refer to Figures 6 and 7). In applications that are sensitive to power-supply noise,VCC and ground can be decoupled with a capacitor of the same value as charge-pump capacitor C1. It is always important to physically locate bypass capacitors close to the IC.

The charge pump operates in a discontinuous mode using an internal oscillator. If the output voltage is less than 5.5V, the charge pump is enabled. If the output voltage exceeds 5.5V, the charge pump is disabled. An oscillator controls the four phases of the voltage shifting. A description of each phase follows.

Phase 1: VSS Charge Storage (Figure 12)

During this phase of the clock cycle, the positive side of capacitors C1 and C2 are charged to VCC.

is then switched to GND and the charge in

–

is transferred to C

–

. Since C

is connected

to VCC, the voltage potential across capacitor C is now 2 times VCC.

Phase 2: VSS Transfer (Figure 13)

Phase two of the clock connects the negative terminal of C2 to the V

storage capacitor and

the positive terminal of C2 to GND. This transfers a negative generated voltage to C3. This generated voltage is regulated to a minimum voltage of -5.5V. Simultaneous with the transfer of the voltage to C3, the positive side of capacitor C1 is switched to VCC and the negative side is connected to GND.

NDHSNETUOxTTUOxR

00 etats-irTevitcA 01 etats-irTetats-irT

Phase 3: VDD Charge Storage (Figure 15)

The third phase of the clock is identical to the first phase — the charge transferred in C produces –VCC in the negative terminal of C1, which is applied to the negative side of capacitor

10 evitcAevitcA 11 evitcAetats-irT

Table 2. Truth Table Logic for Shutdown and Enable Control

C2. Since C across C2 is 2 times VCC.

is at VCC, the voltage potential

Page 11

Phase 4: VDD Transfer (Figure 16)

The fourth phase of the clock connects the negative terminal of C2 to GND, and transfers this positive generated voltage across C2 to C4, the VDD storage capacitor. This voltage is regulated to +5.5V. At this voltage, the internal oscillator is disabled. Simultaneous with the transfer of the voltage to C4, the positive side of capacitor C1 is switched to VCC and the negative side is connected to GND, allowing the charge pump cycle to repeat. The charge pump cycle will continue as long as the operational conditions for the internal oscillator are present.

Since both V+ and V– are separately generated from VCC; in a no–load condition V+ and V– will be symmetrical. Older charge pump approaches that generate V– from V+ will show a decrease in the magnitude of V– compared to V+ due to the inherent inefficiencies in the design.

The charge pump clock rate typically operates at 250kHz. The external capacitors can be as low as 0.1µF with a 16V breakdown voltage rating.

ESD Tolerance

The SP3222EH/3232EH series incorporates ruggedized ESD cells on all driver output and receiver input pins. The improved ESD tolerance is at least ±15kV without damage or latch-up.

Three methods of ESD testing are performed:

a) MIL-STD-883, Method 3015.7 b) IEC1000-4-2 Air-Discharge c) IEC1000-4-2 Direct Contact

The Human Body Model has been the generally accepted ESD testing method for semiconductors. This method is also specified in MIL-STD883, Method 3015.7 for ESD testing. The premise of this ESD test is to simulate the human body’s potential to store electro-static energy and

discharge it to an integrated circuit. The simulation is performed by using a test model as shown in Figure 17. This method will test the IC’s capability to withstand an ESD transient during normal handling such as in manufacturing areas where the ICs tend to be handled frequently.

The IEC-1000-4-2, formerly IEC801-2, is used for testing ESD on equipment and systems. For system manufacturers, they must guarantee a certain amount of ESD protection since the system itself is exposed to the outside environment and human presence. The premise with IEC1000-4-2 is that the system is required to withstand an amount of static electricity when ESD is applied to points and surfaces of the equipment that are accessible to personnel during normal usage. In many cases, the RS232 transceiver IC receives most of the ESD current when the ESD source is applied to the connector pins. The test circuit for IEC1000-4-2 is shown on Figure 18. There are two methods within IEC1000-4-2, the Air Discharge method and the Contact Discharge method.

With the Air Discharge Method, an ESD voltage is applied to the equipment under test (EUT) through air. This simulates an electrically charged person ready to connect a cable onto the rear of the system. The high energy potential on the person discharges through an arcing path to the rear panel of the system before he or she touches the system. This energy, whether discharged directly or through air, is predominantly a function of the discharge current rather than the discharge voltage. Variables with an air discharge such as approach speed of the object carrying the ESD potential to the system and humidity will tend to change the discharge current. For example, the rise time of the discharge current varies with the approach speed.

Page 12

VCC = +5V

Figure 12. Charge Pump — Phase 1

Figure 13. Charge Pump — Phase 2

+6V

a) C

GND

b) C2-

+5V

––

–5V –5V

VCC = +5V

––

–10V

T[]

–

Storage Capacitor

–

Storage Capacitor

–

Storage Capacitor

–

Storage Capacitor

-6V

Ch1 2.00V Ch2 2.00V M 1.00µs Ch1 5.48V

Figure 14. Charge Pump Waveforms

VCC = +5V

+5V

–5V

––

–5V

–

Storage Capacitor

–

Storage Capacitor

Figure 15. Charge Pump — Phase 3

= +5V

+10V

––

–

Storage Capacitor

–

Storage Capacitor

Figure 16. Charge Pump — Phase 4

Page 13

SW1

SW1SW1

DC Power Source

Figure 17. ESD Test Circuit for Human Body Model

The Contact Discharge Method applies the ESD current directly to the EUT. This method was devised to reduce the unpredictability of the ESD arc. The discharge current rise time is constant since the energy is directly transferred without the air-gap arc. In situations such as hand held systems, the ESD charge can be directly discharged to the equipment from a person already holding the equipment. The current is transferred on to the keypad or the serial port of the equipment directly and then travels through the PCB and finally to the IC.

SW2

SW2SW2

Device Under Test

The circuit models in Figures 17 and 18 represent the typical ESD testing circuits used for all three methods. The CS is initially charged with the DC power supply when the first switch (SW1) is on. Now that the capacitor is charged, the second switch (SW2) is on while SW1 switches off. The voltage stored in the capacitor is then applied through RS, the current limiting resistor, onto the device under test (DUT). In ESD tests, the SW2 switch is pulsed so that the device under test receives a duration of voltage.

Contact-Discharge Module

Contact-Discharge ModuleContact-Discharge Module

SW1

SW1SW1

DC Power Source

Figure 18. ESD Test Circuit for IEC1000-4-2

RS and RV add up to 330Ω for IEC1000-4-2.

andand RR

S S

SW2

SW2SW2

add up to 330add up to 330ΩΩ f for IEC1000-4-2.or IEC1000-4-2.

V V

Device Under Test

Page 14

For the Human Body Model, the current limiting resistor (RS) and the source capacitor (CS) are 1.5kΩ an 100pF, respectively. For

I ➙

30A

IEC-1000-4-2, the current limiting resistor (RS) and the source capacitor (CS) are 330Ω an 150pF, respectively.

15A

The higher CS value and lower RS value in the IEC1000-4-2 model are more stringent than the Human Body Model. The larger storage capacitor injects a higher voltage to the test

point when SW2 is switched on. The lower current limiting resistor increases the current

charge onto the test point.

t=0ns

t ➙

Figure 19. ESD Test Waveform for IEC1000-4-2

t=30ns

Device Pin Human Body IEC1000-4-2

Tested Model Air Discharge Direct Contact Level

Driver Outputs ±15kV ±15kV ±8kV 4 Receiver Inputs ±15kV ±15kV ±8kV 4

Table 3. Transceiver ESD Tolerance Levels

Page 15

PACKAGE: PLASTIC SHRINK

SMALL OUTLINE (SSOP)

DIMENSIONS (Inches)

Minimum/Maximum

(mm)

16–PIN

0.068/0.078 (1.73/1.99)

0.002/0.008 (0.05/0.21)

0.010/0.015 (0.25/0.38)

0.239/0.249 (6.07/6.33)

0.205/0.212 (5.20/5.38)

0.0256 BSC (0.65 BSC)

0.301/0.311 (7.65/7.90)

0.022/0.037 (0.55/0.95)

0°/8°

(0°/8°)

20–PIN

0.068/0.078 (1.73/1.99)

0.002/0.008 (0.05/0.21)

0.010/0.015 (0.25/0.38)

0.278/0.289 (7.07/7.33)

0.205/0.212 (5.20/5.38)

0.0256 BSC (0.65 BSC)

0.301/0.311 (7.65/7.90)

0.022/0.037 (0.55/0.95)

0°/8°

(0°/8°)

24–PIN

0.068/0.078 (1.73/1.99)

0.002/0.008 (0.05/0.21)

0.010/0.015 (0.25/0.38)

0.317/0.328 (8.07/8.33)

0.205/0.212 (5.20/5.38)

0.0256 BSC (0.65 BSC)

0.301/0.311

(7.65/7.90)

0.022/0.037

(0.55/0.95)

0°/8°

(0°/8°)

28–PIN

0.068/0.078 (1.73/1.99)

0.002/0.008 (0.05/0.21)

0.010/0.015 (0.25/0.38)

0.397/0.407

(10.07/10.33)

0.205/0.212 (5.20/5.38)

0.0256 BSC (0.65 BSC)

0.301/0.311 (7.65/7.90)

0.022/0.037 (0.55/0.95)

0°/8°

(0°/8°)

Page 16

D1 = 0.005" min.

(0.127 min.)

e = 0.100 BSC

(2.540 BSC)

ALTERNATE

END PINS

(BOTH ENDS)

PACKAGE: PLASTIC

DUAL–IN–LINE (NARROW)

A1 = 0.015" min.

(0.381min.)

A = 0.210" max.

(5.334 max).

eA = 0.300 BSC

(7.620 BSC)

DIMENSIONS (Inches)

Minimum/Maximum

(mm)

16–PIN

0.115/0.195

(2.921/4.953)

0.014/0.022

(0.356/0.559)

0.045/0.070

(1.143/1.778)

0.008/0.014

(0.203/0.356)

0.780/0.800

(19.812/20.320)

0.300/0.325

(7.620/8.255)

0.240/0.280

(6.096/7.112)

0.115/0.150

(2.921/3.810)

0°/ 15°

(0°/15°)

18–PIN

0.115/0.195

(2.921/4.953)

0.014/0.022

(0.356/0.559)

0.045/0.070

(1.143/1.778)

0.008/0.014

(0.203/0.356)

0.880/0.920

(22.352/23.368)

0.300/0.325

(7.620/8.255)

0.240/0.280

(6.096/7.112)

0.115/0.150

(2.921/3.810)

0°/ 15°

(0°/15°)

Page 17

PACKAGE: PLASTIC

SMALL OUTLINE (SOIC)

DIMENSIONS (Inches)

Minimum/Maximum

(mm) A

16–PIN

0.090/0.104 (2.29/2.649)

0.004/0.012

(0.102/0.300)

0.013/0.020

(0.330/0.508)

0.398/0.413

(10.10/10.49)

0.291/0.299

(7.402/7.600)

0.050 BSC

(1.270 BSC)

0.394/0.419

(10.00/10.64)

0.016/0.050

(0.406/1.270)

0°/8°

(0°/8°)

18–PIN

0.090/0.104

(2.29/2.649))

0.004/0.012

(0.102/0.300)

0.013/0.020

(0.330/0.508)

0.447/0.463

(11.35/11.74)

0.291/0.299

(7.402/7.600)

0.050 BSC

(1.270 BSC)

0.394/0.419

(10.00/10.64)

0.016/0.050

(0.406/1.270)

0°/8°

(0°/8°)

Page 18

P ACKA GE: PLASTIC THIN SMALL

OUTLINE (TSSOP)

DIMENSIONS

in inches (mm)

Minimum/Maximum

16–PIN

- /0.043 (- /1.10)

0.002/0.006 (0.05/0.15)

0.007/0.012 (0.19/0.30)

0.193/0.201 (4.90/5.10)

0.169/0.177 (4.30/4.50)

0.026 BSC

(0.65 BSC)

0.126 BSC (3.20 BSC)

0.020/0.030

(0.50/0.75)

0°/8°

0.002/0.006

0.007/0.012

0.252/0.260

0.169/0.177

0.020/0.030

20–PIN

- /0.043 (- /1.10)

(0.05/0.15)

(0.19/0.30)

(6.40/6.60)

(4.30/4.50)

0.026 BSC (0.65 BSC)

0.126 BSC (3.20 BSC)

(0.50/0.75)

0°/8°

Page 19

ORDERING INFORMATION

Model Temperature Range Package Type

SP3222EHCA .......................................... 0˚C to +70˚C .......................................... 20-Pin SSOP

SP3222EHCP .......................................... 0˚C to +70˚C ............................................ 18-Pin PDIP

SP3222EHCT........................................... 0˚C to +70˚C ........................................... 18-Pin SOIC

SP3222EHCY .......................................... 0˚C to +70˚C ........................................ 20-Pin TSSOP

SP3232EHCA .......................................... 0˚C to +70˚C .......................................... 16-Pin SSOP

SP3232EHCP .......................................... 0˚C to +70˚C ............................................ 16-Pin PDIP

SP3232EHCT........................................... 0˚C to +70˚C .................................. 16-Pin Wide SOIC

SP3232EHCY .......................................... 0˚C to +70˚C ........................................ 16-Pin TSSOP

Please consult the factory for pricing and availability on a Tape-On-Reel option.

Corporation

SIGNAL PROCESSING EXCELLENCE

Sipex Corporation Headquarters and

Sales Office

22 Linnell Circle Billerica, MA 01821 TEL: (978) 667-8700 FAX: (978) 670-9001 e-mail: sales@sipex.com

Sales Office

233 South Hillview Drive Milpitas, CA 95035 TEL: (408) 934-7500 FAX: (408) 935-7600

Sipex Corporation reserves the right to make changes to any products described herein. Sipex does not assume any liability arising out of the application or use of any product or circuit described hereing; neither does it convey any license under its patent rights nor the rights of others.

Datasheet SP3232EHCA, SP3232EHCP, SP3232EHCT, SP3232EHCY, SP3222EHCA Datasheet (Sipex Corporation)

Specifications and Main Features

Frequently Asked Questions

User Manual