Datasheet SP3220ECA, SP3220ECT, SP3220ECY, SP3220EEA, SP3220EET Datasheet (Sipex Corporation)

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Page 1

SP3220E

+3.0V to +5.5V RS-232 Driver/Receiver Pair

■ Meets True RS-232 Protocol Operation From A +3.0V to +5.5V Power Supply

■ 235kbps Data Rate Under Load

■ 1µA Low-Power Shutdown With

Receivers Active

■ Interoperable With RS-232 Down To +2.7V Power Source

■ Pin-Compatible With The Sipex SP3221E Device Without The

Auto-Online

■ Enhanced ESD Specifications:

+15kV Human Body Model +15kV IEC1000-4-2 Air Discharge +8kV IEC1000-4-2 Contact Discharge

DESCRIPTION

The SP3220E device is an RS-232 driver/receiver solution intended for portable or hand-held applications such as notebook or palmtop computers. The SP3220E device has a highefficiency, charge-pump power supply that requires only 0.1µF capacitors in 3.3V operation. This charge pump allows the SP3220E device to deliver true RS-232 performance from a single power supply ranging from +3.3V to +5.0V. The ESD tolerance of the SP3220E device is over +15kV for both Human Body Model and IEC1000-4-2 Air discharge test methods. The SP3220E device has a low-power shutdown mode where the driver outputs and charge pumps are disabled. During shutdown, the supply current falls to less than 1µA.

Feature

0.1µF

4 5

C1+

C1C2+

C2-

T1IN

R1OUT

0.1µF

LOGIC

INPUTS

LOGIC

OUTPUTS

SP3220E

GND

5kΩ

V+

V-

T1OUT

R1IN

SHDN

*can be returned to either V

*C3

RS-232 OUTPUTS

RS-232 INPUTS

or GND

0.1µF

Page 2

ABSOLUTE MAXIMUM RATINGS

These are stress ratings only and functional operation of the device at these ratings or any other above those indicated in the operation sections of the specifications below is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability and cause permanent damage to the device.

Input Voltages

TxIN, EN ..............................................-0.3V to +6.0V

RxIN....................................................................+25V

Output Voltages

TxOUT..............................................................+13.2V

RxOUT........................................-0.3V to (VCC + 0.3V)

Short-Circuit Duration

TxOUT.......................................................Continuous

VCC.............................................................-0.3V to +6.0V

V+ (NOTE 1)..............................................-0.3V to +7.0V

V- (NOTE 1).............................................+0.3V to -7.0V

V+ + |V-| (NOTE 1)...................................................+13V

ICC (DC VCC or GND current)..........................+100mA

Storage Temperature........................-65°C to +150°C

Power Dissipation Per Package

16-pin SSOP (derate 9.69mW/oCabove+70oC)...........775mW

16-pin TSSOP (derate 10.5mW/oC above +70oC).......840mW

16-pin Wide SOIC (derate 11.2mW/oC above+70oC)..900mW

NOTE 1: V+ and V- can have maximum magnitudes of 7V, but their absolute difference cannot exceed 13V.

SPECIFICATIONS

Unless otherwise noted, the following specifications apply for VCC = +3.0V to +5.0V with T Typical Values apply at VCC = +3.3V or +5.0V and T

AMB

= 25oC.

RETEMARAP.NIM.PYT.XAMSTINUSNOITIDNOC

SCITSIRETCARAHCCD

tnerruCylppuS3.00.1AmT,daolon

tnerruCylppuSnwodtuhS0.101µA,DNG=NDHST

STUPTUOREVIECERDNASTUPNICIGOL

AMB

BMA

= T

to T

MIN

52+=

V,C

52+=

BMA

MAX

V3.3=

V,C

V3.3+=

WOLdlohserhTcigoLtupnI8.0V 2etoN,NDHS,NE,NIxT

HGIHdlohserhTcigoLtupnI0.2

4.2

tnerruCegakaeLtupnI10.0±0.1±µA,NDHS,NE,NIxTT

2etoN,V3.3= 2etoN,V0.5=

52+=

BMA

tnerruCegakaeLtuptuO50.0±01±µAdelbasidsreviecer

WOLegatloVtuptuO4.0VI

HGIHegatloVtuptuOV

6.0-VCC1.0-VI

TUO

Am6.1=

Am0.1-=

STUPTUOREVIRD

gniwSegatloVtuptuO0.5±4.5±Vk3Ω ,stuptuorevirdllatadnuorgotdaol

ecnatsiseRtuptuO003ΩV

tnerruCtiucriC-trohStuptuO53±

07±

06±

001±

tnerruCegakaeLtuptuO52±µAV

52+=

BMA

T,V0=-V=+V=

V0=

TUO

=+ V51

TUO

=+ V,V21

TUO

=+ V2

TUO

delbasidsrevird,V5.5otV0=

Page 3

SPECIFICATIONS (continued)

Unless otherwise noted, the following specifications apply for VCC = +3.0V to +5.0V with T Typical Values apply at VCC = +3.3V or +5.0V and T

RETEMARAP.NIM.PYT.XAMSTINUSNOITIDNOC

STUPNIREVIECER

egnaRegatloVtupnI51-51+V

AMB

= 25oC.

AMB

= T

MIN

to T

MAX

WOLdlohserhTtupnI6.0

HGIHdlohserhTtupnI5.1

2.1

8.0

5.1

4.2

8.1

4.2

V3.3= V0.5=

siseretsyHtupnI3.0V

ecnatsiseRtupnI357kΩ

SCITSIRETCARAHCGNIMIT

etaRataDmumixaM021532spbkR

yaleDnoitagaporPrevirD0.1

0.1

yaleDnoitagaporPrevieceR3.0

µs µs

µst

3.0

k3=ΩC,

t t

HLP

K3=ΩC,

LHP

K3=ΩC,

LHP

emiTelbanEtuptuOrevieceR002sn

emiTelbasiDtuptuOrevieceR002sn

wekSrevirD001005snt|

wekSrevieceR0020001snt|

etaRwelSnoigeR-noitisnarT03/VµsV

LHP

HLP

T,|

BMA

R,V3.3=

V0.3-otV0.3+ro

L L

Fp0001= Fp0001=

C,TUOxRotNIxR, C,TUOxRotNIxR,

L L

Fp051= Fp051=

52=oC

K3=ΩT,

BMA

52=o,C

V0.3+otV0.3-morfnekatstnemerusaem

gnihctiwsrevirdeno,Fp0001=

NOTE 2: Driver input hysteresis is typically 250mV.

Page 4

TYPICAL PERFORMANCE CHARACTERISTICS

Unless otherwise noted, the following performance characteristics apply for VCC = +3.3V, 235kbps data rates, all drivers loaded with 3kΩ, 0.1µF charge pump capacitors, and T

= +25°C.

AMB

Transmitter Output Voltage [V]

-2

-4

-6

500

1000

Load Capacitance [pF]

1500

2000

Figure 1. Transmitter Output Voltage VS. Load Capacitance for the SP3220E

0 500

118KHz 60KHz 10KHz

1000

Load Capacitance [pF]

1500

2000

Supply Current [mA]

Vout+ Vout-

2330

Slew Rate [V/µs]

0 500

1000

Load Capacitance [pF]

1500

2000

+Slew

-Slew

Figure 2. Slew Rate VS. Load Capacitance for the

SP3220E

2330

Figure 3. Supply Current VS. Load Capacitance when Transmitting Data for the SP3220E

Page 5

EMANNOITCNUFREBMUNNIP

.)etatsZ-hgih(stuptuoreviecerehtetatS

-irTotHGIHevirD.noitarepolamronrofWOLevirD.lortnoCelbanErevieceR 1

+1C.roticapacpmup-egrahcrelbuodegatlovehtfolanimretevitisoP 2

+V.pmupegrahcehtybdetarenegV5.5+ 3

-1C.roticapacpmup-egrahcrelbuodegatlovehtfolanimretevitageN 4

+2C.roticapacpmup-egrahcgnitrevniehtfolanimretevitisoP 5

-2C.roticapacpmup-egrahcgnitrevniehtfolanimretevitageN 6

-V.pmupegrahcehtybdetarenegV5.5- 7 NI1R.tupnireviecer232-SR 8

TUO1R.tuptuoreveicerSOMC/LTT 9

.C.N.tcennoCoN 21,01

NI1T.tupnirevirdSOMC/LTT 11

TUO1T.tuptuorevird232-SR 31

DNG.dnuorG 41

egatlovylppusV5.5+otV0.3+ 51

otWOLevirD.noitarepoecivedlamronrofHGIHevirD.tupnIlortnoCnwodtuhS

NDHS

rewoppmupegrahcdraob-noehtdna)tuptuoZ-hgih(srevirdehtnwodtuhs

.ylppus

Table 1. Device Pin Description

Page 6

SHDN

C1+

V+

C1-

C2+

C2-

V-

R1IN

Figure 4. Pinout Configurations for the SP3220E

3 4 5 6

7 8

SP3220E

15 14 13

GND T1OUT

No Connect

T1IN

No Connect

R1OUT

Page 7

LOGIC

INPUTS

LOGIC

OUTPUTS

0.1µF

4 5

C1+

C1C2+

C2-

T1IN

R1OUT

SP3220E

5kΩ

GND

V+

V-

T1OUT

R1IN

SHDN

*C3

0.1µF

RS-232 OUTPUTS

RS-232 INPUTS

*can be returned to either V

or GND

Figure 5. SP3220E Typical Operating Circuits

Page 8

DESCRIPTION

The SP3220E device meets the EIA/TIA-232 and V.28/V.24 communication protocols and can be implemented in battery-powered, portable, or hand-held applications such as notebook or palmtop computers. The SP3220E device features Sipex's proprietary on-board charge pump circuitry that generates 2 x VCC for RS-232 voltage levels from a single +3.0V to +5.5V power supply. This series is ideal for +3.3V-only systems, mixed +3.0V to +5.5V systems, or +5.0V-only systems that require true RS-232 performance. The SP3220E device has a driver that operates at a typical data rate of 235Kbps fully loaded.

The SP3220E is a 1-driver/1-receiver device ideal for portable or hand-held applications. The SP3220E features a 1µA shutdown mode that reduces power consumption and extends battery life in portable systems. Its receivers remain active in shutdown mode, allowing external devices such as modems to be monitored using only 1µA supply current.

THEORY OF OPERATION

The SP3220E device is made up of three basic circuit blocks: 1. Drivers, 2. Receivers, and 3. the Sipex proprietary charge pump.

Drivers

The drivers are inverting level transmitters that convert TTL or CMOS logic levels to +5.0V EIA/TIA-232 levels inverted relative to the input logic levels. Typically, the RS-232 output voltage swing is +5.5V with no load and at least +5V minimum fully loaded. The driver outputs are protected against infinite short-circuits to ground without degradation in reliability. Driver outputs will meet EIA/TIA-562 levels of +3.7V with supply voltages as low as 2.7V.

The slew rate of the driver output is internally limited to a maximum of 30V/µs in order to meet the EIA standards (EIA RS-232D 2.1.7, Paragraph 5). The transition of the loaded output from HIGH to LOW also meets the monotonicity requirements of the standard.

The SP3220E driver can maintain high data rates up to 240Kbps fully loaded. Figure 6 shows a loopback test circuit used to test the RS-232 driver. Figure 7 shows the test results of the loopback circuit with the driver active at 120Kbps with an RS-232 load in parallel with a 1000pF capacitor. Figure 8 shows the test results where the driver was active at 235Kbps and loaded with an RS-232 receiver in parallel with a 1000pF capacitor. A solid RS-232 data transmission rate of 120Kbps provides compatibility with many designs in personal computer peripherals and LAN applications.

The SP3220E driver's output stage is turned off (high-Z) when the device is in shutdown mode. When the power is off, the SP3220E device permits the outputs to be driven up to +12V. The driver's input does not have pull-up resistors. Designers should connect an unused input to VCC or GND.

In the shutdown mode, the supply current falls to less than 1µA, where SHDN = LOW. When the SP3220E device is shut down, the device's driver output is disabled (high-Z) and the charge pump is turned off with V+ pulled down to V and V- pulled to GND. The time required to exit shutdown is typically 100µs. Connect SHDN to VCC if the shutdown mode is not used. SHDN has no effect on RxOUT. Note that the driver is enabled only when the magnitude of V- exceeds approximately 3V.

The drivers typically can operate at a data rate of 235Kbps. The drivers can guarantee a data rate of 120Kbps fully loaded with 3KΩ in parallel with 1000pF, ensuring compatibility with PC-to-PC communication software.

Page 9

LOGIC

INPUTS

0.1µF

C1+

C1-

C2+

C2TxIN

SP3220E

V+

TxOUT

0.1µF

V-

0.1µF

LOGIC

OUTPUTS

RxOUT

Figure 6. SP3220E Driver Loopback Test Circuit

T1 IN

T1 OUT

R1 OUT

[]

5.00V

Ch1

Ch3

5.00V

Ch2

5.00V M 5.00µs

Ch1

RxIN

5kΩ

*SHDN

GND

1000pF

[]

T1 IN

T1 OUT

R1 OUT

Ch1

Ch3

5.00V

Ch2

5.00V M 2.50µs

Ch1

Figure 7. Driver Loopback Test Results at 120kbps Figure 8. Driver Loopback Test Results at 235kbps

Page 10

Receivers

The receiver converts EIA/TIA-232 levels to TTL or CMOS logic output levels. The receiver has an inverting high-impedance output. This receiver output (RxOUT) is at high-impedance when the enable control EN = HIGH. In the shutdown mode, the receiver can be active or inactive. EN has no effect on TxOUT. The truth table logic of the SP3220E driver and receiver outputs can be found in Table 2.

Since receiver input is usually from a transmission line where long cable lengths and system interference can degrade the signal, the inputs have a typical hysteresis margin of 300mV. This ensures that the receiver is virtually immune to noisy transmission lines. Should an input be left unconnected, a 5kΩ pulldown resistor to ground will commit the output of the receiver to a HIGH state.

Charge Pump

The charge pump is a Sipex–patented design (U.S. 5,306,954) and uses a unique approach compared to older less–efficient designs. The charge pump still requires four external capacitors, but uses a four–phase voltage shifting technique to attain symmetrical 5.5V power supplies. The internal power supply consists of a regulated dual charge pump that provides output voltages 5.5V regardless of the input voltage (VCC) over the +3.0V to +5.5V range.

NDHSNETUOxTTUOxR

00 etats-irTevitcA 01 etats-irTetats-irT

10 evitcAevitcA 11 evitcAetats-irT

Table 2. Truth Table Logic for Shutdown and Enable Control

In most circumstances, decoupling the power supply can be achieved adequately using a 0.1µF bypass capacitor at C5 (refer to Figures 5). In applications that are sensitive to powersupply noise, decouple VCC to ground with a capacitor of the same value as charge-pump capacitor C1. Physically connect bypass capacitors as close to the IC as possible.

The charge pumps operate in a discontinuous mode using an internal oscillator. If the output voltages are less than a magnitude of 5.5V, the charge pumps are enabled. If the output voltage exceed a magnitude of 5.5V, the charge pumps are disabled. This oscillator controls the four phases of the voltage shifting. A description of each phase follows.

Phase 1

— VSS charge storage — During this phase of the clock cycle, the positive side of capacitors C1 and C2 are initially charged to VCC. C switched to GND and the charge in C transferred to C

–

. Since C

is connected to VCC,

is then

–

the voltage potential across capacitor C2 is now 2 times VCC.

Phase 2

— VSS transfer — Phase two of the clock connects the negative terminal of C2 to the V storage capacitor and the positive terminal of C to GND. This transfers a negative generated voltage to C3. This generated voltage is regulated to a minimum voltage of -5.5V. Simultaneous with the transfer of the voltage to C3, the positive side of capacitor C1 is switched to VCC and the negative side is connected to GND.

Phase 3

— VDD charge storage — The third phase of the clock is identical to the first phase — the charge transferred in C1 produces –VCC in the negative terminal of C1, which is applied to the negative side of capacitor C2. Since C

is at VCC, the

voltage potential across C2 is 2 times VCC.

Page 11

Phase 4

— VDD transfer — The fourth phase of the clock connects the negative terminal of C2 to GND, and transfers this positive generated voltage across C2 to C4, the VDD storage capacitor. This voltage is regulated to +5.5V. At this voltage, the internal oscillator is disabled. Simultaneous with the transfer of the voltage to C4, the positive side of capacitor C1 is switched to VCC and the negative side is connected to GND, allowing the charge pump cycle to begin again. The charge pump cycle will continue as long as the operational conditions for the internal oscillator are present.

Since both V+ and V– are separately generated from VCC; in a no–load condition V+ and V– will be symmetrical. Older charge pump approaches that generate V– from V+ will show a decrease in the magnitude of V– compared to V+ due to the inherent inefficiencies in the design.

The clock rate for the charge pump typically operates at 250kHz. The external capacitors can be as low as 0.1µF with a 16V breakdown voltage rating.

ESD Tolerance

The SP3220E device incorporates ruggedized ESD cells on all driver output and receiver input pins. The ESD structure is improved over our previous family for more rugged applications and environments sensitive to electro-static discharges and associated transients. The improved ESD tolerance is at least +15kV without damage nor latch-up.

There are different methods of ESD testing applied:

a) MIL-STD-883, Method 3015.7 b) IEC1000-4-2 Air-Discharge c) IEC1000-4-2 Direct Contact

The Human Body Model has been the generally accepted ESD testing method for semiconductors. This method is also specified in MIL-STD-883, Method 3015.7 for ESD testing. The premise of this ESD test is to simulate the human body’s

potential to store electro-static energy and discharge it to an integrated circuit. The simulation is performed by using a test model as shown in Figure 14. This method will test the IC’s capability to withstand an ESD transient during normal handling such as in manufacturing areas where the ICs tend to be handled frequently.

The IEC-1000-4-2, formerly IEC801-2, is generally used for testing ESD on equipment and systems. For system manufacturers, they must guarantee a certain amount of ESD protection since the system itself is exposed to the outside environment and human presence. The premise with IEC1000-4-2 is that the system is required to withstand an amount of static electricity when ESD is applied to points and surfaces of the equipment that are accessible to personnel during normal usage. The transceiver IC receives most of the ESD current when the ESD source is applied to the connector pins. The test circuit for IEC1000-4-2 is shown on Figure 15. There are two methods within IEC1000-4-2, the Air Discharge method and the Contact Discharge method.

With the Air Discharge Method, an ESD voltage is applied to the equipment under test (EUT) through air. This simulates an electrically charged person ready to connect a cable onto the rear of the system only to find an unpleasant zap just before the person touches the back panel. The high energy potential on the person discharges through an arcing path to the rear panel of the system before he or she even touches the system. This energy, whether discharged directly or through air, is predominantly a function of the discharge current rather than the discharge voltage. Variables with an air discharge such as approach speed of the object carrying the ESD potential to the system and humidity will tend to change the discharge current. For example, the rise time of the discharge current varies with the approach speed.

Page 12

VCC = +5V

Figure 9. Charge Pump — Phase 1

Figure 10. Charge Pump — Phase 2

GND GND

+5V

––

–5V –5V

VCC = +5V

––

–10V

+6V

a) C

b) C2-

–

Storage Capacitor

–

Storage Capacitor

–

Storage Capacitor

–

Storage Capacitor

T[]

-6V

Ch1 2.00V Ch2 2.00V M 1.00µs Ch1 5.48V

Figure 11. Charge Pump Waveforms

VCC = +5V

+5V

–5V

––

–5V

–

Storage Capacitor

–

Storage Capacitor

Figure 12. Charge Pump — Phase 3

= +5V

+10V

––

–

Storage Capacitor

–

Storage Capacitor

Figure 13. Charge Pump — Phase 4

Page 13

SW1

SW1SW1

DC Power Source

Figure 14. ESD Test Circuit for Human Body Model

The Contact Discharge Method applies the ESD current directly to the EUT. This method was devised to reduce the unpredictability of the ESD arc. The discharge current rise time is constant since the energy is directly transferred without the air-gap arc. In situations such as hand held systems, the ESD charge can be directly discharged to the equipment from a person already holding the equipment. The current is transferred on to the keypad or the serial port of the equipment directly and then travels through the PCB and finally to the IC.

SW2

SW2SW2

Device Under Test

The circuit models in Figures 14 and 15 represent the typical ESD testing circuits used for all three methods. The CS is initially charged with the DC power supply when the first switch (SW1) is on. Now that the capacitor is charged, the second switch (SW2) is on while SW1 switches off. The voltage stored in the capacitor is then applied through RS, the current limiting resistor, onto the device under test (DUT). In ESD tests, the SW2 switch is pulsed so that the device under test receives a duration of voltage.

Contact-Discharge Module

Contact-Discharge ModuleContact-Discharge Module

SW1

SW1SW1

DC Power Source

Figure 15. ESD Test Circuit for IEC1000-4-2

RS and RV add up to 330Ω for IEC1000-4-2.

andand RR

S S

SW2

SW2SW2

add up to 330add up to 330ΩΩ f for IEC1000-4-2.or IEC1000-4-2.

V V

Device Under Test

Page 14

For the Human Body Model, the current limiting resistor (RS) and the source capacitor (CS) are 1.5kΩ an 100pF, respectively. For

I ➙

30A

IEC-1000-4-2, the current limiting resistor (RS) and the source capacitor (CS) are 330Ω an 150pF, respectively.

15A

The higher CS value and lower RS value in the IEC1000-4-2 model are more stringent than the Human Body Model. The larger storage capacitor injects a higher voltage to the test point when SW2 is switched on. The lower current limiting resistor increases the current

charge onto the test point.

t=0ns

t ➙

Figure 16. ESD Test Waveform for IEC1000-4-2

t=30ns

Device Pin Human Body IEC1000-4-2

Tested Model Air Discharge Direct Contact Level

Driver Outputs +15kV +15kV +8kV 4 Receiver Inputs

Table 3. Transceiver ESD Tolerance Levels

+15kV +15kV +8kV 4

Page 15

PACKAGE: PLASTIC SHRINK

SMALL OUTLINE (SSOP)

DIMENSIONS (Inches)

Minimum/Maximum

(mm)

16–PIN

0.068/0.078 (1.73/1.99)

0.002/0.008 (0.05/0.21)

0.010/0.015 (0.25/0.38)

0.239/0.249 (6.07/6.33)

0.205/0.212 (5.20/5.38)

0.0256 BSC (0.65 BSC)

0.301/0.311

(7.65/7.90)

0.022/0.037

(0.55/0.95)

0°/8°

(0°/8°)

20–PIN

0.068/0.078 (1.73/1.99)

0.002/0.008 (0.05/0.21)

0.010/0.015 (0.25/0.38)

0.278/0.289 (7.07/7.33)

0.205/0.212 (5.20/5.38)

0.0256 BSC (0.65 BSC)

0.301/0.311 (7.65/7.90)

0.022/0.037 (0.55/0.95)

0°/8°

(0°/8°)

24–PIN

0.068/0.078 (1.73/1.99)

0.002/0.008 (0.05/0.21)

0.010/0.015 (0.25/0.38)

0.317/0.328 (8.07/8.33)

0.205/0.212 (5.20/5.38)

0.0256 BSC

(0.65 BSC)

0.301/0.311 (7.65/7.90)

0.022/0.037 (0.55/0.95)

0°/8°

(0°/8°)

28–PIN

0.068/0.078 (1.73/1.99)

0.002/0.008 (0.05/0.21)

0.010/0.015 (0.25/0.38)

0.397/0.407

(10.07/10.33)

0.205/0.212 (5.20/5.38)

0.0256 BSC (0.65 BSC)

0.301/0.311 (7.65/7.90)

0.022/0.037 (0.55/0.95)

0°/8°

(0°/8°)

Page 16

PACKAGE: PLASTIC

SMALL OUTLINE (SOIC)

DIMENSIONS (Inches)

Minimum/Maximum

(mm) A

16–PIN

0.090/0.104 (2.29/2.649)

0.004/0.012

(0.102/0.300)

0.013/0.020

(0.330/0.508)

0.398/0.413

(10.10/10.49)

0.291/0.299

(7.402/7.600)

0.050 BSC

(1.270 BSC)

0.394/0.419

(10.00/10.64)

0.016/0.050

(0.406/1.270)

0°/8°

(0°/8°)

18–PIN

0.090/0.104

(2.29/2.649))

0.004/0.012

(0.102/0.300)

0.013/0.020

(0.330/0.508)

0.447/0.463

(11.35/11.74)

0.291/0.299

(7.402/7.600)

0.050 BSC

(1.270 BSC)

0.394/0.419

(10.00/10.64)

0.016/0.050

(0.406/1.270)

0°/8°

(0°/8°)

Page 17

P ACKA GE: PLASTIC THIN SMALL

OUTLINE (TSSOP)

DIMENSIONS

in inches (mm)

Minimum/Maximum

16–PIN

- /0.043

(- /1.10)

0.002/0.006 (0.05/0.15)

0.007/0.012 (0.19/0.30)

0.193/0.201 (4.90/5.10)

0.169/0.177 (4.30/4.50)

0.026 BSC (0.65 BSC)

0.126 BSC (3.20 BSC)

0.020/0.030 (0.50/0.75)

0°/8°

20–PIN

- /0.043 (- /1.10)

0.002/0.006 (0.05/0.15)

0.007/0.012 (0.19/0.30)

0.252/0.260 (6.40/6.60)

0.169/0.177 (4.30/4.50)

0.026 BSC

(0.65 BSC)

0.126 BSC

(3.20 BSC)

0.020/0.030 (0.50/0.75)

0°/8°

Page 18

ORDERING INFORMATION

Model Temperature Range Package Type

SP3220ECA ............................................. 0˚C to +70˚C .......................................... 16-Pin SSOP

SP3220ECT ............................................. 0˚C to +70˚C .................................. 16-Pin Wide SOIC

SP3220ECY............................................. 0˚C to +70˚C ........................................ 16-Pin TSSOP

SP3220EEA ............................................ -40˚C to +85˚C ........................................ 16-Pin SSOP

SP3220EET ............................................ -40˚C to +85˚C ................................ 16-Pin Wide SOIC

SP3220EEY ............................................ -40˚C to +85˚C ...................................... 16-Pin TSSOP

Corporation

SIGNAL PROCESSING EXCELLENCE

Sipex Corporation Headquarters and

Sales Office

22 Linnell Circle Billerica, MA 01821 TEL: (978) 667-8700 FAX: (978) 670-9001 e-mail: sales@sipex.com

Sales Office

233 South Hillview Drive Milpitas, CA 95035 TEL: (408) 934-7500 FAX: (408) 935-7600

Sipex Corporation reserves the right to make changes to any products described herein. Sipex does not assume any liability arising out of the application or use of any product or circuit described hereing; neither does it convey any license under its patent rights nor the rights of others.

Datasheet SP3220ECA, SP3220ECT, SP3220ECY, SP3220EEA, SP3220EET Datasheet (Sipex Corporation)

Specifications and Main Features

Frequently Asked Questions

User Manual