Octal Sample-and-Hold
a
FEATURES
High Speed Version of SMP08
Internal Hold Capacitors
Low Droop Rate
TTL/CMOS Compatible Logic Inputs
Single or Dual Supply Operation
Break-Before-Make Channel Addressing
Compatible With CD4051 Pinout
Low Cost
APPLICATIONS
Multiple Path Timing Deskew for A.T.E.
Memory Programmers
Mass Flow/Process Control Systems
Multichannel Data Acquisition Systems
Robotics and Control Systems
Medical and Analytical Instrumentation
Event Analysis
Stage Lighting Control
GENERAL DESCRIPTION
The SMP18 is a monolithic octal sample-and-hold; it has eight
internal buffer amplifiers, input multiplexer, and internal hold
capacitors. It is manufactured in an advanced oxide isolated
CMOS technology to obtain high accuracy, low droop rate, and
fast acquisition time. The SMP18 has a typical linearity error of
only 0.01% and can accurately acquire a 10-bit input signal to
±1/2 LSB in less than 2.5 microseconds. The SMP18’s output
swing includes the negative supply in both single and dual supply operation.
The SMP18 was specifically designed for systems that use a
calibration cycle to adjust a multiple of system parameters. The
low cost and high level of integration make the SMP18 ideal for
calibration requirements that have previously required an ASIC,
or high cost multiple D/A converters.
The SMP18 is also ideally suited for a wide variety of sampleand-hold applications including amplifier offset or VCA gain adjustments. One or more SMP18s can be used with single or
multiple DACs to provide multiple set points within a system.
with Multiplexed Input
SMP18
FUNCTIONAL BLOCK DIAGRAM
(LSB)
A
INPUT
3
SW
SW
HOLD CAPS
(INTERNAL)
SMP18
The SMP18 offers significant cost and size reduction over
discrete designs. It is available in a 16-pin plastic DIP, a
narrow body SO-16 surface-mount SOIC package or the thin
TSSOP-16 package. The SMP18 is a higher speed direct
replacement for the SMP08.
(MSB)
C
B
1 OF 8 DECODER
SW
SW
SW
SW
INH
SW
691011
8
DGND
16
V
DD
SW
13
14
15
12
1
5
2
4
7
CH0OUT
CH1OUT
CH2OUT
OUT
CH
3
OUT
CH
4
CH5OUT
CH6OUT
OUT
CH
7
V
SS
REV. C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700 World Wide Web Site: http://www.analog.com
Fax: 617/326-8703 © Analog Devices, Inc., 1996
SMP18–SPECIFICATIONS
(@ VDD = +5 V, VSS = –5 V, DGND = 0 V, RL = No Load, TA = –408C to +858C for SMP18F,
ELECTRICAL CHARACTERISTICS
P
arameter Symbol Conditions Min Typ Max Units
unless otherwise noted)
Linearity Error –3 V ≤ V
Buffer Offset Voltage V
OS
TA = +25°C, VIN = 0 V 2.5 10 mV
–40°C ≤ T
Hold Step V
Droop Rate ∆V
Output Source Current I
Output Sink Current I
HS
CH
SOURCE
SINK
VIN = 0 V, TA = +25°C to +85°C 46mV
V
IN
/∆tTA = +25°C, VIN = 0 V 2 40 mV/s
VIN = 0 V
VIN = 0 V
≤ +3 V 0.01 %
IN
≤ +85°C, VIN = 0 V 3.5 20 mV
A
= 0 V, TA = –40°C8mV
1
1
1.2 mA
0.5 mA
Output Voltage Range RL = 20 kΩ –3.0 +3.0 V
LOGIC CHARACTERISTICS
Logic Input High Voltage V
Logic Input Low Voltage V
Logic Input Current I
DYNAMIC PERFORMANCE
Acquisition Time
3
2
Hold Mode Settling Time t
Channel Select Time t
Channel Deselect Time t
Inhibit Recovery Time t
t
INH
INL
IN
AQ
H
CH
DCS
IR
VIN = 2.4 V 0.5 1 µA
TA = +25°C, –3 V to +3 V to 0.1% 3.5 µs
To ±1 mV of Final Value 1 µs
2.4 V
0.8 V
90 ns
45 ns
90 ns
Slew Rate SR 6 V/µs
Capacitive Load Stability <30% Overshoot 500 pF
Analog Crosstalk –3 V to +3 V Step –72 dB
SUPPLY CHARACTERISTICS
Power Supply Rejection Ratio PSRR V
Supply Current I
DD
= ±5 V to ±6 V 60 75 dB
SS
TA = +25°C 5.5 7.5 mA
–40°C ≤ TA ≤ +85°C
7.5 9.5 mA
(@ VDD = +12 V, VSS = 0 V, DGND = 0 V, RL = No Load, TA = –408C to +858C for SMP18F,
ELECTRICAL CHARACTERISTICS
unless otherwise noted)
Parameter Symbol Conditions Min Typ Max Limits
Linearity Error 60 mV ≤ V
Buffer Offset Voltage V
OS
TA = +25°C, VIN = 6 V 2.5 10 mV
–40°C ≤ T
Hold Step V
Droop Rate ∆V
Output Source Current I
Output Sink Current I
HS
CH
SOURCE
SINK
Output Voltage Range R
VIN = 6 V, TA = +25°C to +85°C 46mV
V
= 6 V, TA = –40°C8mV
IN
/∆tTA = +25°C, VIN = 6 V 2 40 mV/s
VIN = 6 V
VIN = 6 V
= 20 kΩ 0.06 10.0 V
L
≤ 10 V 0.01 %
IN
≤ +85°C, VIN = 6 V 3.5 20 mV
A
1
1
1.2 mA
0.5 mA
RL = 10 kΩ 0.06 9.5 V
LOGIC CHARACTERISTICS
Logic Input High Voltage V
Logic Input Low Voltage V
Logic Input Current I
DYNAMIC PERFORMANCE
Acquisition Time
3
2
Hold Mode Settling Time t
Channel Select Time t
Channel Deselect Time t
Inhibit Recovery Time t
Slew Rate
4
INH
t
INL
IN
AQ
H
CH
DCS
IR
VIN = 2.4 V 0.5 1 µA
TA = +25°C, 0 to 10 V to 0.1% 2.5 3.25 µs
To ±1 mV of Final Value 1 µs
SR 7 V/µs
2.4 V
0.8 V
90 ns
45 ns
90 ns
Capacitive Load Stability <30% Overshoot 500 pF
Analog Crosstalk 0 V to 10 V Step –72 dB
SUPPLY CHARACTERISTICS
Power Supply Rejection Ratio PSRR 10.8 V ≤ V
Supply Current I
DD
TA = +25°C 6.0 8.0 mA
≤ 13.2 V 60 75 dB
DD
–40°C ≤ TA ≤ +85°C 8.0 10.0 mA
NOTES
1
Outputs are capable of sinking and sourcing over 10 mA but offset is guaranteed at specified load levels.
2
All input control signals are specified with tr = tf = 5 ns (10% to 90% of +5 V) and timed from a voltage level of 1.6 V.
3
This parameter is guaranteed without test.
4
Slew rate is measured in the sample mode with a 0 to 10 V step from 20% to 80%.
Specifications subject to change without notice.
–2–
REV. C
SMP18
14
13
12
11
16
15
10
9
8
1
2
3
4
7
6
5
TOP VIEW
(Not to Scale)
SMP18
CH4OUT
CH
0
OUT
CH
1
OUT
CH
2
OUT
V
DD
CH6OUT
INPUT
CH
7
OUT
B CONTROL
A CONTROL
CH
3
OUT
CH
5
OUT
INH
V
SS
DGND
C CONTROL
WARNING!
ESD SENSITIVE DEVICE
ABSOLUTE MAXIMUM RATINGS
PIN CONNECTIONS
VDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, 17 V
V
to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, 17 V
DD
V
to DGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, V
LOGIC
VIN to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSS, V
V
to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSS, V
OUT
DD
DD
DD
Analog Output Current . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
(Not short-circuit protected)
Operating Temperature Range
FP, FS . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . +150°C
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 60 sec) . . . . . . . . . . . . +300°C
Package Type uJA* u
JC
16-Pin Plastic DIP (P) 76 33 °C/W
16-Pin SOIC (S) 92 27 °C/W
16-Lead TSSOP (RU) 180 35 °C/W
NOTES
*θJA is specified for worst case mounting conditions, i.e., θJA is specified for device
in socket for plastic DIP packages; θJA is specified for device soldered to printed
circuit board for SOIC and TSSOP packages.
Units
ORDERING GUIDE
Temperature Package Package
Model Range Description Option
SMP18FP –40°C to +85°C Plastic DIP N-16
SMP18FRU –40°C to +85°C TSSOP-16 RU-16
SMP18FS –40°C to +85°C SO-16 R-16A
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the SMP18 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
REV. C
–3–
SMP18
INPUT VOLTAGE – Volts
DROOP RATE – mV/s
130
70
10
01 10
23456789
110
90
50
30
VDD = +12V
VSS = 0V
T
A
= +85°C
NO LOAD
VDD – Volts
SLEW RATE – V/µs
30
0
10 11 18
12 13 14 15 16 17
25
20
15
10
5
VDD = +12V
V
SS
= 0V
T
A
= +25°C
NO LOAD
+SR
–SR
INPUT VOLTAGE – Volts
OFFSET VOLTAGE – mV
4
–10
01 10
23456789
2
0
–2
–4
–6
–8
VDD = +12V
VSS = 0V
T
A
= –40°C
RL =
∞
RL = 20kΩ
RL = 10kΩ
–Typical Performance Characteristics
100
VDD = +12V
V
= 0V
SS
= +6V
V
IN
10
R
= 10kΩ
L
0
DROOP RATE – mV/s
0.1
0.01
–40 –20 100
020406080
TEMPERATURE – °C
Droop Rate vs. Temperature
0
–1
–2
–3
–4
HOLD STEP – mV
–5
–6
23456789
01 10
INPUT VOLTAGE – Volts
VDD = +12V
VSS = 0V
T
= +25°C
A
NO LOAD
5
3
1
–1
DROOP RATE – mV/s
–3
–5
01 10
234 567 89
INPUT VOLTAGE – Volts
VDD = +12V
VSS = 0V
T
= +25°C
A
NO LOAD
Droop Rate vs. Input Voltage
1
VDD = +12V
0
V
= 0V
SS
= 6V
V
IN
–1
NO LOAD
–2
–3
–4
HOLD STEP – mV
–5
–6
–7
–55 –35 125
–15 5 25 65 85 10545
TEMPERATURE – °C
Droop Rate vs. Input Voltage
Hold Step vs. Input Voltage
4
2
RL =
0
–2
–4
–6
OFFSET VOLTAGE – mV
–8
–10
01 10
∞
RL = 20kΩ
RL = 10kΩ
23456789
INPUT VOLTAGE – Volts
Offset Voltage vs. Input Voltage
VDD = +12V
VSS = 0V
T
= +25°C
A
Hold Step vs. Temperature
20
15
10
5
0
–5
–10
OFFSET VOLTAGE – mV
–15
–20
01 10
RL =
RL = 10kΩ
23456789
INPUT VOLTAGE – Volts
VDD = +12V
VSS = 0V
T
= +85°C
A
∞
RL = 20kΩ
Offset Voltage vs. Input Voltage
–4–
Slew Rate vs. V
DD
Offset Voltage vs. Input Voltage
REV. C
Typical Performance Characteristics–
FREQUENCY – Hz
90
80
0
10 100 1M1k 10k 100k
70
60
20
50
40
30
10
REJECTION RATIO – dB
VDD = +12V
VSS = 0V
V
IN
= +6V
T
A
= +25°C
NO LOAD
+PSRR
–PSRR
FREQUENCY – Hz
REJECTION RATIO – dB
60
50
–10
10 100 1M
1k 10k 100k
40
30
20
10
0
VDD = +12V
VSS = 0V
T
A
= +25°C
NO LOAD
+PSRR
HOLD CAPACITORS
REFERENCED TO V
SS
–PSRR
SMP18
0
–1
–2
–3
–4
–5
–6
OFFSET VOLTAGE – mV
–7
–8
–55 –35 125
–15 5 25 65 85 10545
TEMPERATURE – °C
VDD = +12V
VSS = 0V
= +5V
V
IN
R
= 10kΩ
L
Offset Voltage vs. Temperature
2
1
0
–1
–2
GAIN – dB
–3
–4
–5
100 1k 10M
10k 100k 1M
FREQUENCY – Hz
14
12
10
8
6
SUPPLY CURRENT – mA
4
2
VDD = +6V
VSS = –6V
T
= +25°C
A
NO LOAD
PHASE
GAIN
VSS = 0V
NO LOAD
+85°C
+25°C
–40°C
46 18
8 10121416
VDD – Volts
Supply Current vs. V
90
45
0
–45
–90
–135
PHASE SHIFT – Degrees
–180
–225
DD
35
VDD = +12V
VSS = 0V
30
T
= +25°C
A
NO LOAD
25
20
15
10
OUTPUT IMPEDANCE – Ω
5
0
10 100 1M1k 10k 100k
Sample Mode Power Supply Rejection
FREQUENCY – Hz
REV. C
Gain, Phase Shift vs. Frequency
15
12
9
6
3
PEAK-TO-PEAK OUTPUT – Volts
0
10k 100k 10M1M
FREQUENCY – Hz
VDD = +6V
VSS = –6V
T
= +25°C
A
NO LOAD
Maximum Output Voltage vs.
Frequency
Output Impedance vs. Frequency
Hold Mode Power Supply Rejection
–5–
SMP18
10kΩ
V
CC
+15V
1
2
3
4
5
6
7
8
R4
1kΩ
SMP18
C1
10µF
+
C2
1µF
R2
10kΩR210kΩR210kΩR210kΩ
16
15
14
13
12
11
10
R1
10Ω
9
D1
R3
2kΩ
R2
R2
R2
R2
10kΩ
10kΩ
10kΩ
Burn-in Circuit
APPLICATIONS INFORMATION
The SMP18, a multiplexed octal S/H, minimizes board space
in systems requiring cycled calibration or an array of control
voltages. When used in conjunction with a low cost 16-bit D/A,
the SMP18 can easily be integrated into microprocessor based
systems. Since the SMP18 features break-before-make switching
and an internal decoder, no external logic is required. The
SMP18 has an internally regulated TTL supply so that
TTL/CMOS compatibility is maintained over the full supply
range. See Figure 1 for channel decode address information.
POWER SUPPLIES
The SMP18 is capable of operating with either single or dual
supplies over a voltage range of 7 to 15 volts. Based on the supply voltages chosen, V
and VSS establish the output voltage
DD
range, which is:
(VSS + 0.06 V ) ≤ V
≤ (VDD – 2 V )
OUT
Note that several specifications, including acquisition time, offset and output voltage compliance, will degrade for supply voltages of less than 7 V.
If split supplies are used, the negative supply should be bypassed
with a 0.1 µF capacitor in parallel with a 10 µF to ground. The
internal hold capacitors are connected to this supply pin, and
any noise will appear at the outputs.
In single supply applications, it is extremely important that the
V
(negative supply) pin is connected to a clean ground. The
SS
hold capacitors are internally tied to the V
(negative) rail. Any
SS
ground noise or disturbance will directly couple to the output of
the sample-and-hold degrading the signal-to-noise performance.
The analog and digital ground traces on the circuit board should
be physically separated to reduce digital switching noise from
entering the analog circuitry.
POWER SUPPLY SEQUENCING
VDD should be applied to the SMP18 before the logic input signals. The SMP18 has been designed to be immune to latchup,
but standard precautions should still be taken.
OUTPUT BUFFERS (Pins 1, 2, 4, 5, 12, 13, 14, 15)
The buffer offset specification is 10 mV; this is less than 1/2
LSB of an 8-bit DAC with 10 V full scale. The hold step (magnitude of step caused in the output voltage when switching from
sample-to-hold mode, also referred to as the pedestal error or
sample-to-hold offset) is about 4 mV with little variation over
the full output voltage range. The droop rate of a held channel
is 2 mV/s typical and 40 mV/s maximum.
The buffers are designed to drive loads connected to ground.
The outputs can source more than 20 mA over the full voltage
range but have limited current sinking capability near V
SS
. In
split supply operation, symmetrical output swings can be obtained by restricting the output range to 2 V from either supply.
On-chip SMP18 buffers eliminate potential stability problems
associated with external buffers; outputs are stable with capacitive loads up to 500 pF. However, since the SMP18’s buffer
outputs are not short circuit protected, care should be taken to
avoid shorting any output to the supplies or ground.
SIGNAL INPUT (Pin 3)
The signal input should be driven from a low impedance voltage
source such as the output of an op amp. The op amp should
have a high slew rate and fast settling time if the SMP18’s acquisition time characteristics are to be maintained. As with all
CMOS devices, all input voltages should be kept within range of
the supply rails (V
≤ VIN ≤ V
SS
) to avoid the possibility of
DD
latchup. If single supply operation is desired, op amps such as
the OP183 or AD820 that have input and output voltage compliances including ground, can be used to drive the inputs. Split
supplies, such as ±7.5 V, can be used with the SMP18.
–6–
REV. C
SMP18
APPLICATION TIPS
All unused digital inputs should be connected to logic LOW.
For analog inputs that may become temporarily disconnected, a
resistor to V
, VSS or analog ground should be used with a
DD
value ranging from 200 kΩ to 1 MΩ.
Do not apply signals to the SMP18 with power off unless the in-
put current is limited to less than 10 mA.
DIGITAL
INPUTS
ADDRESS
WR
BUS
+12V
REF02
+5V
4
AV
V
REF
DAC8228
CS
WR
ADDRESS
DECODE
+12V
17
DD
V
OA
3
V
Z
1
GND
15
516
A
B
C
DGND
INH
SMP18
V
SS
3
11
10
9
8
6
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
TYPICAL APPLICATIONS
An 8-Channel Multiplexed D/A Converter
Figure 1 illustrates a typical demultiplexing function of the
SMP18. It is used to sample-and-hold eight different output
voltages corresponding to eight different digital codes from a
D/A converter. The SMP18’s droop rate of 40 mV/s requires a
refresh once every 250 ms before the voltage drifts beyond
1/2 LSB accuracy (1 LSB of an 8-bit DAC is equivalent to
19.5 mV out of a full-scale voltage of 5 V). For a 10-bit DAC
the refresh rate must be less than 60 ms, and for a 12-bit
system, 15 ms. This implementation is very cost effective compared to using multiple DACs as the number of output channels
increases.
13
CH
0
14
CH
1
15
CH
2
12
CH
3
1
CH
4
5
CH
5
2
CH
6
4
CH
7
PIN 9CPIN 10BPIN 11APIN 6
CHANNEL DECODING
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
X
X
INH CH PIN
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
X
1
0
1
2
3
4
5
6
7
NONE
13
14
15
12
1
5
2
4
–
REV. C
V
SS
16
+12V
0.1µF
7
Figure 1. 8-Channel Multiplexed D/A Converter
–7–
SMP18
0.210 (5.33)
MAX
0.160 (4.06)
0.115 (2.93)
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
16-Pin Plastic DIP
(N-16)
0.840 (21.33)
0.745 (18.93)
16
18
PIN 1
0.022 (0.558)
0.014 (0.356)
0.100
(2.54)
BSC
9
0.280 (7.11)
0.240 (6.10)
0.060 (1.52)
0.015 (0.38)
0.070 (1.77)
0.045 (1.15)
SEATING
PLANE
16-Pin (Narrow Body)
(SO-16)
0.3937 (10.00)
0.3859 (9.80)
0.130
(3.30)
MIN
0.325 (8.25)
0.300 (7.62)
0.015 (0.381)
0.008 (0.204)
0.195 (4.95)
0.115 (2.93)
C1543a–2–10/96
0.1574 (4.00)
0.1497 (5.80)
0.0098 (0.25)
0.0040 (0.10)
SEATING
PLANE
0.177 (4.50)
0.006 (0.15)
0.002 (0.05)
SEATING
PLANE
16 9
PIN 1
0.0500
(1.27)
BSC
0.201 (5.10)
0.193 (4.90)
16 9
0.169 (4.30)
1
PIN 1
0.0118 (0.30)
0.0256
(0.65)
0.0075 (0.19)
BSC
0.2550 (6.20)
81
0.2284 (5.80)
0.0688 (1.75)
0.0532 (1.35)
0.0192 (0.49)
0.0138 (0.35)
0.0099 (0.25)
0.0075 (0.19)
16-Lead TSSOP
(RU-16)
0.256 (6.50)
0.246 (6.25)
8
0.0433
(1.10)
MAX
0.0079 (0.20)
0.0035 (0.090)
0.0196 (0.50)
0.0099 (0.25)
8°
0°
8°
0°
x 45°
0.0500 (1.27)
0.0160 (0.41)
0.028 (0.70)
0.020 (0.50)
PRINTED IN U.S.A.
–8–
REV. C
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