Page 1
SUMMIT
MICROELECTRONICS, Inc.
Nonvolatile DACPOT™ Electronic Potentiometer
With Up/Down Counter Interface
FEATURES
• Digitally Controlled Electronic Potentiometer
• 7-Bit Digital-to-Analog Converter (DAC)
– Independent Reference Inputs
– Differential Non-Linearity - +0.5LSB
– Integral Non-Linearity - +1LSB
•V
Value in EEPROM for Power-On Recall
OUT
– Equivalent to 128-Step Potentiometer
• Unity Gain Op Amp Drives ±100µA
• Simple Trimming Adjustment
– Up/Down Counter Style Operation
• Low Noise Operation
• “Clickless” Transitions between DAC Steps
• No Mechanical Wearout Problem
– 1,000,000 Stores (typical)
– 100 Year Data Retention
• Operation from +2.7V to +5.5V Supply
OVERVIEW
The SMP9317 DACPOT™ trimmer is a 7-bit nonvolatile
DAC designed to replace mechanical potentiometers.
The SMP9317 includes a unity-gain amplifier to buffer the
DAC output and enables V
The DACPOT trimmer operates over a supply voltage
range of 2.7V to 5.5V.
The SMP9317’s simple up/down counter input provides
an ideal interface for automatic test equipment to dither
and monitor the V
quick and consistent calibration of even the most sophisticated systems.
The SMP9317 is a pin-compatible performance upgrade
for other industry nonvolatile potentiometers. The
SMP9317 offers higher resolution than these devices and
provides ‘clickless’ transitions of V
SMP9317
to swing from rail to rail.
OUT
voltage. This interface allows for
OUT
.
OUT
• Ultra-Low Power, 0.5mW max at +5V
FUNCTIONAL BLOCK DIAGRAM
7-bit E2 PROM
UP/DN
INC
CS
Counter
&
Write
Control
7-bit
Data
Register
V
DD
7-bit DAC
-
+
AMP
V
V
H
OUT
V
L
GND
2031 ILL2.0
SUMMIT MICROELECTRONICS, Inc. • 300 Orchard City Drive, Suite 131 • Campbell, CA 95008 • Telephone 408-378-6461 • Fax 408-378-6586 • www.summitmicro.com
© SUMMIT MICROELECTRONICS, Inc. 1998
2031-04 12/4/98
1
Characteristics subject to change without notice
Page 2
SMP9317
PIN NAMES
Symbol Description
INC Increment Input, High to Low
Edge Trigger
UP/DN Up/Down Input controlling relative
V
movement
OUT
V
H
V+ reference input
GND Analog and Digital Ground
V
OUT
V
L
Trimmed Voltage Output
V- reference input
CS Active low chip select input
V
DD
Supply Voltage (2.7V to 5.5V)
Analog Section
The SMP9317 is a 7-bit, voltage output digital-to-analog
converter (DAC). The DAC consists of a resistor network
that converts a 7-bit value into equivalent analog output
voltages in proportion to the applied reference voltage.
Reference Inputs
The voltage differential between the VL and VH inputs
sets the full-scale output voltage range. VL must be equal
to or greater than ground (i.e. a positive voltage). VH must
be greater than VL and less than or equal to VDD. See
table on page 3 for guaranteed operating limits.
Output Buffer Amplifier
The voltage output is from a precision unity-gain follower
that can slew up to 1V/µs.
Digital Interface
The interface is designed to emulate a simple up/down
counter, but instead of a parallel count output, a
ratiometric voltage output is provided.
Chip Select (
CSCS
CS) is an active low input. Whenever CS is
CSCS
high the SMP9317 is in standby mode and consumes the
least power. This mode is equivalent to a potentiometer
that is adjusted to the required setting. When CS is low
the SMP9317 will recognize transitions on the INC input
and will move the V
either toward the VH reference or
OUT
toward the VL reference depending upon the state of the
UP/DN input.
The host may exit an adjustment routine in two ways:
deselecting the SMP9317 while INC is low will not perform a store operation (a subsequent power cycle will
recall the original data); deselecting the SMP9317 while
INC is high will store the current V
setting into non-
OUT
volatile memory.
PINOUT
INC
UP/DN
V
GND
Increment (
1
2
3
H
4
INCINC
INC) is an edge triggered input. Whenever
INCINC
8
7
6
5
2031 ILL1.0
V
CS
V
V
DD
L
OUT
CS is low and a high to low transition occurs on the INC
input, the V
voltage will either move toward VH or V
OUT
depending upon the state of the UP/DN input.
UP/Down (UP/
DNDN
DN) is an input that will determine the V
DNDN
OUT
movement relative to VH and VL. When CS is low, UP/DN
is high and there is a high to low transition on INC, the
V
voltage will move (1/128th x VH-VL) toward VH.
OUT
When CS and UP/DN are low, and there is a high to low
transition on INC, the V
will move (1/128th x VH-VL)
OUT
toward VL.
Power–Up/Power–Down Conditions
On power–up the SMP9317 loads the value of EEPROM
memory into the wiper position register. The value in the
register is changed using the CS, INC, and UP/DN pins.
The new data in the register will be lost at power-down
unless CS was brought high, with INC high, to initiate a
store operation after the last increment or decrement. On
the next device power–up, the value of EEPROM memory
will be loaded into the wiper position register. During
power-up the SMP9317 is write-protected in two ways:
1) A power-on reset, that trips at approximately 2.5V,
holds CS and INC high internally.
2) Resistor pull-ups on all logic inputs prevent data
change if the inputs are floating.
Data Retention
The SMP9317 is guaranteed to perform at least
1,000,000 writes to EEPROM before a wear–out condition can occur. After EEPROM wearout, the SMP9317
continues to function as a volatile digital-potentiometer.
The wiper position can be changed during powered
conditions using the digital interface. However, on power–
up the wiper–position will be indeterminate.
On shipment from the factory, Summit Microelectronics
does not specify any EEPROM memory value. The value
must be set by the customer as needed.
L
2031-04 12/4/98
2
Page 3
SMP9317
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias -55°C to +125°C
Storage Temperature -65°C to +150°C
Voltage on pins with reference to GND:
Analog Inputs -0.5V to VDD+.5V
Digital Inputs -0.5V to VDD+.5V
Analog Outputs -0.5V to VDD+.5V
Digital Outputs -0.5V to VDD+.5V
Lead Solder Temperature (10 secs) 300°C
RECOMMENDED OPERATING CONDITIONS
Condition Min Max
Temperature -40°C +85°C
V
DD
+2.7V +5.5V
DAC DC ELECTRICAL CHARACTERISTICS
VDD = +2.7V to +5.5V, V
Symbol Parameter Conditions Min. Typ. Max. Units
Accuracy
INL Integral Non-Linearity I
= VDD, V
refH
= 0V, TA = -40°C to +85°C, unless specified otherwise
refL
= 50µA, TR = C - 0.6 ±1 LSB
LOAD
*COMMENT
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to
the device. These are stress ratings only, and
functional operation of the device at these or any
other conditions outside those listed in the operation sections of this specification is not implied.
Exposure to any absolute maximum rating for
extended periods may affect device performance
and reliability.
2031 PGM T1.0
TR = I - 0.6 ±1 LSB
References
Analog
Output
I
= 100µA, TR =C - 1.2 - LSB
LOAD
TR = I - 1.2 - LSB
DNL Differential Non-Linearity I
= 50µA, TR = C - 0.25 ±0.5 LSB
LOAD
TR = I - 0.25 ±0.5 LSB
I
= 100µA, TR = C - 0.5 - LSB
LOAD
TR = I - 0.5 - LSB
V
H
V
L
R
IN
TCR
G
EFS
V
OUT
TCV
I
L
R
OUT
V
Input Voltage 2.5 - V
refH
V
Input Voltage VH ≥ V
refL
V
to V
refH
Temperature Coefficient V
IN
of R
IN
Resistance - 38K - Ω
refL
refH
L
to V
refL
Gnd - VDD-2.5 V
- 700 - ppm/°C
Full-Scale Gain Error DATA = 7F - - ±1 LSB
ZS Zero-Scale Output Voltage DATA = 00 0 20 mV
OUTVOUT
Temperature VDD = +5, I
Coefficient, note 3 V
Amplifier Output Load Current
Amplifier Output Resistance
= +5V, V
refH
IL = 100µA +5V - 10 Ω
= 50µA,
LOAD
= 0V - - 200 µV/°C
refL
100 µA
+3V - 20 Ω
PSRR Power Supply Rejection I
= 10µA - - 1 LSB/V
LOAD
DD
V
e
N
Amplifier Output Noise f = 1KHz, VDD = +5V - 90 - nV/ H
THD Total Harmonic Distortion VIN = 1V rms, f = 1KHz - 0.08 - %
BW Bandwidth - 3dB V
= 100mV rms - 1,000 - kHz
IN
2031 PGM T3.2
3
2031-04 12/4/98
Z
Page 4
SMP9317
RELIABILITY CHARACTERISTICS (over recommended operating conditions unless otherwise specified)
Symbol Parameter Min Max Unit Test Method
V
ZAP
I
LTH
T
DR
N
END
ESD Susceptibility 2000 V MS-883, TM 3015
Latch-Up 100 mA JEDEC Standard 17
Data Retention 100 Years MS-883, TM 1008
Endurance 1,000,000 Stores MS-883, TM 1033
2031 PGM T2.0
DC ELECTRICAL CHARACTERISTICS
VDD = +2.7V to +5.5V, VH = VDD, VL = 0V, TA = -40°C to +85°C, Unless otherwise specified
Symbol Parameter Conditions Min Typ Max Units
I
DD
Supply Current CS = V
IL
to V
IH
1.0 mA
during store, note 1 W/INC HI
I
SB
I
IH
I
IL
V
IH
V
IL
Notes:
1. IDD is the supply current drawn while the EEPROM is being updated. IDD does not include the current that flows through the Reference
resistor chain.
2. CS, UP/DN and INC have internal pull-up resistors of approximately 200kΩ. When the input is pulled to ground the resulting output
current will be VDD/200kΩ.
3. TCV
OUT
Supply Standby Current CS = V
Input Leakage Current VIN = V
IH
DD
100 µA
Input Leakage Current, note 2 VIN = 0V -25 µA
High Level Input Voltage 2 V
Low Level Input Voltage VDD ≥ 4.5V 0 0.8 V
is guaranteed but not tested.
10 µA
DD
2031 PGM T4.1
V
2031-04 12/4/98
4
Page 5
OPERATIONAL TRUTH TABLE
SMP9317
INCINC
INC
INCINC
HITOLO L H V
HITOLO L L V
HLO
LLO
CSCS
CS UP/
CSCS
HI X Store Setting
TO
HI X Maintain Setting, NO Store
TO
DNDN
DN Operation
DNDN
toward V
OUT
toward V
OUT
H
L
X H X Standby, note 1
Notes: 1. The Standby or operating current will be lowest with INC and UP/DN pins at H as there are weak internal pull-ups that draw current
when connected LO.
2031 PGM T5.1
AC TIMING CHARACTERISTICS
Symbol Parameter Min Max Units
t
CLIL
t
IHDC
t
DCIL
t
IL
t
IH
t
IHCH
t
WP
t
ILVOUT
CS to INC Setup 100 ns
INC High to UP/DN Change 100 ns
UP/DN to INC Setup 100 ns
INC Low Period 200 ns
INC High Period 200 ns
INC Inactive to CS Inactive 100 ns
Write Cycle Time 5 ms
INC to V
Delay 5 µs
OUT
2031 PGM T6.0
CS
INC
UP/DN
V
OUT
t
CLIL
t
IL
t
IHDC
t
ILVOUT
t
IH
t
DCIL
AC TIMING DIAGRAM
5
t
IHCH
t
WP
2031 ILL3.1
2031-04 12/4/98
Page 6
8 Pin SOIC (Type S) Package JEDEC (150 mil body width)
.050 (1.27) TYP.
.157 (4.00)
.150 (3.80)
.275 (6.99) TYP.
.050 (1.270) TYP.
8 Places
SMP9317
1
.196 (5.00)
.189 (4.80)
.061 (1.75)
.053 (1.35)
.0192 (.49)
.0138 (.35)
ORDERING INFORMATION
Base Part Number
.0098 (.25)
.004 (.127)
.05 (1.27) TYP.
FOOTPRINT
.035 (.90)
.016 (.40)
SMP9317 S
.030 (.762) TYP.
8 Places
.020 (.50)
.010 (.25)
.244 (6.20)
.228 (5.80)
8pn JEDEC SOIC ILL.2
Package
S = 8 Pin SOIC
2031 ILL4.0
x45°
NOTICE
SUMMIT Microelectronics, Inc. reserves the right to make changes to the products contained in this publication in order to improve
design, performance or reliability. SUMMIT Microelectronics, Inc. assumes no responsibility for the use of any circuits described
herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent
infringement. Charts and schedules contained herein reflect representative operating parameters, and may vary depending upon
a user’s specific application. While the information in this publication has been carefully checked, SUMMIT Microelectronics, Inc.
shall not be liable for any damages arising as a result of any error or omission.
SUMMIT Microelectronics, Inc. does not recommend the use of any of its products in life support applications where the failure or
malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety
or effectiveness. Products are not authorized for use in such applications unless SUMMIT Microelectronics, Inc. receives written
assurances, to its satisfaction, that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; and
(c) potential liability of SUMMIT Microelectronics, Inc. is adequately protected under the circumstances.
© Copyright 1998 SUMMIT Microelectronics, Inc.
2031-04 12/4/98
6
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