Datasheet SL74HC534D, SL74HC534N Datasheet (SLS)

SL74HC534

Semiconductor

Octal 3-State Inverting D Flip-Flop

High-Performance Silicon-Gate CMOS

The SL74HC534 is identical in pinout to the LS/ALS534. The device
inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LS/ALSTTL outputs.

Data meeting the setup time is clocked, in inverted form, to the
outputs with the rising edge of the Clock. The Output Enable input
does not affect the states of the flip -flops, but when Output Enable is
high, the outputs are forced to the high impedance state. Thus, data
may be stored even when the outputs are not enabled.

• Outputs Directly Interface to CMOS, NMOS, and TTL

• Operating Voltage Range: 2.0 to 6.0 V

• Low Input Current: 1.0 µA

• High Noise Immunity Characteristic of CMOS Devices

TA = -55° to 125° C for all packages

ORDERING INFORMATION

SL74HC534N Plastic

SL74HC534D SOIC

LOGIC DIAGRAM

PIN 20=VCC

PIN 10 = GND

PIN ASSIGNMENT

FUNCTION TABLE

Inputs Output

Output

Enable

L H L
L L H

Clock D Q

L L,H, X no

change

H X X Z

X = don’t care
Z = high impedance

System Logic

SLS

SL74HC534

Semiconductor

MAXIMUM RATINGS*

Symbol Parameter Value Unit

VCC DC Supply Voltage (Referenced to GND) -0.5 to +7.0 V

VIN DC Input Voltage (Referenced to GND) -1.5 to VCC +1.5 V

V

DC Output Voltage (Referenced to GND) -0.5 to VCC +0.5 V

OUT

IIN DC Input Current, per Pin ±20 mA

I

DC Output Current, per Pin ±35 mA

OUT

ICC DC Supply Current, VCC and GND Pins ±75 mA

PD Power Dissipation in Still Air, Plastic DIP+

SOIC Pack age+

750
500

Tstg Storage Temperature -65 to +150 °C

TL Lead Temperature, 1 mm from Case for 10 Seconds

260 °C

(Plastic DIP or SOIC Package)

*

Maximum Ratings are those values beyond which damage to the device may occur.

Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C

SOIC Package: : - 7 mW/°C from 65° to 125°C

RECOMMENDED OPERATING CONDITIONS

Symbol Parameter Min Max Unit

VCC DC Supply Voltage (Referenced to GND) 2.0 6.0 V

VIN, V

DC Input Voltage, Output Voltage (Referenced to GND) 0 VCC V

OUT

TA Operating Temperature, All Package Types -55 +125 °C

tr, tf Input Rise and Fall Time (Figure 1) VCC =2.0 V

VCC =4.5 V
V

=6.0 V

CC

0
0
0

1000

500
400

mW

ns

This device contains protection circuitry to guard against damage due to high static voltages or electric
fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, VIN and V
GND≤(VIN or V

OUT

)≤VCC.

should be constrained to the range

OUT

Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC).
Unused outputs must be left open.

System Logic

SLS

SL74HC534

Semiconductor

DC ELECTRICAL CHARACTERISTICS(Voltages Referenced to GND)

VCC Guaranteed Limit

Symbol Parameter Test Conditions V 25 °C

to

-55°C

VIH Minimum High-Level

Input Voltage

VIL Maximum L ow -Level

Input Voltage

VOH Minimum High-Level

Output Voltage

VIN=VIH or VIL

VOL Maximum Low -Level

Output Voltage

VIN= VIL or VIH

IIN Maximum Input

V

=0.1 V or VCC-0.1 V

OUT

I

≤ 20 µA

OUT

V

=0.1 V or VCC-0.1 V

OUT

I

 ≤ 20 µA

OUT

VIN=VIH or VIL

I

 ≤ 20 µA

OUT

I

 ≤ 6.0 mA

OUT

I

 ≤ 7.8 mA

OUT

VIN= VIL or VIH

I

 ≤ 20 µA

OUT

I

 ≤ 6.0 mA

OUT

I

 ≤7.8 mA

OUT

2.0

4.5

6.0

2.0

4.5

6.0

2.0

4.5

6.0

4.5

6.0

2.0

4.5

6.0

4.5

6.0

1.5

3.15

4.2

0.5

1.35

1.8

1.9

4.4

5.9

3.98

5.48

0.1

0.1

0.1

0.26

0.26

VIN=VCC or GND 6.0 ±0.1 ±1.0 ±1.0 µA

Leakage Current

≤85

°C

1.5

3.15

4.2

0.5

1.35

1.8

1.9

4.4

5.9

3.84

5.34

0.1

0.1

0.1

0.33

0.33

≤125

°C

1.5

3.15

4.2

0.5

1.35

1.8

1.9

4.4

5.9

3.7

5.2

0.1

0.1

0.1

0.4

0.4

Unit

V

V

V

V

IOZ Maximum Three State

Leakage Current

ICC Maximum Quiescent

Supply Current
(per Package)

Output in High-Impedance
State
VIN =VIH or V
V

= VCC or GND

OUT

IL

VIN=VCC or GND
I

=0µA

OUT

6.0 ±0.5 ±5.0 ±10 µA

6.0 4.0 40 160 µA

System Logic

SLS

SL74HC534

Semiconductor

AC ELECTRICAL CHARACTERISTICS(C

=50pF,Input tr=tf=6.0 ns)

L

VCC Guaranteed Limit

Symbol Parameter V 25 °C to

≤85°C ≤125°C Unit

-55°C

f

Maximum Clock Frequency (50% Duty Cycle)

max

(Figures 1 and 4)

t

, t

PLH

Maximum Propagation Delay, Clock to Q (Figures

PHL

1 and 4)

t

, t

PLZ

Maximum Propagation Delay, Output Enable to Q

PHZ

(Figures 2 and 5)

t

, t

PZH

Maximum Propagation Delay, Output Enable to Q

PZL

(Figures 2 and 5)

t

, t

TLH

Maximum Output Transition Time, Any Output

THL

(Figures 1 and 4)

2.0

4.5

6.0

2.0

4.5

6.0

2.0

4.5

6.0

2.0

4.5

6.0

2.0

4.5

6.0

6.0
30
35

125

25
21

150

30
26

150

30
26

75
15
13

5.0
24
28

155

31
26

190

38
33

190

38
33

95
19
16

4.0
20
24

190

38
32

225

45
38

225

45
38

110

22
19

CIN Maximum Input Capacitance - 10 10 10 pF

MHz

ns

ns

ns

ns

C

Maximum Three-State Output Capacitance

OUT

- 15 15 15 pF

(Output in High-Impedance State)

Power Dissipation Capacitance (Per Flip-Flop) Typical @25°C,VCC=5.0 V

CPD Used to determine the no-load dynamic power

consumption:
PD=CPDV

2

f+ICCVCC

CC

34 pF

TIMING REQUIREMENTS (C

=50pF,Input tr=tf=6.0 ns)

L

VCC Guaranteed Limit

Symbol Parameter V 25 °C to

≤85°C ≤125°C Unit

-55°C

tSU Minimum Setup Time, Data to

Clock (Figure 3)

th Minimum Hold Time, Clock to

Data (Figure 3)

tw Minimum Pulse Width, Clock

(Figure 1)

2.0

4.5

6.0

2.0

4.5

6.0

2.0

4.5

6.0

50
10

9
5

5
5

60
12
10

65
13
11

5
5
5

75
15
13

75
15
13

5
5
5

90
18
15

ns

ns

ns

t

Maximum Input Rise and Fall

r, tf

Times (Figure 1)

System Logic

SLS

2.0

4.5

6.0

1000

500
400

1000

500
400

1000

500
400

ns

SL74HC534

Semiconductor

Figure 1. Switching Waveforms Figure 2. Switching Waveforms

Figure 3. Switching Waveforms

Figure 4. Test Circuit Figure 5. Test Circuit

EXPANDED LOGIC DIAGRAM

SLS

System Logic