Datasheet SL74HC299D, SL74HC299N Datasheet (SLS)

Semiconductor

8-Bit Bidirectional Universal Shift Register with Parallel I/O

High-Performance Silicon-Gate CMOS

The SL74HC299 is identical in pinout to the LS/ALS299. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALSTTL outputs.

The SL74HC299 features a multiplexed parallel input/output data port to achieve full 8-bit handling in a 20 pin package. Due to the large output drive capability and the 3-state feature, this device is ideally suited for interface with bus lines in a bus-oriented system.

Two Mode-Select inputs and two Output Enable inputs are used to choose the mode of operation as listed in the Function Table. Synchronous parallel loading is accomplished by taking both ModeSelect lines, S1 and S2, high. This places the outputs in the highimpedance state, which permits data applied to the data port to be clocked into the register. Reading out of the register can be accomplished when the outputs are enabled. The active-low asynchronous Reset overrides all other inputs.

• Outputs Directly Interface to CMOS, NMOS, and TTL

• Operating Voltage Range: 2.0 to 6.0 V

• Low Input Current: 1.0 µA

• High Noise Immunity Characteristic of CMOS Devices

SL74HC299

ORDERING INFORMATION

SL74HC299N Plastic

SL74HC299D SOIC

TA = -55° to 125° C for all packages

PIN ASSIGNMENT

LOGIC DIAGRAM

PIN 20=VCC

PIN 10 = GND

SLS

System Logic

SL74HC299

Semiconductor

MAXIMUM RATINGS*

Symbol Parameter Value Unit

VCC DC Supply Voltage (Referenced to GND) -0.5 to +7.0 V VIN DC Input Voltage (Referenced to GND) -1.5 to VCC +1.5 V

V

DC Output Voltage (Referenced to GND) -0.5 to VCC +0.5 V

OUT

IIN DC Input Current, per Pin ±20 mA

I

DC Output Current, per Pin ±35 mA

OUT

ICC DC Supply Current, VCC and GND Pins ±75 mA PD Power Dissipation in Still Ai r, Plastic DIP+

SOIC Package+

750 500

Tstg Storage Temperature -65 to +150 °C

TL Lead Temperature, 1 mm from Case for 10 Seconds

260 °C

(Plastic DIP or SOIC Package)

*

Maximum Ratings are those values beyond whi ch damage to the device may occur.

Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C

SOIC Package: : - 7 mW/°C from 65° to 125°C

RECOMMENDED OPERATING CONDITIONS

Symbol Parameter Min Max Unit

VCC DC Supply Voltage (Referenced to GND) 2.0 6.0 V

VIN, V

DC Input Voltage, Output Voltage (Referenced to GND) 0 VCC V

OUT

TA Operating Temperature, All Package Types -55 +125 °C

tr, tf Input Rise and Fall Time (Figure 1) VCC =2.0 V

VCC =4.5 V V

=6.0 V

CC

0

1000 0 0

500 400

mW

ns

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and V GND≤(VIN or V

OUT

)≤VCC.

should be constrained to the range

OUT

Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. I/O pins must be connected to a properly terminated line or bus.

System Logic

SLS

SL74HC299

Semiconductor

DC ELECTRICAL CHARACTERISTICS(Voltages Referenced to GND)

VCC Guaranteed Limit

Symbol Parameter Test Conditions V 25 °C

to

-55°C

VIH Minimum High-Level

Input Voltage

VIL Maximum Low -Level

Input Voltage

VOH Minimum High-Level

Output Voltage

VIN=VIH or VIL

VOL Maximum Low -Level

Output Voltage

VIN=VIH or VIL

IIN Maximum Input

V

=0.1 V or VCC-0.1 V

OUT

I

≤ 20 µA

OUT

V

=0.1 V or VCC-0.1 V

OUT

I

 ≤ 20 µA

OUT

VIN=VIH or VIL

I

 ≤ 20 µA

OUT

I

 ≤ 6.0 mA (P/Q)

OUT

I

 ≤ 7.8 mA (P/Q)

OUT

I

 ≤ 4.0 mA (Q’)

OUT

I

 ≤ 5.2 mA (Q’)

OUT

VIN= VIL or VIH

I

 ≤ 20 µA

OUT

I

 ≤ 6.0 mA (P/Q)

OUT

I

 ≤ 7.8 mA (P/Q)

OUT

I

 ≤ 4.0 mA (Q’)

OUT

I

 ≤ 5.2 mA (Q’)

OUT

2.0

4.5

6.0

2.0

4.5

6.0

2.0

4.5

6.0

4.5

6.0

4.5

6.0

2.0

4.5

6.0

4.5

6.0

4.5

6.0

1.5

3.15

4.2

0.3

0.9

1.2

1.9

4.4

5.9

3.98

5.48

3.98

5.48

0.1

0.26

VIN=VCC or GND 6.0 ±0.1 ±1.0 ±1.0 µA

Leakage Current

≤85

°C

1.5

3.15

4.2

0.3

0.9

1.2

1.9

4.4

5.9

3.84

5.34

3.84

5.34

0.1

0.33

≤125

°C

1.5

3.15

4.2

0.3

0.9

1.2

1.9

4.4

5.9

3.7

5.2

3.7

5.2

0.1

0.4

Unit

V

IOZ Maximum Three-State

Leakage Current (QA thru QH)

ICC Maximum Quiescent

Supply Current (per Package)

System Logic

SLS

Output in High-Impedance State VIN= V V

IL

OUT=VCC

or V

IH

or GND

VIN=VCC or GND I

=0µA

OUT

6.0 ±0.5 ±5.0 ±10 µA

6.0 8.0 80 160 µA

SL74HC299

Semiconductor

AC ELECTRICAL CHARACTERISTICS(C

=50pF,Input tr=tf=6.0 ns)

L

VCC Guaranteed Limit

Symbol Parameter V 25 °C to

≤85°C ≤125°C Unit

-55°C

f

Maximum Clock Frequency (50% Duty Cycle)

max

(Figures 1 and 5)

t

, t

PLH

Maximum Propagation Delay, Clock to QA’ or QH’

PHL

(Figures 1 and 5)

t

, t

PLH

Maximum Propagation Delay, Clock to QA thru QH

PHL

(Figures 1 and 5)

t

Maximum Propagation Delay, Reset to QA’ or QH’

PHL

(Figures 2 and 5)

t

Maximum Propagation Delay, Reset to QA thru QH

PHL

(Figures 2 and 5)

t

, t

PLZ

Maximum Propagation Delay , OE1, OE2, S1, or S2

PHZ

to QA thru QH (Figures 3 and 6)

2.0

4.5

6.0

2.0

4.5

6.0

2.0

4.5

6.0

2.0

4.5

6.0

2.0

4.5

6.0

2.0

4.5

6.0

5.0 25 29

170

34 29

160

32 27

175

35 30

190

38 32

150

30 26

4.0 20 24

215

43 37

200

40 34

220

44 37

240

48 41

190

38 33

3.4 17 20

255

51 43

240

48 41

265

53 45

285

57 48

225

45 38

MHz

ns

t

, t

t

PZL

TLH

Maximum Propagation Delay , OE1, OE2, S1, or S2

PZH

to QA thru QH (Figures 3 and 6)

, t

Maximum Output Transition Time, QA thru Q

THL

(Figures 1 and 5)

, t

Maximum Output Transition Time, QA’ thru QH’

THL

(Figures 1 and 5)

H

2.0

4.5

6.0

2.0

4.5

6.0

2.0

4.5

6.0

150

30 26

60 12 10

75 15 13

190

38 33

75 15 13

95 19 16

225

45 38

90 18 15

110

22 19

CIN Maximum Input Capacitance) - 10 10 10 pF

C

Maximum Three-State I/O Capacitance

OUT

- 15 15 15 pF

(I/O in High-Impedance State), QA thru QH

Power Dissipation Capacitance (Per Package),

Typical @25°C,VCC=5.0 V

Output Enable

CPD Used to determine the no-load dynamic power

consumption: PD=CPDV

2

f+ICCVCC

CC

240 pF

ns

SLS

System Logic

SL74HC299

Semiconductor

TIMING REQUIREMENTS(C

VCC Guaranteed Limit

Symbol Parameter V 25 °C to-55°C ≤85°C ≤125°C Unit

tsu Minimum Setup Time, Mode Select S1

or S2 to Clock (Figure 4)

tsu Minimum Setup Time, Data Inputs SA,

SH, PA thru PH to Clock (Figure 4)

th Minimum Hold Time, Clock to Mode

Select S1 or S2 (Figure 4)

th Minimum Hold Time, Clock to Data

Inputs, SA, SH, PA thru PH (Figure 4)

t

Minimum Recovery Time, Reset

rec

Inactive to Clock (Figure 2)

tw Minimum Pulse Width, Clock (Figure

1)

=50pF,Input tr=tf=6.0 ns)

L

2.0

4.5

6.0

2.0

4.5

6.0

2.0

4.5

6.0

2.0

4.5

6.0

2.0

4.5

6.0

2.0

4.5

6.0

100

20 17

100

20 17

120

24 20

5 5 5

50 10

9

80 16 14

125

25 21

125

25 21

150

30 26

5 5 5

65 13 11

100

20 17

150

30 26

150

30 26

180

36 31

5 5 5

75 15 13

120

24 20

ns

tw Minimum Pulse Width, Reset (Figure

2)

tr, tf Maximum Input Rise and Fall Times

(Figure 1)

2.0

4.5

6.0

2.0

4.5

6.0

80 16 14

1000

500 400

100

20 17

1000

500 400

120

24 20

1000

500 400

ns

SLS

System Logic

SL74HC299

Semiconductor

FUNCTION TABLE

Inputs Response

Mode Reset Mode

Select

S2 S1 OE1 OE2 DA DH

Reset L X L L L X X X L L L L L L L L L L

L L X L L X X X L L L L L L L L L L L H H X X X X X QA through QH=Z L L

Shift

Right

H L H X H D X Shift Right: QA through QH=Z;

H L H L L D X Shift Right: DA FA =QA;

Shift

Left

H H L X H X D Shift Left: QA through QH=Z;

H H L L L X D Shift Left: DH FH =QH;

Parallel

Load

H L H H X D X Shift Right: QA through QH=Z;

H H L H X X D Shift Left: QA through QH=Z;

H H H X X X X Parallel Load:P

Output

Enables

Clock Serial

Inputs

PA/

PB/

PC/

PD/

QA

QB

QC

QD

DA FA; FA FB; etc

F

FB =QB; etc

A

DH FH; FH FG; etc

FH FG =QG; etc

PE/

PF/

PG/

PH/

QE

QF

QG

QH

FN PA PH

N

QA’ QH’

D QG

QB D

Hold H L L H X X X X Hold: QA through QH=Z; FN=FN PA PH

H L L X H X X X Hold: QA through QH=Z; FN=FN PA PH H L L L L X X X Hold: QN =QH PA PH

Z = high impedance D = data on serial input F = flip-flop (see Logic Diagram) When one or both output controls are high the eight input/output terminals are disabled to the high impedance state; however, sequential operation or clearing of the register is not affected.

System Logic

SLS

SL74HC299

Semiconductor

Figure 1. Switching Waveforms Figure 2. Switching Waveforms

Figure 3a. Switching Waveforms Figure 3b. Switching Waveforms

Figure 4. Switching Waveforms Figure 5. Test Circuit

SLS

Figure 6. Test Circuit

System Logic

SL74HC299

Semiconductor

EXPANDED LOGIC DIAGRAM

SLS

System Logic