Datasheet SL74HC4094D, SL74HC4094N Datasheet (SLS)

SL74HC4094

Semiconductor

8-Bit Serial-Input Shift Register With Latched
3-State Outputs

High-Performance Silicon-Gate CMOS

The SL74HC4094 is identical in pinout to the LS/ALS4094. The
device inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LS/ALSTTL outputs.

This device consists of an 8-bit shift register and 8-bit D-type latch
with three-state parallel outputs. Data is shifted serially through the
shift register on the positive going transition of the clock input signal.
The output of the last stage SQH can be used to cascade several
devices.

Data on the SQH output is transferred to a second output (SQH’) on
the following negative transition of the clock input signal. The data of
each stage of the shift register is provided with a latch, which latches
data on the negative going transition of the Strobe input signal. When
the Strobe input is held high, data propagates through the latch to a 3­state output buffer.

This buffer is enabled when Output Enable input is taken high.

• Outputs Directly Interface to CMOS, NMOS, and TTL

• Operating Voltage Range: 2.0 to 6.0 V

• Low Input Current: 1.0 µA

• High Noise Immunity Characteristic of CMOS Devices

ORDERING INFORMATION

SL74HC4094N Plastic

SL74HC4094D SOIC

TA = -55° to 125° C for all packages

PIN ASSIGNMENT

LOGIC DIAGRAM

FUNCTION TABLE

Inputs Parallel

Outputs

Clock Output

PIN 16 =VCC

PIN 8 = GND

NC = No Change
Z = high impedance
X = don’t care

Enable
L X X Z Z Q6 NC
L X X Z Z NC SQH
H L X NC NC Q6 NC
H H L L Q
H H H H Q
H X X NC NC NC SQH

Strobe A QA QN SQH SQH’

Serial

Outputs

Q6 NC

N-1

Q6 NC

N-1

SLS

System Logic

SL74HC4094

Semiconductor

MAXIMUM RATINGS*

Symbol Parameter Value Unit

VCC DC Supply Voltage (Referenced to GND) -0.5 to +7.0 V
VIN DC Input Voltage (Referenced to GND) -1.5 to VCC +1.5 V

V

DC Output Voltage (Referenced to GND) -0.5 to VCC +0.5 V

OUT

IIN DC Input Current, per Pin ±20 mA

I

DC Output Current, per Pin ±25 mA

OUT

ICC DC Supply Current, VCC and GND Pins ±50 mA
PD Power Dissipation in Still Air, Plastic DIP+

SOIC Package+

750
500

Tstg Storage Temperature -65 to +150 °C

TL Lead Temperature, 1 mm from Case for 10 Seconds

260 °C

(Plastic DIP or SOIC Package)

*

Maximum Ratings are those values beyond which damage to the device may occur.

Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C

SOIC Package: : - 7 mW/°C from 65° to 125°C

RECOMMENDED OPERATING CONDITIONS

Symbol Parameter Min Max Unit

VCC DC Supply Voltage (Referenced to GND) 2.0 6.0 V

VIN, V

DC Input Voltage, Output Voltage (Referenced to GND) 0 VCC V

OUT

TA Operating Temperature, All Package Types -55 +125 °C

tr, tf Input Rise and Fall Time (Figure 1) VCC =2.0 V

VCC =4.5 V
V

=6.0 V

CC

0
0
0

1000

500
400

mW

ns

This device contains protection circuitry to guard against damage due to high static voltages or electric
fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, VIN and V
GND≤(VIN or V

OUT

)≤VCC.

should be constrained to the range

OUT

Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC).
Unused outputs must be left open.

System Logic

SLS

SL74HC4094

Semiconductor

DC ELECTRICAL CHARACTERISTICS(Voltages Referenced to GND)

VCC Guaranteed Limit

Symbol Parameter Test Conditions V 25 °C

to

-55°C

VIH Minimum High-Level

Input Voltage

VIL Maximum Low -Level

Input Voltage

VOH Minimum High-Level

Output Voltage

VIN= VIH or VIL

VOL Maximum Low -Level

Output Voltage

VIN= VIH or VIL

IIN Maximum Input

V

= 0.1 V or VCC-0.1 V

OUT

I

≤ 20 µA

OUT

V

=0.1 V or VCC-0.1 V

OUT

I

 ≤ 20 µA

OUT

VIN=VIH or VIL

I

 ≤ 20 µA

OUT

I

 ≤ 4.0 mA

OUT

I

 ≤ 5.2 mA

OUT

VIN=VIH or VIL

I

 ≤ 20 µA

OUT

I

 ≤ 4.0 mA

OUT

I

 ≤ 5.2 mA

OUT

2.0

4.5

6.0

2.0

4.5

6.0

2.0

4.5

6.0

4.5

6.0

2.0

4.5

6.0

4.5

6.0

1.5

3.15

4.2

0.5

1.35

1.8

1.9

4.4

5.9

3.98

5.48

0.1

0.1

0.1

0.26

0.26

VIN=VCC or GND 6.0 ±0.1 ±1.0 ±1.0 µA

Leakage Current

≤85

°C

1.5

3.15

4.2

0.5

1.35

1.8

1.9

4.4

5.9

3.84

5.34

0.1

0.1

0.1

0.33

0.33

≤125

°C

1.5

3.15

4.2

0.5

1.35

1.8

1.9

4.4

5.9

3.7

5.2

0.1

0.1

0.1

0.4

0.4

Unit

V

V

V

V

IOZ Maximum Three-State

Leakage Current

ICC Maximum Quiescent

Supply Current
(per Package)

System Logic

SLS

Output in High-Impedance
State
VIN= VIL or VIH
V

OUT=VCC

or GND

VIN=VCC or GND
I

=0µA

OUT

6.0 ±0.5 ±5.0 ±10 µA

6.0 4.0 40 160 µA

SL74HC4094

Semiconductor

AC ELECTRICAL CHARACTERISTICS(C

VCC Guaranteed Limit

=50pF,Input tr=tf=6.0 ns)

L

Symbol Parameter V 25 °C to

≤85°C ≤125°C Unit

-55°C

f

Maximum Clock Frequency (50% Duty Cycle)

max

(Figures 1 and 5)

t

, t

PLH

Maximum Propagation Delay, Clock to SQH

PHL

(Figures 1 and 5)

t

, t

PLH

Maximum Propagation Delay, Clock to QA-QH

PHL

(Figures 2 and 5)

t

, t

PLZ

Maximum Propagation Delay ,Output Enable to

PHZ

QA-QH (Figures 3 and 6)

t

, t

PZL

Maximum Propagation Delay ,Output Enable to

PZH

QA-QH (Figures 3 and 6)

2.0

4.5

6.0

2.0

4.5

6.0

2.0

4.5

6.0

2.0

4.5

6.0

2.0

4.5

6.0

6
30
35

150

30
26

195

40
33

125

25
21

175

35
30

5
25
28

190

38
33

245

50
42

155

31
26

220

44
37

4
20
23

225

45
38

295

60
50

190

38
32

265

53
45

CIN Maximum Input Capacitance - 10 10 10 pF

C

Maximum Three-State Output Capacitance

OUT

- 15 15 15 pF

(Output in High-Impedance State), QA-QH

Power Dissipation Capacitance (Per Package) Typical @25°C,VCC=5.0 V

MHz

ns

ns

ns

ns

CPD Used to determine the no-load dynamic power

consumption: PD=CPDV

TIMING REQUIREMENTS(C

2

f+ICCVCC

CC

=50pF,Input tr=tf=6.0 ns)

L

300 pF

VCC Guaranteed Limit

Symbol Parameter V 25 °C to

≤85°C ≤125°C Unit

-55°C

tsu Minimum Setup Time, Serial Data

Input A to Clock (Figure 4)

th Minimum Hold Time, Clock to Data

Input A (Figure 4)

tw Minimum Pulse Width, Strobe (Figure

1)

tr, tf Maximum Input Rise and Fall Times

(Figure 1)

2.0

4.5

6.0

2.0

4.5

6.0

2.0

4.5

6.0

2.0

4.5

6.0

50
10

9.0
3

3
3

80
16
14

1000

500
400

65
13
11

3
3
3

100

20
17

1000

500
400

75
15
13

3
3
3

120

24
20

1000

500
400

ns

ns

ns

ns

SLS

System Logic

SL74HC4094

Semiconductor

Figure 1. Switching Waveforms Figure 2. Switching Waveforms

Figure 3. Switchin g Waveforms Figure 4. Switching Waveforms

SLS

Figure 5. Test Circuit Figure 6. Test Circuit

System Logic

SL74HC4094

Semiconductor

EXPANDED LOGIC DIAGRAM

SLS

System Logic

SL74HC4094

Semiconductor

TIMING DIAGRAM

SLS

System Logic