Datasheet SL74HC4053 Datasheet (System Logic Semiconductor)

Semiconductor

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Analog Multiplexer/Demultiplexer

High-Performance Silicon-Gate CMOS

The SL74HC4053 utilize silicon-gate CMOS technology to achieve fast propagation delays, low ON resistances, and low OFF leakage currents. These analog multiplexers/demultiplexers control analog voltages that may vary across the complete power supply range (from VCC to VEE).

The Channel-Select inputs determine which one of the Analog Inputs/Outputs is to be connected, by means of an analog switch, to the Common Output/Input.When the Enable pin is high, all analog switches are turned off.

The Channel -Select and Enable inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALSTTL outputs.

• Fast Switching and Propagation Speeds

• Low Crosstalk Between Switches

• Diode Protection on All Inputs/Outputs

• Analog Power Supply Range (VCC-VEE)=2.0 to 12.0 V

• Digital (Control) Power Supply Range (VCC-GND)=2.0 to 6.0 V

• Low Noise

SL74HC4053

ORDERING INFORMATION

SL74HC4053N Plastic

SL74HC4053D SOIC

TA = -55° to 125° C for all packages

PIN ASSIGNMENT

LOGIC DIAGRAM

Triple Single-Pole, Double-Position

Plus Common Off

PIN 16 =V

PIN 7 = VEE

PIN 8 = GND

CC

FUNCTION TABLE

Control Inputs ON

Enable Select Channels

C B A L L L L Z0 Y0 X0 L L L H Z0 Y0 X1 L L H L Z0 Y1 X0 L L H H Z0 Y1 X1 L H L L Z1 Y0 X0 L H L H Z1 Y0 X1 L H H L Z1 Y1 X0 L H H H Z1 Y1 X1

H X X X None

X = don’t care

SLS

System Logic

SL74HC4053

Semiconductor

MAXIMUM RATINGS*

Symbol Parameter Value Unit

VCC Positive DC Supply Voltage (Referenced to GND)

(Referenced to VEE)

-0.5 to +7.0

-0.5 to +14.0

VEE Negative DC Supply Voltage (Referenced to GND) -7.0 to +0.5 V

VIS Analog Input Voltage V

- 0.5 to VCC+0.5 V

EE

VIN Digital Input Voltage (Referenced to GND) -1.5 to VCC +1.5 V

I DC Input Current Into or Out of Any Pin ±25 mA

PD Power Dissipation in Still Air, Plastic DIP+

SOIC Package+

750 500

Tstg Storage Temperature -65 to +150 °C

TL Lead Temperature, 1 mm from Case for 10 Seconds

260 °C

(Plastic DIP or SOIC Package)

*

Maximum Ratings are those values beyond which damage to the device may occur.

Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C

SOIC Package: : - 7 mW/°C from 65° to 125°C

RECOMMENDED OPERATING CONDITIONS

Symbol Parameter Min Max Unit

VCC Positive Supply Voltage (Referenced to GND)

(Referenced to VEE)

2.0

6.0

12.0

V

mW

V

VEE Negative DC Supply Voltage (Referenced to GND) - 6.0 GND V

VIS Analog Input Voltage VEE VCC V

VIN Digital Input Voltage (Referenced to GND) GND VCC V

*

V

Static or Dynamic Voltage Across Switch - 1.2 V

IO

TA Operating Temperature, All Package Types -55 +125 °C

tr, tf Input Rise and Fall Time (Channel Select

or Enable Inputs)

*

For voltage drops across the switch greater than 1.2 V (switch on), excessive VCC current may be drawn;

VCC =2.0 V VCC =4.5 V V

=6.0 V

CC

0 0 0

1000

500 400

ns

i. e., the current out of the switch may contain both VCC and switch input components. The reliability of the device will be unaffected unless the Maximum Ratings are exceeded.

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and V

should be constrained to the range

OUT

indicated in the Recommended Operating Conditions..

Unused digital input pins must always be tied to an appropriate logic voltage level (e.g., either GND or VCC).

Unused Analog I/O pins may be left open or terminated.

System Logic

SLS

SL74HC4053

Semiconductor

DC ELECTRICAL CHARACTERISTICS Digital Section (Voltages Referenced to GND) V

Except Where Noted

VCC Guaranteed Limit

=GND,

EE

Symbol Parameter Test Conditions V 25 °C to

-55°C

VIH Minimum High-Level

Input Voltage, Channel Select or Enable Inputs

VIL Maximum Low -Level

Input Voltage, Channel Select or Enable Inputs

IIN Maximum Input

Leakage Current,

RON = Per Spec 2.0

4.5

6.0

RON = Per Spec 2.0

4.5

6.0

VIN=VCC or GND,

6.0 ±0.1 ±1.0 ±1.0 µA

VEE=-6.0 V

1.5

3.15

4.2

0.3

0.9

1.2

≤85

°C

1.5

3.15

4.2

0.3

0.9

1.2

Channel-Select or Enable Inputs

ICC Maximum Quiescent

Supply Current (per Package)

Channel Select = VCC or GND Enable = VCC or GND V

= VCC or GND

IS

VIO= 0 V VEE = GND VEE = -6.0

6.0

2 8

20 80

DC ELECTRICAL CHARACTERISTICS Analog Section

VCC VEE Guaranteed Limit

Symbol Parameter Test Conditions V V 25 °C

to

-55°C

≤85

°C

≤125

°C

1.5

3.15

4.2

0.3

0.9

1.2

40

160

≤125

°C

Unit

V

µA

Unit

RON Maximum “ON” Resistance VIN=VIL or V

V

= VCC or V

IS

IS ≤ 2.0 mA(Figure 1)

VIN=VIL or V

V

= VCC or VEE

IS

(Endpoints) IS ≤ 2.0 mA(Figure 1)

∆RON Maximum Difference in

“ON” Resistance Between Any Two Channels in the

VIN=VIL or V V

= 1/2 (VCC- VEE)

IS

IS ≤ 2.0 mA

Same Package

I

Maximum Off- Channel

OFF

Leakage Current, Any One Channel

Maximum Off- Channel

Leakage Current, Common Channel

ION Maximum On- Channel

Leakage Current, Channel to Channel

VIN=VIL or V V

= VCC- V

IO

Switch Off (Figure 2) VIN=VIL or V

VIO= VCC- V Switch Off (Figure 3)

VIN=VIL or V Switch to Switch = VCC- VEE (Figure 5)

EE

IH

EE

4.5

0.0

4.5

-4.5

6.0

-6.0

4.5

0.0

4.5

-4.5

6.0

-6.0

4.5

0.0

4.5

6.0

-4.5

-6.0

190 120 100

150 100

80 30

12 10

240

280

150

170

125

140

190

230

125

140

100

35 15 12

115

40 18 14

Ω

6.0 -6.0 0.1 0.5 1.0 µA

6.0 -6.0 0.1 1.0 2.0

6.0 -6.0 0.1 1.0 2.0 µA

SLS

System Logic

SL74HC4053

Semiconductor

AC ELECTRICAL CHARACTERISTICS(C

=50pF,Input tr=tf=6.0 ns)

L

VCC Guaranteed Limit

Symbol Parameter V 25 °C to

≤85°C ≤125°C Unit

-55°C

t

, t

PLH

Maximum Propagation Delay, Channel -Select to

PHL

Analog Output (Figures 8 and 9)

t

, t

PLH

Maximum Propagation Delay , Analog Input to

PHL

Analog Output (Figures 10 and 11)

t

, t

PLZ

Maximum Propagation Delay , Enable to Analog

PHZ

Output (Figures 12 and 13)

t

, t

PZL

Maximum Propagation Delay , Enable to Analog

PZH

Output (Figures 12 and 13)

CIN Maximum Input Capacitance, Channel -Select or

2.0

4.5

6.0

2.0

4.5

6.0

2.0

4.5

6.0

2.0

4.5

6.0

370

74 63

60 12 10

290

58 49

345

69 59

465

93 79

75 15 13

364

73 62

435

87 74

- 10 10 10 pF

Enable Inputs

C

Maximum Capacitance

I/O

Analog I/O

All Switches Off

- 35 35 35 pF

550 110

94 90

18 15

430

86 73

515 103

87

ns

Common O/I - 50 50 50 Feedthrough - 1.0 1.0 1.0

Power Dissipation Capacitance (Per Package)

Typical @25°C,VCC=5.0 V, VEE=0 V

(Figure 15)

CPD Used to determine the no-load dynamic power

consumption: PD=CPDV

2

f+ICCVCC

CC

45 pF

SLS

System Logic

SL74HC4053

Semiconductor

ADDITIONAL APPLICATION CHARACTERISTICS (GND = 0.0 V)

VCC VEE Limit*

Symbol Parameter Test Conditions V V 25 °C Unit

BW Maximum On-

Channel Bandwidth or Minimum Frequency

fin=1 MHz Sine Wave Adjust fin Voltage to Obtain 0 dBm at V Increase fin Frequence Until dB Meter Reads -3 dB RL =50 Ω, CL=10 pF

OS

Response (Figure 5)

- Off-Channel Feedthrough Isolation (Figure 6)

fin= Sine Wave Adjust fin Voltage to Obtain 0 dBm at V

= 10 kHz, RL =600 Ω, CL=50 pF

fin

IS

fin = 1.0 MHz, RL =50 Ω, CL=10 pF 2.25

- Feedthrough Noise, Channel Select Input to Common O/I

VIN≤ 1 MHz Square Wave (tr = tf = 6 ns) Adjust RL at Setup so that IS= 0 A Enable = GND

RL

=600 Ω, CL=50 pF

(Figure 7)

RL =10 Ω, CL=10 pF 2.25

2.25

4.50

6.00

2.25

4.50

6.00

4.50

6.00

2.25

4.50

6.00

4.50

6.00

-2.25

-4.50

-6.00

-2.25

-4.50

-6.00

-2.25

-4.50

-6.00

-2.25

-4.50

-6.00

-2.25

-4.50

-6.00

120 120 120

-50

-40

25 105 135

35 145 190

MHz

dB

mVpp

- Crosstalk Between Any Two Switches (Figure 14)

fin= Sine Wave Adjust fin Voltage to Obtain 0 dBm at V

= 10 kHz, RL =600 Ω, CL=50 pF

fin

fin = 1 MHz, RL =50 Ω, CL=10 pF 2.25

THD Total Harmonic

Distortion (Figure 16)

fin= 1 kHz, RL =10 kΩ, CL=50 pF THD = THD V V V

- THD

Measured

=4.0 VPP sine wave

IS

=8.0 VPP sine wave

IS

=11.0 VPP sine wave

IS

Source

* Limits not tested. Determined by design and verified by qualification.

IS

2.25

4.50

6.00

4.50

6.00

2.25

4.50

6.00

-2.25

-4.50

-6.00

-2.25

-4.50

-6.00

-2.25

-4.50

-6.00

-50

-60

0.10

0.08

0.05

dB

%

SLS

System Logic

SL74HC4053

Semiconductor

Figure 1. On Resistance Test Set -Up

Figure 2. Maximum Off Channel Leakage

Current, Any One Channel, Test Set -UP

Figure 4. Maximum On Channel Leakage Current, Channel to Channel, Test Set -UP

Figure 3. Maximum Off Channel Leakage Current,

Common Channel, Test Set -UP

* Includes all probe and jig capacitance.

Figure 5. Maximum On Channel Bandwidth,

Test Set -UP

* Includes all probe and jig capacitance.

Figure 6. Off Channel Feedthrough Isolation,

Test Set -UP

* Includes all probe and jig capacitance.

Figure 7.Feedthrough Noise, Channel Select to Common

Out, Test Set -UP

System Logic

SLS

SL74HC4053

Semiconductor

Figure 8. Switching Weveforms

* Includes all probe and jig capacitance.

Figure 9. Test Set -UP, Channel Select to Analog Out

Figure 10. Switching Weveforms

Figure 12. Switching Weveforms Figure 13. Test Set -UP, Enable to Analog Out

* Includes all probe and jig capacitance.

Figure 11. Test Set -UP, Analog In to Analog Out

SLS

System Logic

SL74HC4053

Semiconductor

* Includes all probe and jig capacitance.

Figure 14. Crosstalk Between Any Two Switches,

Test Set -Up

Figure 15. Power Dissipation Capacitance, Test Set -Up

Figure 16. Total Harmonic Distortion, Test Set -UP

EXPANDED LOGIC DIAGRAM

SLS

System Logic

Datasheet SL74HC4053 Datasheet (System Logic Semiconductor)

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