Datasheet SL74HC393 Datasheet (System Logic Semiconductor)

SL74HC393

Semiconductor

Dual 4-Stage Binary Ripple Counter

High-Performance Silicon-Gate CMOS

The SL74HC393 is identical in pinout to the LS/ALS393. The device
inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LS/ALSTTL outputs.

This device consists of two independent 4-bit binary ripple
counters with parallel outputs from each counter stage. A÷256 counter
can be obtained by cascading the two binary counters.

Internal flip-flops are triggered by high-to-low transitions of the
clock input. Reset for the counters is asynchronous and active-high.
State changes of the Q outputs do not occur simultaneously becaue of
internal ripple delays. Therefore, decoded output signals are subject to
decoding spikes and should not be used as clocks or as strobes except
when gated with the Clock of the SL74HC393.

• Outputs Directly Interface to CMOS, NMOS, and TTL

• Operating Voltage Range: 2.0 to 6.0 V

• Low Input Current: 1.0 µA

• High Noise Immunity Characteristic of CMOS Devices

ORDERING INFORMATION

SL74HC393N Plastic

SL74HC393D SOIC

TA = -55° to 125° C for all packages

PIN ASSIGNMENT

LOGIC DIAGRAM

PIN 14 =VCC

PIN 7 = GND

FUNCTION TABLE

Inputs Outputs

Clock Reset

X H L
H L No Change

L L No Change

L No Change
L Advance to Next

State

X = don’t care

System Logic

SLS

SL74HC393

Semiconductor

MAXIMUM RATINGS*

Symbol Parameter Value Unit

VCC DC Supply Voltage (Referenced to GND) -0.5 to +7.0 V
VIN DC Input Voltage (Referenced to GND) -1.5 to VCC +1.5 V

V

DC Output Voltage (Referenced to GND) -0.5 to VCC +0.5 V

OUT

IIN DC Input Current, per Pin ±20 mA

I

DC Output Current, per Pin ±25 mA

OUT

ICC DC Supply Current, VCC and GND Pins ±50 mA
PD Power Dissipation in Still Air, Plastic DIP+

SOIC Package+

750
500

Tstg Storage Temperature -65 to +150 °C

TL Lead Temperature, 1 mm from Case for 10 Seconds

260 °C

(Plastic DIP or SOIC Package)

*

Maximum Ratings are those values beyond which damage to the device may occur.

Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C

SOIC Package: : - 7 mW/°C from 65° to 125°C

RECOMMENDED OPERATING CONDITIONS

Symbol Parameter Min Max Unit

VCC DC Supply Voltage (Referenced to GND) 2.0 6.0 V

VIN, V

DC Input Voltage, Output Voltage (Referenced to GND) 0 VCC V

OUT

TA Operating Temperature, All Package Types -55 +125 °C

tr, tf Input Rise and Fall Time (Figure 1) VCC =2.0 V

VCC =4.5 V
V

=6.0 V

CC

0
0
0

1000

500
400

mW

ns

This device contains protection circuitry to guard against damage due to high static voltages or electric
fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, VIN and V
GND≤(VIN or V

OUT

)≤VCC.

should be constrained to the range

OUT

Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC).
Unused outputs must be left open.

System Logic

SLS

SL74HC393

Semiconductor

DC ELECTRICAL CHARACTERISTICS(Voltages Referenced to GND)

VCC Guaranteed Limit

Symbol Parameter Test Conditions V 25 °C

to

-55°C

VIH Minimum High-Level

Input Voltage

VIL Maximum Low -Level

Input Voltage

VOH Minimum High-Level

Output Voltage

VIN=VIH or VIL

VOL Maximum Low -Level

Output Voltage

VIN=VIH or VIL

IIN Maximum Input

V

=0.1 V or VCC-0.1 V

OUT

I

≤ 20 µA

OUT

V

=0.1 V or VCC-0.1 V

OUT

I

 ≤ 20 µA

OUT

VIN=VIH or VIL

I

 ≤ 20 µA

OUT

I

 ≤ 4.0 mA

OUT

I

 ≤ 5.2 mA

OUT

VIN=VIH or VIL

I

 ≤ 20 µA

OUT

I

 ≤ 4.0 mA

OUT

I

 ≤ 5.2 mA

OUT

2.0

4.5

6.0

2.0

4.5

6.0

2.0

4.5

6.0

4.5

6.0

2.0

4.5

6.0

4.5

6.0

1.5

3.15

4.2

0.3

0.9

1.2

1.9

4.4

5.9

3.98

5.48

0.1

0.1

0.1

0.26

0.26

VIN=VCC or GND 6.0 ±0.1 ±1.0 ±1.0 µA

Leakage Current

≤85

°C

1.5

3.15

4.2

0.3

0.9

1.2

1.9

4.4

5.9

3.84

5.34

0.1

0.1

0.1

0.33

0.33

≤125

°C

1.5

3.15

4.2

0.3

0.9

1.2

1.9

4.4

5.9

3.7

5.2

0.1

0.1

0.1

0.4

0.4

Unit

V

V

V

V

ICC Maximum Quiescent

Supply Current
(per Package)

VIN=VCC or GND
I

=0µA

OUT

6.0 8.0 80 160 µA

System Logic

SLS

SL74HC393

Semiconductor

AC ELECTRICAL CHARACTERISTICS(C

VCC Guaranteed Limit

=50pF,Input tr=tf=6.0 ns)

L

Symbol Parameter V 25 °C to

-55°C

f

Maximum Clock Frequency (50% Duty Cycle)

max

(Figures 1 and 3)

t

, t

PLH

Maximum Propagation Delay, Clock to Q1

PHL

(Figures 1 and 3)

t

, t

PLH

Maximum Propagation Delay, Clock to Q2

PHL

(Figures 1 and 3)

t

, t

PLH

Maximum Propagation Delay, Clock to Q3

PHL

(Figures 1 and 3)

t

, t

PLH

Maximum Propagation Delay, Clock to Q4

PHL

(Figures 1 and 3)

t

Maximum Propagation Delay, Reset to any Q

PHL

(Figures 2 and 3)

t

, t

TLH

Maximum Output Transition Time, Any Output

THL

(Figures 1 and 3)

2.0

4.5

6.0

2.0

4.5

6.0

2.0

4.5

6.0

2.0

4.5

6.0

2.0

4.5

6.0

2.0

4.5

6.0

2.0

4.5

6.0

5.4
27
32

120

24
20

190

38
32

240

48
41

290

58
49

165

33
28

75
15
13

≤85°C ≤125°C Unit

4.4
22
26

150

30
26

240

48
41

300

60
51

365

73
62

205

41
35

95
19
16

3.6
18
21

180

36
31

285

57
48

360

72
61

435

87
74

250

50
43

110

22
19

MHz

ns

ns

ns

ns

ns

ns

CIN Maximum Input Capacitance - 10 10 10 pF

Power Dissipation Capacitance (Per Counter) Typical @25°C,VCC=5.0 V

CPD Used to determine the no-load dynamic pow er

consumption: PD=CPDV

TIMING REQUIREMENTS(C

2

f+ICCVCC

CC

=50pF,Input tr=tf=6.0 ns)

L

40 pF

VCC Guaranteed Limit

Symbol Parameter V 25 °C to-55°C ≤85°C ≤125°C Unit

t

Minimum Recovery Time, Reset

rec

Inactive to Clock (Figure 2)

tw Minimum Pulse Width, Clock (Figure

1)

tw Minimum Pulse Width, Set

(Figure 2)

tr, tf Maximum Input Rise and Fall Times

(Figure 1)

2.0

4.5

6.0

2.0

4.5

6.0

2.0

4.5

6.0

2.0

4.5

50
10

9

80
16
14

125

25
21

1000

500

65
13
11

100

20
17

155

31
26

1000

500

75
15
13

120

24
20

190

38
32

1000

500

ns

ns

ns

ns

SLS

System Logic

SL74HC393

Semiconductor

6.0 400 400 400

SLS

System Logic

SL74HC393

Semiconductor

Figure 1. Switching Waveform Figure 2. Switching Waveform

Figure 4.Test Circuit

EXPANDED LOGIC DIAGRAM

SLS

System Logic

SL74HC393

Semiconductor

TIMING DIAGRAM

COUNT SEQUENCE

Outputs

Count Q4 Q3 Q2 Q1

0 L L L L
1 L L L H
2 L L H L
3 L L H H
4 L H L L
5 L H L H
6 L H H L
7 L H H H
8 H L L L

9 H L L H
10 H L H L
11 H L H H
12 H H L L
13 H H L H
14 H H H L
15 H H H H

SLS

System Logic

WWW.ALLDATASHEET.COM

Copyright © Each Manufacturing Company.

All Datasheets cannot be modified without permission.

This datasheet has been download from :

www.AllDataSheet.com

100% Free DataSheet Search Site.

Free Download.

No Register.

Fast Search System.

www.AllDataSheet.com