Datasheet SL74HC367 Datasheet (System Logic Semiconductor)

Semiconductor

Hex 3-State Noninverting Buffer
with Separate 2-Bit and 4-Bit Sections

High-Performance Silicon-Gate CMOS

The SL74HC367 is identical in pinout to the LS/ALS367. The device
inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LS/ALSTTL outputs.

This device is arranged into 2-Bit and 4-Bit sections, each having
its own active-low Output Enable. When either of the enables is high,
the affected buffer outputs are placed into high-impedance states. The
SL74HC367 has noninverting outputs.

• Outputs Directly Interface to CMOS, NMOS, and TTL

• Operating Voltage Range: 2.0 to 6.0 V

• Low Input Current: 1.0 µA

• High Noise Immunity Characteristic of CMOS Devices

ORDERING INFORMATION

TA = -55° to 125° C for all packages

SL74HC367

SL74HC367N Plastic

SL74HC367D SOIC

LOGIC DIAGRAM

PIN ASSIGNMENT

FUNCTION TABLE

Inputs Output

Enable 1,Enable 2 A Y

L L L
L H H

SLS

PIN 16 =VCC

PIN 8 = GND

System Logic

Z = high impedance
X = don’t care

H X Z

SL74HC367

Semiconductor

MAXIMUM RATINGS*

Symbol Parameter Value Unit

VCC DC Supply Voltage (Referenced to GND) -0.5 to +7.0 V
VIN DC Input Voltage (Referenced to GND) -1.5 to VCC +1.5 V

V

DC Output Voltage (Referenced to GND) -0.5 to VCC +0.5 V

OUT

IIN DC Input Current, per Pin ±20 mA

I

DC Output Current, per Pin ±35 mA

OUT

ICC DC Supply Current, VCC and GND Pins ±75 mA
PD Power Dissipation in Still Air, Plastic DIP+

SOIC Package+

750
500

Tstg Storage Temperature -65 to +150 °C

TL Lead Temperature, 1 mm from Case for 10 Seconds

260 °C

(Plastic DIP or SOIC Package)

*

Maximum Ratings are those values beyond which damage to the device may occur.

Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C

SOIC Package: : - 7 mW/°C from 65° to 125°C

RECOMMENDED OPERATING CONDITIONS

Symbol Parameter Min Max Unit

VCC DC Supply Voltage (Referenced to GND) 2.0 6.0 V

VIN, V

DC Input Voltage, Output Voltage (Referenced to GND) 0 VCC V

OUT

TA Operating Temperature, All Package Types -55 +125 °C

tr, tf Input Rise and Fall Time (Figure 1) VCC =2.0 V

VCC =4.5 V
V

=6.0 V

CC

0
0
0

1000

500
400

mW

ns

This device contains protection circuitry to guard against damage due to high static voltages or electric
fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, VIN and V
GND≤(VIN or V

OUT

)≤VCC.

should be constrained to the range

OUT

Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC).
Unused outputs must be left open.

System Logic

SLS

SL74HC367

Semiconductor

DC ELECTRICAL CHARACTERISTICS(Voltages Referenced to GND)

VCC Guaranteed Limit

Symbol Parameter Test Conditions V 25 °C

to

-55°C

VIH Minimum High-Level

Input Voltage

VIL Maximum Low -Level

Input Voltage

VOH Minimum High-Level

Output Voltage

VIN=VIH

VOL Maximum Low -Level

Output Voltage

VIN= VIL

IIN Maximum Input

V

= VCC-0.1 V

OUT

I

≤ 20 µA

OUT

V

=0.1 V

OUT

I

 ≤ 20 µA

OUT

VIN=VIH

I

 ≤ 20 µA

OUT

I

 ≤ 6.0 mA

OUT

I

 ≤ 7.8 mA

OUT

VIN= VIL

I

 ≤ 20 µA

OUT

I

 ≤ 6.0 mA

OUT

I

 ≤ 7.8 mA

OUT

2.0

4.5

6.0

2.0

4.5

6.0

2.0

4.5

6.0

4.5

6.0

2.0

4.5

6.0

4.5

6.0

1.5

3.15

4.2

0.3

0.9

1.2

1.9

4.4

5.9

3.98

5.48

0.1

0.1

0.1

0.26

0.26

VIN=VCC or GND 6.0 ±0.1 ±1.0 ±1.0 µA

Leakage Current

≤85

°C

1.5

3.15

4.2

0.3

0.9

1.2

1.9

4.4

5.9

3.84

5.34

0.1

0.1

0.1

0.33

0.33

≤125

°C

1.5

3.15

4.2

0.3

0.9

1.2

1.9

4.4

5.9

3.7

5.2

0.1

0.1

0.1

0.4

0.4

Unit

V

V

V

V

IOZ Maximum Three-State

Leakage Current

ICC Maximum Quiescent

Supply Current
(per Package)

System Logic

SLS

Output in High-Impedance
State
VIN= VIL or VIH
V

OUT=VCC

or GND

VIN=VCC or GND
I

=0µA

OUT

6.0 ±0.5 ±5.0 ±10 µA

6.0 8.0 80 160 µA

SL74HC367

Semiconductor

AC ELECTRICAL CHARACTERISTICS(C

=50pF,Input tr=tf=6.0 ns)

L

VCC Guaranteed Limit

Symbol Parameter V 25 °C to

≤85°C ≤125°C Unit

-55°C

T

, t

PLH

Maximum Propagation Delay, Input A to

PHL

Output Y (Figures 1 and 3)

T

, t

PLZ

Maximum Propagation Delay ,Output Enable to

PHZ

Output Y (Figures 2 and 4)

T

, t

PZL

Maximum Propagation Delay ,Output Enable to

PZH

Output Y (Figures 2 and 4)

T

, t

TLH

Maximum Output Transition Time, Any Output

THL

(Figures 1 and 3)

2.0

4.5

6.0

2.0

4.5

6.0

2.0

4.5

6.0

2.0

4.5

6.0

120

24
20

175

35
30

190

38
32

60
12
10

150

30
26

220

44
37

240

48
41

75
15
13

180

36
31

265

53
46

285

57
48

90
18
15

CIN Maximum Input Capacitance - 10 10 10 pF

C

Maximum Three-State Output Capacitance

OUT

- 15 15 15 pF

(Output in High-Impedance State)

Power Dissipation Capacitance (Per Buffer) Typical @25°C,VCC=5.0 V

ns

ns

ns

ns

CPD Used to determine the no-load dynamic power

consumption:
PD=CPDV

2

f+ICCVCC

CC

40 pF

Figure 1. Switching Waveforms Figure 2. Switching Waveforms

SLS

System Logic

SL74HC367

Semiconductor

Figure 3. Test Circuit Figure 4. Test Circuit

EXPANDED LOGIC DIAGRAM

(1/6 of the Device)

SLS

System Logic

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