Datasheet SI3442DV Datasheet (Fairchild Semiconductor)

March 2001

SI3442DV

N-Channel Logic Level Enhancement Mode Field Effect Transistor

General Description Features

These N-Channel logic level enhancement mode power field
effect transistors are produced using Fairchild's proprietary,
high cell density, DMOS technology. This very high density
process is tailored to minimize on-state resistance. These
devices are particularly suited for low voltage applications in
notebook computers, portable phones, PCMICA cards, and
other battery powered circuits where fast switching, and low
in-line power loss are needed in a very small outline surface
mount package.

____________________________________________________________________________________________

4.1 A, 20 V. R
R

= 0.06 Ω @ VGS = 4.5 V

DS(ON)

= 0.075 Ω @ VGS =2.7 V.

DS(ON)

Proprietary SuperSOTTM-6 package design using copper
lead frame for superior thermal and electrical capabilities.

High density cell design for extremely low R

DS(ON)

.

Exceptional on-resistance and maximum DC current
capability.

4

5

6

Absolute Maximum Ratings T

= 25°C unless otherwise note

A

Symbol Parameter SI3442DV

V
V
I

D

Drain-Source Voltage 20 V

DSS

Gate-Source Voltage - Continuous 8 V

GSS

Drain Current - Continuous (Note 1a) 4.1 A

- Pulsed 15

P

T

Maximum Power Dissipation (Note 1a) 1.6 W

D

(Note 1b) 1

(Note 1c)

Operating and Storage Temperature Range -55 to 150 °C

J,TSTG

0.8

THERMAL CHARACTERISTICS

R
R

Thermal Resistance, Junction-to-Ambient (Note 1a) 78 °C/W

JA

θ

Thermal Resistance, Junction-to-Case (Note 1) 30 °C/W

JC

θ

3

2

1

© 2001Fairchild Semiconductor Corporation

SI3442DV Rev. A

ELECTRICAL CHARACTERISTICS (T

= 25°C unless otherwise noted)

A

Symbol Parameter Conditions Min Typ Max Units
OFF CHARACTERISTICS

DSS

Drain-Source Breakdown Voltage VGS = 0 V, ID = 250 µA 20 V
Zero Gate Voltage Drain Current

Gate - Body Leakage, Forward
Gate - Body Leakage, Reverse

(Note 2)

Gate Threshold Voltage

V

= 16 V, V

DS

V

= 8 V, VDS = 0 V

GS

V

= -8 V, VDS= 0 V

GS

V

= VGS, ID = 250 µA

DS

GS

= 0 V

= 55oC

T

J

= 125oC

T

J

1 µA

10 µA

100 nA

-100 nA

0.4 0.7 1 V

0.3 0.5 0.8

Static Drain-Source On-Resistance VGS = 4.5 V, ID = 4.1 A 0.039 0.06

0.06 0.11

15 A

On-State Drain Current

TJ = 125oC

= 2.7 V, ID = 3.6 A 0.05 0.075

V

GS

= 4.5 V, VDS = 5 V

V

GS

Forward Transconductance VDS = 4.5 V, ID = 4.1 A 12 S

Ω

BV
I

DSS

I

GSSF

I

GSSR

ON CHARACTERISTICS

V

GS(th)

R

DS(ON)

I

D(on)

g

FS

DYNAMIC CHARACTERISTICS

C

iss

C

oss

C

rss

Input Capacitance
Output Capacitance 230 pF
Reverse Transfer Capacitance 95 pF

SWITCHING CHARACTERISTICS

t
t
t
t
Q
Q
Q

D(on)

r

D(off)

f

g

gs

gd

Turn - On Delay Time
Turn - On Rise Time 25 45 ns
Turn - Off Delay Time 28 50 ns
Turn - Off Fall Time 8 15 ns
Total Gate Charge
Gate-Source Charge 1 nC
Gate-Drain Charge 3.3 nC

(Note 2)

V

= 10 V, V

DS

f = 1.0 MHz

V

= 5 V, ID = 1 A,

DD

V

= 4.5 V, R

GEN

V

= 10 V,

DS

I

= 4.1 A, VGS = 4.5 V

D

GS

GEN

= 0 V,

= 6 Ω

365 pF

9 17 ns

10 14 nC

SI3442DV Rev.A

ELECTRICAL CHARACTERISTICS (T

= 25°C unless otherwise noted)

A

Symbol Parameter Conditions Min Typ Max Units
DRAIN-SOURCE DIODE CHARACTERISTICS

I

S

V

SD

1. R

Scale 1 : 1 on letter size paper

2. Pulse Test: Pulse Width <

Continuous Source Diode Current 1.3 A
Drain-Source Diode Forward Voltage

Notes:

is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R

JA

θ

design while R

(t)

P

D

Typical R

is determined by the user's board design.

CA

θ

=

T

R

JA

θ

a. 78
b. 125
c. 156

T

J−TA

=

(t)

R

J A

θ

θ

J C

using the board layouts shown below on 4.5"x5" FR-4 PCB in a still air environment:

o

C/W when mounted on a 1 in2 pad of 2oz copper.

o

C/W when mounted on a 0.01 in2 pad of 2oz copper.

o

C/W when mounted on a 0.003 in2 pad of 2oz copper.

J−TA

+R

2

= I

(t) × R

DS(ON ) T

D

(t)

θ

CA

J

1a

300µs, Duty Cycle < 2.0%.

V

= 0 V, IS = 1.3 A (Note 2)

GS

1b

1c

0.75 1.2 V

is guaranteed by

JC

θ

SI3442DV Rev.A

Typical Electrical Characteristics

15

12

V = 4.5V

GS

3.0V

2.7V

2.5V

2.0V

9

6

3

D

I , DRAIN-SOURCE CURRENT (A)

0

0 1 2 3

V , DRAIN-SOURCE VOLTAGE (V)

DS

1.5V

Figure 1. On-Region Characteristics.

1.8

I = 4.1A

D

1.6

V = 4.5V

GS

1.4

1.2

1

DS(ON)

R , NORMALIZED

0.8

DRAIN-SOURCE ON-RESISTANCE

0.6

-50 -25 0 25 50 75 100 125 150
T , JUNCTION TEMPERATURE (°C)

J

2.5

2

V =2.0V

GS

1.5

DS(on)

1

R , NORMALIZED

DRAIN-SOURCE ON-RESISTANCE

0.5
0 3 6 9 12 15

2.5V

2.7V

I , DRAIN CURRENT (A)

D

3.0V

3.5V

Figure 2. On-Resistance Variation

with Drain Current and Gate Voltage

2.5

V = 4.5V

GS

2

T = 125°C

1.5

1

DS(on)

R , NORMALIZED

0.5

DRAIN-SOURCE ON-RESISTANCE

0

0 3 6 9 12 15

J

25°C

I , DRAIN CURRENT (A)

D

-55°C

4.5V

.

Figure 3. On-Resistance Variation

with Temperature.

15

V =- 5V

DS

12

9

6

D

I , DRAIN CURRENT (A)

3

0

0 0.5 1 1.5 2 2.5 3

V , GATE TO SOURCE VOLTAGE (V)

GS

T = -55°C

J

25°C

125°C

Figure 5. Transfer Characteristics.

Figure 4. On-Resistance Variation

with Drain Current and Temperature

1.3

1.2

1.1
1

0.9

0.8

th

V , NORMALIZED

0.7

0.6

GATE-SOURCE THRESHOLD VOLTAGE

0.5

-50 -25 0 25 50 75 100 125 150
T , JUNCTION TEMPERATURE (°C)

J

V = V

DS

I = 250µA

D

Figure 6. Gate Threshold Variation

with Temperature

.

.

GS

SI3442DV Rev.A

Typical Electrical Characteristics (continued)

1.12

I = 250µA

D

1.08

1.04

1

DSS

BV , NORMALIZED

0.96

DRAIN-SOURCE BREAKDOWN VOLTAGE

0.92

-50 -25 0 25 50 75 100 125 150
T , JUNCTION TEMPERATURE (°C)

J

Figure 7. Breakdown Voltage Variation with

Temperature.

1500
1000

600

300
200

CAPACITANCE (pF)

f = 1 MHz
V = 0V

100

GS

50

0.1 0.2 0.5 1 2 5 10 20
V , DRAIN TO SOURCE VOLTAGE (V)

DS

C

C

C

iss

oss

rss

10

5

V =0V

GS

1

0.1

0.01

0.001

S

I , REVERSE DRAIN CURRENT (A)

0.0001
0 0.2 0.4 0.6 0.8 1 1.2

T = 125°C

J

25°C

-55°C

V , BODY DIODE FORWARD VOLTAGE (V)

SD

Figure 8. Body Diode Forward Voltage Variation with

Source Current and Temperature.

5

I = 4.1A

D

4

3

2

1

GS

V , GATE-SOURCE VOLTAGE (V)

0

0 3 6 9 12

Q , GATE CHARGE (nC)

g

V = 5V

DS

10V

15V

Figure 9. Capacitance Characteristics.

V

DD

V

IN

D

V

GS

R

GEN

G

S

Figure 11. Switching Test Circuit

Figure 10. Gate Charge Characteristics.

t t

on off

t

R

d(on)

L

V

OUT

V

OUT

r

90%

10%

DUT

V

IN

50%

10%

PULSE WIDTH

.

Figure 12. Switching Waveforms.

t

d(off)

50%

90%

90%

10%

SI3442DV Rev.A

tt

f

INVERTED

Typical Electrical and Thermal Characteristics

(continued)

25

V = 5V

DS

20

15

T = -55°C

J

25°C

125°C

10

5

FS

g , TRANSCONDUCTANCE (SIEMENS)

0

0 2 4 6 8 10

I , DRAIN CURRENT (A)

D

Figure 13. Transconductance Variation with

Drain Current and Temperature

5

4.5

4

3.5

1b

1c

3

2.5

D

I , STEADY-STATE DRAIN CURRENT (A)

2

0 0.2 0.4 0.6 0.8 1

2oz COPPER MOUNTING PAD AREA (in )

.

4.5"x5" FR-4 Board

o

T = 25 C

A

Still Air
V = 4.5V

GS

2

2

1.5

1b

1

1c

0.5

STEADY-STATE POWER DISSIPATION (W)

0

0 0.2 0.4 0.6 0.8 1

2oz COPPER MOUNTING PAD AREA (in )

4.5"x5" FR-4 Board

o

T = 25 C

A

Still Air

2

1a

Figure 14. SuperSOTTM-6 Maximum Steady-State

Power Dissipation versus Copper Mounting Pad
Area.

20
10

RDS(ON) LIMIT

1a

5
2

1

0.5

V = 4.5V

0.2

0.1

D

I , DRAIN CURRENT (A)

0.05

GS

SINGLE PULSE

R = See Note 1c

JA

θ

T = 25°C

A

DC

0.02

0.01

0.1 0.2 0.5 1 2 5 10 20 40
V , DRAIN-SOURCE VOLTAGE (V)

DS

100us

1ms

10ms

100ms

1s

Figure 15. Maximum Steady-State Drain Current

Figure 16. Maximum Safe Operating Area.

versus Copper Mounting Pad Area.

1

D = 0.5

0.5

R (t) = r(t) * R

JA

0.2

0.1

0.05

0.02

r(t), NORMALIZED EFFECTIVE

0.01

TRANSIENT THERMAL RESISTANCE

0.005

0.2

0.1

0.05

0.02

0.01

Single Pulse

0.00001 0.0001 0.001 0.01 0.1 1 10 100 300
t , TIME (sec)

1

Figure 17. Transient Thermal Response Curve.

Note: Thermal characterization performed using the conditions described in note 1c. Transient thermal response will change

depending on the circuit board design.

θ

R = See Note 1c

JA

θ

P(pk)

t

1

t

2

T - T = P * R (t)

J

A

Duty Cycle, D = t / t

JA

θ

1

JA

θ

2

SI3442DV Rev.A

TRADEMARKS

The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is
not intended to be an exhaustive list of all such trademarks.

ACEx™
Bottomless™
CoolFET™
CROSSVOL T™
DenseTrench™
DOME™
EcoSPARK™
E2CMOS
EnSigna

TM

TM

FACT™
FACT Quiet Series™



FAST
FASTr™
GlobalOptoisolator™
GTO™
HiSeC™
ISOPLANAR™
LittleFET™
MicroFET™
MICROWIRE™
OPTOLOGIC™
OPTOPLANAR™

PACMAN™
POP™
PowerTrench



QFET™
QS™
QT Optoelectronics™
Quiet Series™
SILENT SWITCHER
SMART ST ART™
St ar* Power™
Stealth™



SuperSOT™-3
SuperSOT™-6
SuperSOT™-8
SyncFET™
TinyLogic™
UHC™
UltraFET



VCX™

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NOTICE TO ANY PRODUCTS HEREIN T O IMPROVE RELIABILITY , FUNCTION OR DESIGN. FAIRCHILD
DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICA TION OR USE OF ANY PRODUCT
OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS P ATENT
RIGHTS, NOR THE RIGHTS OF OTHERS.

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DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORA TION.
As used herein:

1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant into
the body, or (b) support or sustain life, or (c) whose
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
reasonably expected to result in significant injury to the
user.

2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or

effectiveness.

PRODUCT STA TUS DEFINITIONS
Definition of Terms

Datasheet Identification Product Status Definition

Advance Information

Preliminary

No Identification Needed

Obsolete

Formative or
In Design

First Production

Full Production

Not In Production

This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.

This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.

This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.

This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.

Rev. H1