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SCAN182541A
Non-Inverting Line Driver
with 25
Ω Series Resistor Outputs
SCAN182541A Non-Inverting Line Driver with 25
January 1993
Revised August 2000
General Description
The SCAN182541A is a high performance BiCMOS line
driver featuring se pa rate da ta i npu ts o rga nize d i nt o d ual 9bit bytes with byte-oriented paired output enable control
signals. This device is compliant with IEEE 1149.1 Standard Test Access Port and Boundary-Scan architecture
with the incorporation of th e defined Boundary-Scan test
logic and test access port consisting of Test Data Input
(TDI), Test Data Out (TDO), Test Mode Select (TMS), and
Test Clock (TCK).
Features
■ IEEE 1149.1 (JTAG) Compliant
■ High performance BiCMOS technology
Ω series resistor outputs elim inate need for external
■ 25
terminating resistors
■ Dual output enable signals per byte
■ 3-STATE outputs for bus-oriented applications
■ 25 mil pitch SSOP (Shrink Small Outline Package)
■ Includes CLAMP, IDCODE and HIGHZ instructions
■ Additional instructions SAMPLE-IN, SAMPLE-OUT and
EXTEST-OUT
■ Power up 3-STATE for hot insert
■ Member of Fairchild’s SCAN Products
Ordering Code:
Order Number
SCAN182541ASSC MS56A 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide
Devices also availab l e in Tape and Reel. Specify by appending th e s uffix let t er “X” to the ordering code.
Package
Number
Package Description
Connection Diagram Pin Descriptions
Names
AI
(0–8)
BI
(0–8)
AOE
AOE
BOE
BOE
AO
BO
Pin
Input Pins, A Side
Input Pins, B Side
,
3-STATE Output Enable Input Pins, A Side
1
2
,
3-STATE Output Enable Input Pins, B Side
1
2
Output Pins, A Side
(0–8)
Output Pins, B Side
(0–8)
Description
Ω
Series Resistor Outputs
© 2000 Fairchild Semiconductor Corporation DS011543 www.fairchildsemi.com
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Truth Tables
†AOE
1
LLHH
HXXZ
SCAN182541A
XHXZ
LLLL
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Block Diagrams
Inputs
†AOE
AO
AI
2
(0–8)
(0–8)
†BOE
Inputs
†BOE
1
BI
2
(0–8)
BO
(0–8)
LLHH
HXXZ
XHXZ
LLLL
Z = High Impedance
† = Inactive-to-ac ti ve tr ans ition must occur to enable outputs upon
power-up.
Byte A
Tap Controller
Byte B
Note: BSR stands for Boun dary Scan Register.
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Description of BOUNDARY-SCAN Circuitry
The scan cells used in the BOUNDARY-SCAN register are
one of the followin g two types de pending upon t heir location. Scan cell TYPE1 is intended to solely observe system
data, while TYPE2 has the additional ability to control system data.
Scan cell TYPE1 is located on each system input pin while
scan cell TYPE2 is locate d at each system output pi n as
well as at each of the two internal active-high output enable
signals. AOE controls the activity of the A-outputs while
BOE controls the activity of the B-outputs. Each will activate their respectiv e outputs by loading a logi c high.
The BYPASS register is a single bit shift register stage
identical to scan cell TYPE1. It captures a fixed logic low.
Bypass Register Scan Chain Definition
SCAN182541A Product IDCODE
(32-Bit Code per IEEE 1149.1)
Version Entity
0000 111111 000000100100000001111 1
MSB LSB
Logic 0
Part ManufacturerRequired b
y
Number ID 1149.1
Scan Cell TYPE1
The INSTRUCTION r egist er is a n 8-b it r egister whic h captures the default val ue of 10 000001 (SA MPLE/PRE LOAD)
during the CAPTURE-IR inst ruct ion comm and. Th e benef it
of capturing SAMPLE/PRELOAD as the default instruction
during CAPTURE-IR is that the user is no longer required
to shift in the 8-bit instruction for SAMPLE/P RELOAD . The
sequence of: CAPTURE-IR
update the SAMPLE/PRELOAD instruction. For more information refer to the section on instruction definitions.
MSB
→LSB
SCAN182541A
→EXIT1-IR→ UPDATE-IR will
Instruction Register Scan Chain Definition
Instruction Code Instruction
00000000 EXTEST
10000001 SAMPLE/PRELOAD
10000010 CLAMP
00000011 HIGH-Z
01000001 SAMPLE-IN
01000010 SAMPLE-OUT
00100010 EXTEST-OUT
10101010 IDCODE
11111111 BYPASS
All Others BYPASS
Scan Cell TYPE2
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Description of BOUNDARY-SCAN Circuitry (Continued)
BOUNDARY-SCAN Register
Scan Chain Definition (42 Bits in Length)
SCAN182541A
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Description of BOUNDARY-SCAN Circuitry (Continued)
Input BOUNDARY-SCAN Register
Scan Chain De finition (22 Bits in Length)
When SAMPLE-IN is Active
SCAN182541A
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Description of BOUNDARY-SCAN Circuitry (Continued)
Output BOUNDARY-SCAN Register
Scan Chain Definition (20 Bits in Length)
When SAMPLE-OUT and EXTEXT Out are Active
SCAN182541A
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Description of BOUNDARY-SCAN Circuitry (Continued)
BOUNDARY-SCAN Register Definition Index
Bit No. Pin Name Pin No. Pin Type Scan Cell Type
41 AOE
40 AOE
1
2
39 AOE Internal TYPE2
38 BOE
37 BOE
1
2
36 BOE Internal TYPE2
35 AI
34 AI
33 AI
32 AI
31 AI
30 AI
29 AI
28 AI
27 AI
26 BI
25 BI
24 BI
23 BI
22 BI
21 BI
20 BI
19 BI
18 BI
17 AO
16 AO
15 AO
14 AO
13 AO
12 AO
11 AO
10 AO
9AO
8BO
7BO
6BO
5BO
4BO
3BO
2BO
1BO
0BO
0
1
2
3
4
5
6
7
8
0
1
2
3
4
5
6
7
8
0
1
2
3
4
5
6
7
8
0
1
2
3
4
5
6
7
8
3 Input TYPE1
54 Input TYPE1
26 Input TYPE1
31 Input TYPE1
55 Input TYPE1
53 Input TYPE1
52 Input TYPE1
50 Input TYPE1
49 Input TYPE1
47 Input TYPE1
46 Input TYPE1
44 Input TYPE1
43 Input TYPE1
42 Input TYPE1
41 Input TYPE1
39 Input TYPE1
38 Input TYPE1
36 Input TYPE1
35 Input TYPE1
33 Input TYPE1
32 Input TYPE1
30 Input TYPE1
2 Output TYPE2
4 Output TYPE2
5 Output TYPE2
7 Output TYPE2
8 Output TYPE2
10 Output TYPE2
11 Output TYPE2
13 Output TYPE2
14 Output TYPE2
15 Output TYPE2
16 Output TYPE2
18 Output TYPE2
19 Output TYPE2
21 Output TYPE2
22 Output TYPE2
24 Output TYPE2
25 Output TYPE2
27 Output TYPE2
Control
Signals
A–in
B–in
A–out
B–out
SCAN182541A
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Absolute Maximum Ratings(Note 1) Recommended Operating
Storage Temperature −65°C to +150°C
Ambient Temperature under Bias
Junction Temperature under Bias
Pin Potential to Ground Pin −0.5V to +7.0V
V
CC
Input Voltage (Note 2)
SCAN182541A
Input Current (Note 2)
−55°C to +125°C
−55°C to +150°C
−0.5V to +7.0V
−30 mA to +5.0 mA
Voltage Applied to Any Output
in Disabled or Power-Off State
in the HIGH State
−0.5V to +5.5V
−0.5V to V
Current Applied to Output
in LOW State (Max) Twice the Rated I
DC Latchup Source Current
Over Voltage Latchup (I/O) 10V
EDS (HBM) Min. 2000V
OL
−500 mA
Conditions
Free Air Ambient Temperature
Supply Voltage
Minimum Input Edge Rate (
Data Input 50 mV/ns
Enable Input 20 mV/ns
CC
(mA)
Note 1: Absolute Maximum Ratings are values beyond which the device
may be damaged or have its useful life impair ed. Functional operation
under these conditi ons is not implied.
Note 2: Either voltage lim it or c urrent limit is sufficient to prot ect inputs.
DC Electrical Characteristics
−40°C to +85°C
+4.5V to +5.5V
∆V/∆t)
Symbol Parameter
V
V
V
V
V
I
IH
I
BVI
I
BVIT
I
IL
V
IIH + I
IIL + L
I
OZH
I
OZL
I
OS
I
CEX
I
ZZ
Input HIGH Voltage 2.0 V Recognized HIGH Signal
IH
Input LOW Voltage 0.8 V Recognized LOW Signal
IL
Input Clamp Diode Voltage Min −1.2 V IIN = −18 mA
CD
Output HIGH Voltage Min 2.5 V IOH = −3 mA
OH
Output LOW Voltage Min 0.8 V IOL = 15 mA
OL
Input HIGH Current
Input HIGH Current Breakdown Test Max 7 µAVIN = 7.0V
Input HIGH Current Breakdown Test (I/O) Max 100 µAVIN = 5.5V
Input LOW Current
Input Leakage Test 0.0 4.75 V IID = 1.9 µA
ID
Output Leakage Current Max 50 µAV
OZH
Output Leakage Current Max −50 µAV
OZL
Output Leakage Current Max 50 µAV
Output Leakage Current Max −50 µAV
Output Short-Circuit Current Max −100 −275 mA V
Output HIGH Leakage Current Max 50 µAV
Bus Drainage Test 0.0 100 µAV
V
Min 2.0 V IOH = −32 mA
All Others
TMS, TDI Max 5 µAVIN = V
All Others
TMS, TDI Max −385 µAVIN = 0.0V
Max 5 µAVIN = 2.7V (Note 3)
Max 5 µAVIN = V
Max −5 µAVIN = 0.5V (Note 3)
Max −5 µAV
Min Typ Max Units Conditions
CC
All Other Pins Grounded
All Others Grounded
= 0.0V
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
CC
CC
= 2.7V
= 0.5V
= 2.7V
= 0.5V
= 0.0V
= VCC
= 5.5V
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DC Electrical Characteristics (Continued)
SCAN182541A
Symbol Parameter
I
I
I
I
CCH
CCL
CCZ
CCT
Power Supply Current Max 250 µAV
Power Supply Current Max 65 mA V
Power Supply Current Max 250 µA TDI, TMS = V
Additional ICC/Input All Other Inputs Max 2.9 mA VIN = VCC − 2.1V
TDI, TMS Inputs Max 3 mA V
I
CCD
Note 3: Guaranteed not tested.
Dynamic I
CC
No Load Max 0.2 mA/ Outputs Open
AC Electrical Characteristics
Normal Operation:
Symbol Parameter
t
PLH
t
PHL
t
PLZ
t
PHZ
t
PZL
t
PZH
t
PLH
t
PHL
t
PLZ
t
PHZ
t
PZL
t
PZH
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLZ
t
PHZ
t
PLZ
t
PHZ
t
PLZ
t
PHZ
t
PZL
t
PZH
t
PZL
t
PZH
t
PZL
t
PZH
Note 4: Voltage Range 5.0V ± 0.5V
Propagation Delay 5.0 1.0 3.4 5.2
Data to Q 1.9 4.1 6.5
Disable Time 5.0 2.0 5.2 8.7
Enable Time 5.0 2.4 6.1 9.6
Propagation Delay 5.0 3.2 6.0 9.4
TCK to TDO 4.5 7.6 11.3
Disable Time 5.0 2.5 5.8 9.9
TCK to TDO 3.7 7.4 11.8
Enable Time 5.0 4.9 8.6 12.9
TCK to TDO 3.1 6.7 10.7
Propagation Delay 3.7 6.7 10.3
TCK to Data Out during Update-DR State 5.0 4.9 8.3 12.4
Propagation Delay 4.2 7.9 12.2
TCK to Data Out during Update-IR State 5.0 5.3 9.2 13.8
Propagation Delay 5.0 9.4 14.6
TCK to Data Out during Test Logic Reset State 5.0 6.2 10.9 16.4
Disable Time 3.7 7.9 13.0
TCK to Data Out during Update-DR State 5.0 4.3 8.7 13.7
Disable Time 3.7 8.5 14.2
TCK to Data Out during Update-IR State 5.0 4.3 9.4 14.8
Disable Time 4.7 10.1 16.6
TCK to Data Out during Test Logic Reset State 5.0 5.5 10.9 17.3
Enable Time 5.5 9.8 14.7
TCK to Data Out during Update-DR State 5.0 4.0 7.9 12.5
Enable Time 5.8 10.9 16.5
TCK to Data Out during Update-IR State 5.0 4.3 9.0 14.4
Enable Time 6.6 12.5 19.1
TCK to Data Out during Test Logic Reset State 5.0 4.9 10.5 16.9
V
Min Typ Max Units Conditions
CC
= VCC; TDI, TMS = V
OUT
Max 1.0 mA V
Max 65.8 mA V
= VCC; TDI, TMS = GND
OUT
= LOW; TDI, TMS = V
OUT
= LOW; TDI, TMS = GND
OUT
CC
Max 1.0 mA TDI, TMS = GND
= VCC − 2.1V
IN
MHz One Bit Toggling, 50% Duty Cycle
V
CC
(V)
TA = −40°C to +85°C
CL = 50 pF
(Note 4) Min Typ Max
1.9 5.6 9.2
1.6 5.1 8.5
CC
CC
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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AC Operating Requirements
Scan Test Operation:
V
Symbol Parameter
CC
(V)
(Note 5) Guaranteed Minimum
SCAN182541A
t
S
t
H
t
S
t
H
t
S
Setup Time
Data to TCK (Note 6)
Hold Time
Data to TCK (Note 6)
Setup Time, H or L
AOE
, BOEn to TCK (Note 7)
n
Hold Time, H or L
TCK to AOEn, BOEn (Note 7)
Setup Time, H or L
Internal AOE
, BOEn,5.02.7ns
n
5.0 2.2 ns
5.0 1.8 ns
5.0 3.7 ns
5.0 1.8 ns
to TCK (Note 8)
t
H
Hold Time, H or L
TCK to Internal 5.0 1.8 ns
AOEn, BOEn (Note 8)
t
S
t
H
t
S
t
H
t
W
Setup Time, H or L
TMS to TCK
Hold Time, H or L
TCK to TMS
Setup Time, H or L
TDI to TCK
Hold Time, H or L
TCK to TDI
5.0 7.5 ns
5.0 1.8 ns
5.0 5.0 ns
5.0 2.0 ns
Pulse Width TCK H 5.0 10.0
L 10.8
f
MAX
t
PU
t
DN
Note 5: Voltage Range 5.0V ± 0.5V
Note 6: This delay represent s th e t im ing relationship between the data input and TCK at the associated scan cells numbered 0-8, 9-17, 18-26 and 27-35.
Note 7: Timing pertains to BSR 38 and 41 or BSR 37 and 40.
Note 8: This delay represents the timing relationship between AOE/BOE and TCK for scan cells 36 and 39 only.
Note: All Input Timing Delays involv ing TCK are measu red from the rising edg e of T C K.
Maximum TCK Clock Frequency 5.0 50 MHz
Wait Time, Power Up to TCK 5.0 100 ns
Power Down Delay 0.0 100 ms
TA = −40°C to +85°C
C
= 50 pF
L
Units
ns
Capacitance
Symbol Parameter Typ Units
C
IN
C
OUT
Note 9: C
Input Capacitance 5.8 pF VCC = 0.0V
Output Capacitance (Note 9) 13.8 pF VCC = 5.0V
is measured at frequency f = 1 MHz, per MIL-STD-883B, Method 3012.
OUT
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Conditions, T
= 25°C
A
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Physical Dimensions inches (millimeters) unless otherwise noted
SCAN182541A Non-Inverting Line Driver with 25
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide
Fairchild does not assume any responsibility for use of any circuitry described , no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are dev ic es or syste ms
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provide d in the l abe ling, can be reasonably expected to result in a significant injury to the
user.
Package Number MS56A
2. A critical compo nent in any com ponen t of a life s upp ort
device or system whose failure to perform can be reasonably expected to cause the failure of the l ife support
device or system, or to affect its safety or effectiveness.
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Ω
Series Resistor Outputs
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