Datasheet SCAN182374ASSC, SCAN182374ASSCX Datasheet (Fairchild Semiconductor)

© 2000 Fairchild Semiconductor Corporation DS011545 www.fairchildsemi.com

January 1993
Revised August 2000

SCAN182374A D-Type Flip-Flop with 25

Ω

Series Resistor Outputs

SCAN182374A
D-Type Flip-Flop with 25

Ω Series Resistor Outputs

General Description

The SCAN182374A is a high performance BiCMOS D-type
flip-flop featuring separate D-type inputs organized into
dual 9-bit bytes with byte -orien ted clock a nd out put ena ble
control signals. This device is compliant with IEEE 1149.1
Standard Test Access Port and Boundary Scan Architec­ture with the incorporat ion of the defined boundary-scan
test logic and test access port consisting of Test Data Input
(TDI), Test Data Out (TDO), Test Mode Select (TMS), and
Test Clock (TCK).

Features

■ IEEE 1149.1 (JTAG) Compliant

■ High performance BiCMOS technology

■ 25

Ω series resistor outputs elim inate need for external

terminating resistors

■ Buffered positive edge-triggered clock

■ 3-STATE outputs for bus-oriented applications

■ 25 mil pitch SSOP (Shrink Small Outline Package)

■ Includes CLAMP, IDCODE and HIGHZ instructions

■ Additional instructions SAMPLE -IN, SAM P LE-O U T and

EXTEST-OUT

■ Power up 3-STATE for hot insert

■ Member of Fairchild’s SCAN Products

Ordering Code:

Device also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagram Pin Descriptions

Tru th Tables

H = HIGH Voltage Level Z = High Impedance
L = LOW Voltage Level



= L-to-H Transition

X = Immaterial
Note 1: Inactive-to-active transition must occur to enable outputs upon

power-up.

Order Number Package Number Package Description

SCAN182374ASSC MS56A 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide

Pin Names Description

AI

(0–8)

, BI

(0–8)

Data Inputs
ACP, BCP Clock Pulse Inputs
AOE

1

, BOE

1

3-STATE Output Enable Inputs
AO

(0–8)

, BO

(0–8)

3-STATE Outputs

Inputs

AO

(0–8)

ACP AOE1

(Note 1)

AI

(0–8)

XHXZ



LLL



LHH

Inputs

BO

(0–8)

BCP BOE

1

(Note 1)

BI

(0–8)

XHXZ



LLL



LHH

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SCAN182374A

Functional Description

The SCAN182374A consi sts of two sets of nine edge- trig­gered flip-flops with individual D-type inputs and 3-STATE
true outputs. The buffered clock and buffered Output
Enable pins are co mmon to all flip-flops. Each set of the
nine flip-flops will store the state of their individual D inputs
that meet the setup and hold time requirements on the

LOW-to-HIGH Clock (ACP or BCP) transition. With the
Output Enable (AOE

1

or BOE1) LOW, the contents of the

nine flip-flops are available at the outputs. When the Output
Enable is HIGH, the outputs go to the high impedance
state. Operation of the Output Enable inp ut does not affect
the state of the flip-flops.

Logic Diagram

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

Block Diagrams

Byte-A

Note: BSR stands for Boun dary Scan Register

Tap Controller

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SCAN182374A

Block Diagrams (Continued)

Byte-B

Note: BSR stands for BOUNDARY-SCAN Register

Description of BOUNDARY-SCAN Circuitry

The scan cells used in the BOUNDARY-SCAN register are
one of the followin g two types de pending upon t heir loca­tion. Scan cell TYPE1 is intended to solely observe system
data, while TYPE2 has the additional ability to control sys­tem data.

Scan cell TYPE1 is located on each system input pin while
scan cell TYPE2 is locate d at each system output pin as
well as at each of the two internal active-high output enable
signals. AOE controls the activity of the A-outputs while
BOE controls the activity of the B-outputs. Each will acti­vate their respective outputs by loading a logi c high.

The BYPASS register is a single bit shift register stage
identical to scan cell TYPE1. It captures a fixed logic low.

Bypass Register Scan Chain Definition

Logic 0

SCAN182374A Product IDCODE

(32-Bit Code per IEEE 1149.1)

The INSTRUCTION r egist er is a n 8-b it r egister whic h cap­tures the default valu e of 10000 001 (SAM PLE/PRE LOAD)
during the CAPTURE-IR inst ructi on comm and. Th e benef it
of capturing SAMPLE/PRELOAD as the default instruction
during CAPTURE-IR is that the user is no longer required
to shift in the 8-bit instruction for SAMPLE/P RELOAD . The
sequence of: CAPTURE-IR

→ EXIT1-IR → UPDATE-IR

will update the SAMPLE/PRELOAD instruction. For more
information refer to the section on instruction definitions.

Instruction Register Scan Chain Definition

Version Entity Per Manufacturer Required

Number ID by 1149.1

0000 111111 0000000111 00000001111 1

MSB LSB

MSB → LSB

Instruction Code Instruction

00000000 EXTEST
10000001 SAMPLE/PRELOAD
10000010 CLAMP
00000011 HIGH-Z
01000001 SAMPLE-IN
01000010 SAMPLE-OUT
00100010 EXTEST-OUT
10101010 IDCODE

11111111 BYPASS
All Other BYPASS

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SCAN182374A

Description of BOUNDARY-SCAN Circuitry (Continued)

Scan Cell TYPE1

Scan Cell TYPE2

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SCAN182374A

Description of BOUNDARY-SCAN Circuitry (Continued)

BOUNDARY-SCAN Register

SCAN182374A Scan Chain Definition (42 Bits in Length)

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SCAN182374A

Description of BOUNDARY-SCAN Circuitry (Continued)

Input BOUNDARY-SCAN Register

Scan Chain Definition (22 Bits in Length)

When Sample In is Active

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SCAN182374A

Description of BOUNDARY-SCAN Circuitry (Continued)

Output BOUNDARY-SCAN Register

Scan Chain Definition (20 Bits in Length)

When Sample Out and EXTEST Out are Active

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SCAN182374A

Description of BOUNDARY-SCAN Circuitry (Continued)

BOUNDARY-SCAN Register Definition Index

Bit No. Pin Name Pin No. Pin Type Scan Cell Type

41 AOE

1

3 Input TYPE1

Control
Signals

40 ACP 54 Input TYPE1
39 AOE Internal TYPE2
38 BOE

1

26 Input TYPE1
37 BCP 31 Input TYPE1
36 BOE Internal TYPE2
35 AI

0

55 Input TYPE1

A–in

34 AI

1

53 Input TYPE1
33 AI

2

52 Input TYPE1
32 AI

3

50 Input TYPE1
31 AI

4

49 Input TYPE1
30 AI

5

47 Input TYPE1
29 AI

6

46 Input TYPE1
28 AI

7

44 Input TYPE1
27 AI

8

43 Input TYPE1
26 BI

0

42 Input TYPE1

B–in

25 BI

1

41 Input TYPE1
24 BI

2

39 Input TYPE1
23 BI

3

38 Input TYPE1
22 BI

4

36 Input TYPE1
21 BI

5

35 Input TYPE1
20 BI

6

33 Input TYPE1
19 BI

7

32 Input TYPE1
18 BI

8

30 Input TYPE1
17 AO

0

2 Output TYPE2

A–out

16 AO

1

4 Output TYPE2

15 AO

2

5 Output TYPE2

14 AO

3

7 Output TYPE2

13 AO

4

8 Output TYPE2

12 AO

5

10 Output TYPE2
11 AO

6

11 Output TYPE2
10 AO

7

13 Output TYPE2

9AO

8

14 Output TYPE2

8BO

0

15 Output TYPE2

B–out

7BO

1

16 Output TYPE2

6BO

2

18 Output TYPE2

5BO

3

19 Output TYPE2

4BO

4

21 Output TYPE2

3BO

5

22 Output TYPE2

2BO

6

24 Output TYPE2

1BO

7

25 Output TYPE2

0BO

8

27 Output TYPE2

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SCAN182374A

Absolute Maximum Ratings(Note 2) Recommended Operating

Conditions

Note 2: Absolute maximum ratings are values beyond which the device

may be damaged or have its useful life impaired . Functional operation
under these conditions is not implied.

Note 3: Either voltage lim it or c urrent limit is sufficient to protect inputs.

DC Electrical Characteristics

Note 4: Guaranteed not tested.

Storage Temperature −65°C to +150°C
Ambient Temperature under Bias

−55°C to +125°C

Junction Temperature under Bias

−55°C to +150°C

V

CC

Pin Potential to Ground Pin −0.5V to +7.0V

Input Voltage (Note 3)

−0.5V to +7.0V

Input Current (Note 3)

−30 mA to +5.0 mA

Voltage Applied to Any Output

in the Disabled or
Power-Off State

−0.5V to +5.5V

in the HIGH State

−0.5V to V

CC

Current Applied to Output

in LOW State (Max) Twice the Rated I

OL

(mA)

DC Latchup Source Current

−500 mA

Over Voltage Latchup (I/O) 10V
ESD (HBM) Min. 2000V

Free Air Ambient Temperature

−40°C to +85°C

Supply Voltage

+4.5V to +5.5V

Minimum Input Edge Rate (

∆V/∆t)

Data Input 50 mV/ns
Enable Input 20 mV/ns

Symbol Parameter

V

CC

Min Typ Max Units Conditions

V

IH

Input HIGH Voltage 2.0 V Recognized HIGH Signal

V

IL

Input LOW Voltage 0.8 V Recognized LOW Signal

V

CD

Input Clamp Diode Voltage Min −1.2 V IIN = −18 mA

V

OH

Output HIGH Voltage Min 2 .5 V IOH = −3 mA

Min 2.0 V IOH = −32 mA

V

OL

Output LOW Voltage Min 0.8 V IOL = 15 mA

I

IH

Input HIGH Current All Others Max 5 µAVIN = 2.7V (Note 4)

Max 5 µAVIN = V

CC

TMS, TDI Inputs Max 5 µAVIN = V

CC

I

BVI

Input HIGH Current Breakdown Test Max 7 µAVIN = 7.0V

I

BVIT

Input HIGH Current Breakdown Test (I/O) Max 100 µAVIN = 5.5V

I

IL

Input LOW Current All Others Max −5 µAVIN = 0.5V (Note 4)

Max −5 µAVIN = 0.0V

TMS, TDI Max −385 µAV

IN

= 0.0V

V

ID

Input Leakage Test 0.0 4.75 V IID = 1.9 µA

All Other Pins Grounded

I

IH

+ I

OZH

Output Leakage Current Max 50 µAV

OUT

= 2.7V

I

IL

+ I

OZL

Output Leakage Current Max −50 µAV

OUT

= 0.5V

I

OZH

Output Leakage Current Max 50 µAV

OUT

= 2.7V

I

OZL

Output Leakage Current Max −50 µAV

OUT

= 0.5V

I

OS

Output Short-Circuit Current Max −100 −275 mA V

OUT

= 0.0V

I

CEX

Output HIGH Leakage Current Max 50 µAV

OUT

= V

CC

I

ZZ

Bus Drainage Test 0.0 100 µAV

OUT

= 5.5V

All Others Grounded

I

CCH

Power Supply Current Max 250 µAV

OUT

= VCC; TDI, TMS = V

CC

Max 1.0 mA V

OUT

= VCC; TDI, TMS = GND

I

CCL

Power Supply Current Max 65 mA V

OUT

= LOW; TDI, TMS = V

CC

Max 65.8 mA V

OUT

= LOW; TDI, TMS = GND

I

CCZ

Power Supply Current Max 250 µA TDI, TMS = V

CC

Max 1.0 mA TDI, TMS = GND

I

CCT

Additional ICC/Input All Other Inputs Max 2.9 mA VIN = VCC − 2.1V

TDI, TMS Inputs Max 3 mA VIN = VCC − 2.1V

I

CCD

Dynamic I

CC

No Load Max 0.2 mA/ Outputs Open

MHz One Bit Toggling, 50% Duty Cycle

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SCAN182374A

AC Electrical Characteristics

Normal Operation

Note 5: Voltage Range 5.0V ± 0.5V

AC Operating Requirements

Normal Operation

Note 6: Voltage Range is 5.0V ± 0.5V.

AC Electrical Characteristics

Scan Test Operation

Note 7: Voltage Range 5.0V ± 0.5V

Symbol Parameter

V

CC

TA = −40°C to +85°C

Units

(V)

CL = 50 pF

(Note 5) Min Typ Max

t

PLH

Propagation Delay

5.0

1.4 4.6 6.1
ns

t

PHL

CP to Q 2.1 4.9 6.8

t

PLZ

Disable Time

5.0

1.9 4.6 8.0
ns

t

PHZ

1.8 4.8 8.7

t

PZL

Enable Time

5.0

2.0 6.7 9.4
ns

t

PZH

1.4 6.0 8.2

Symbol Parameter

V

CC

TA = −40°C to +85°C

Units

(V)

C

L

= 50 pF

(Note 6) Guaranteed Minimum

t

S

Setup Time, H or L

5.0 2.8 ns

Data to CP

t

H

Hold Time, H or L

5.0 2.4 ns

CP to Data

t

W

CP Pulse Width 5.0 0.0 ns

f

MAX

Maximum ACP/BCP

5.0 50 MHz

Clock Frequency

Symbol Parameter

V

CC

TA = −40°C to +85°C

Units

(V)

CL = 50 pF

(Note 7) Min Typ Max

t

PLH

Propagation Delay

5.0

2.9 5.8 9.5
ns

t

PHL

TCK to TDO 4.0 7.3 11.5

t

PLZ

Disable Time

5.0

1.9 5.6 10.0
ns

t

PHZ

TCK to TDO 3.0 7.1 12.1

t

PZL

Enable Time

5.0

4.4 8.4 13.2
ns

t

PZH

TCK to TDO 2.7 6.4 10.9

t

PLH

Propagation Delay

5.0

3.4 6.5 10.5
ns

t

PHL

TCK to Data Out during Update-DR State 4.3 8.1 12.7

t

PLH

Propagation Delay

5.0

3.9 7.8 12.8
ns

t

PHL

TCK to Data Out during Update-IR State 4.7 9.1 14.5

t

PLH

Propagation Delay

5.0

4.7 9.5 15.6
ns

t

PHL

TCK to Data Out during Test Logic Reset State 5.6 10.9 17.4

t

PLZ

Disable Time

5.0

3.2 7.8 13.6
ns

t

PHZ

TCK to Data Out during Update-DR State 3.9 8.5 14.2

t

PLZ

Disable Time

5.0

3.2 8.6 15.0
ns

t

PHZ

TCK to Data Out during Update-IR State 3.8 9.3 15.6

t

PLZ

Disable Time

5.0

4.2 10.2 18.0
ns

t

PHZ

TCK to Data Out during Test Logic Reset State 5.0 11.0 18.5

t

PZL

Enable Time

5.0

5.0 9.6 15.3
ns

t

PZH

TCK to Data Out during Update-DR State 3.7 7.7 13.0

t

PZL

Enable Time

5.0

5.3 10.8 17.4
ns

t

PZH

TCK to Data Out during Update-IR State 4.0 9.0 15.1

t

PZL

Enable Time

5.0

6.2 12.6 20.4
ns

t

PZH

TCK to Data Out during Test Logic Reset State 4.7 10.7 18.1

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SCAN182374A

AC Operating Requirements

Scan Test Operation

Note 8: Voltage Range 5.0V ± 0.5V
Note 9: This delay represents the t im ing relationship be tween the data input an d T C K at t he associated scan ce lls numbered 0–8, 9–17, 18–26 and 27–35.
Note 10: Timing pertains to BSR 38 and 41 only.
Note 11: This delay represents the timing relationship between AOE/BOE and TCK for scan cells 36 and 39 only.
Note 12: Timing pertains to BSR 37 and 40 only.
Note: All Input Timing Delays involving TCK are measured from the rising edge of TCK.

Capacitance

TA = 25°C

Note 13: C

OUT

is measured at frequency f = 1 MHz, per MIL-STD-883B, Method 3012.

Symbol Parameter

V

CC

TA = −40°C to +85°C

Units

(V)

CL = 50 pF

(Note 8) Guaranteed Minimum

t

S

Setup Time

5.0 2.7 ns

Data to TCK (Note 9)

t

H

Hold Time

5.0 3.1 ns

Data to TCK (Note 9)

t

S

Setup Time, H or L

5.0 5.0 ns

AOE

1

, BOE1 to TCK (Note 10)

t

H

Hold Time, H or L

5.0 1.8 ns

TCK to AOE1, BOE1 (Note 10)

t

S

Setup Time, H or L

5.0 3.6 ns

Internal AOE, BOE to TCK (Note 11)

t

H

Hold Time, H or L

5.0 2.1 ns

TCK to Internal AOE, BOE (Note 11)

t

S

Setup Time

5.0 3.4 ns

ACP, BCP (Note 12) to TCK

t

H

Hold Time

5.0 1.8 ns

TCK to ACP, BCP (Note 12)

t

S

Setup Time, H or L

5.0 8.7 ns

TMS to TCK

t

H

Hold Time, H or L

5.0 1.8 ns

TCK to TMS

t

S

Setup Time, H or L

5.0 6.4 ns

TDI to TCK

t

H

Hold Time, H or L

5.0 3.2 ns

TCK to TDI

t

W

Pulse Width TCK H

5.0

8.2
ns

L11.2

f

MAX

Maximum TCK Clock Frequency 5.0 50 MHz

t

PU

Wait Time, Power Up to TCK 5.0 100 ns

t

DN

Power Down Delay 0.0 100 ms

Symbol Parameter Typ Units Conditions

C

IN

Input Capacitance 5.8 pF VCC = 0.0V

C

OUT

(Note 13) Output Capacitance 13.8 pF VCC = 5.0V

www.fairchildsemi.com 12

SCAN182374A D-Type Flip-Flop with 25

Ω

Series Resistor Outputs

Physical Dimensions inches (millimeters) unless otherwise noted

56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide

Package Number MS56A

Fairchild does not assume any responsibility for use of any circuitr y described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:

1. Life suppor t de vices o r syste ms a re device s or syste ms
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea­sonably expected to result in a significant inju ry to the
user.

2. A cri tical compon ent in any com ponen t of a life su pport
device or system whose failure t o perform can be rea­sonably expected to ca use the failure of the life supp ort
device or system, or to affect its safety or effectiveness.

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