Datasheet SAA5284GP, SAA5284GP-M1 Datasheet (Philips)

DATA SH EET

Objective specification
Supersedes data of 1997 Mar 03
File under Integrated Circuits, IC22

1998 Feb 05

INTEGRATED CIRCUITS

SAA5284

Multimedia video data acquisition
circuit

1998 Feb 05 2

Philips Semiconductors Objective specification

Multimedia video data acquisition circuit SAA5284

CONTENTS

1 FEATURES
2 GENERAL DESCRIPTION
3 QUICK REFERENCE DATA
4 ORDERING INFORMATION
5 MAIN FUNCTIONAL BLOCKS
6 BLOCK DIAGRAM
7 PINNING INFORMATION

7.1 Pinning

7.2 Pin description
8 FUNCTIONAL DESCRIPTION

8.1 Power supply strategy

8.2 Clocking strategy

8.3 Power-on reset

8.4 Analog switch

8.5 Analog video-to-data byte converter

8.6 Packet filtering

8.7 Packet buffer

8.8 FIFO

8.9 Host interface

8.10 Interrupt support

8.11 DMA support

8.12 I2C-bus interface
9 LIMITING VALUES
10 QUALITY & RELIABILITY
11 CHARACTERISTICS
12 TIMING
13 APPLICATION INFORMATION

13.1 Hardware application circuit for ISA card

13.2 Hardware application circuit for PCI application

13.3 Software application information
14 PACKAGE OUTLINE
15 SOLDERING

15.1 Introduction

15.2 Reflow soldering

15.3 Wave soldering

15.4 Repairing soldered joints
16 DEFINITIONS
17 LIFE SUPPORT APPLICATIONS
18 PURCHASE OF PHILIPS I2C COMPONENTS

1998 Feb 05 3

Philips Semiconductors Objective specification

Multimedia video data acquisition circuit SAA5284

1 FEATURES

• High performance multi-standard data slicer

• Intercast (Intel Corporation) compatible

• Teletext (WST, Chinese teletext) (625 lines)

• Teletext (US teletext, NABTS and MOJI) (525 lines)

• Wide Screen Signalling (WSS), Video Programming

Signal (VPS)

• Closed Caption (Europe, US)

• Data broadcast, PDC (packet 30 and 31)

• User programmable data format (programmable framing

code)

• 2 kbytes data cache on-chip to avoid data loss and
reduce host CPU overhead

• Filtering of packets 30 and 31 WST/NABTS

• Choice of clock frequencies, direct-in clock or crystal

oscillator

• Parallel interface, Motorola, Intel and digital video bus

• I

2

C-bus control

• Data transport by digital video bus

• Choice of programmable interrupt, DMA or polling

driven

• Data type selectable video line by video line, with
Vertical Blanking Interval and Full Field mode

• Single IC with few external components and small
footprint QFP44 package

• Optimized for EMC.

2 GENERAL DESCRIPTION

The SAA5284 is a Vertical Blanking Interval (VBI) and Full
Field (FF) video data acquisition device tailored for
application on PC add-in cards, PC mother-boards, set-top
boxes and as a SAA5250 replacement. The IC in
combination with a range of software modules will acquire
most existing formats of broadcast VBI and FF data.

These associated software modules are available under
licence. Scope is provided for acquiring some as yet
unspecified formats. The SAA5284 incorporates all the
data slicing, parallel interface, data filtering and control
logic. It is controlled either by a parallel interface or
I

2

C-bus. It can output ASCII VBI data as pixels on the
digital video bus where no parallel port is available. It is
available in a QFP44 package.

3 QUICK REFERENCE DATA

Note

1. Selectable: 12, 13.5, 15 or 16 MHz.

4 ORDERING INFORMATION

SYMBOL PARAMETER MIN. TYP. MAX. UNIT

V

DD

supply voltage 4.5 5.0 5.5 V

I

DD

supply current − 72 95 mA

V

sync(p-p)

sync voltage (peak-to-peak value) 0.1 0.3 0.6 V

V

i(CVBS)(p-p)

input voltage on pin CVBS0 and CVBS1
(peak-to-peak value)

0.7 1.0 1.4 V

f

xtal

crystal frequency; see note 1 − 12.0 − MHz

T

amb

operating ambient temperature −20 − +70 °C

TYPE NUMBER

PACKAGE

NAME DESCRIPTION VERSION

SAA5284GP QFP44 plastic quad flat package; 44 leads (lead length 2.35 mm);

body 14 × 14 × 2.2 mm

SOT205-1

1998 Feb 05 4

Philips Semiconductors Objective specification

Multimedia video data acquisition circuit SAA5284

5 MAIN FUNCTIONAL BLOCKS

1. Input clamp and sync separator

2. Analog-to-digital converter

3. Multi-standard data slicer and clock regenerator

4. Packet filtering; (8 and 4) Hamming correction

5. On-chip data cache

6. Line selectable data type

7. 12, 13.5, 15 and 16 MHz clock or oscillator options

8. FIFO access to data

9. Interrupt and DMA support

10. Multi-standard parallel interface

11. I

2

C-bus interface

12. Power-on reset.
Figure 1 shows a block diagram of the SAA5284.

6 BLOCK DIAGRAM

Fig.1 Block diagram.

handbook, full pagewidth

MGG740

ANALOG

SWITCH

SAA5284

MULTI-STANDARD
HOST INTERFACE

I2C-BUS

INTERFACE

400 kHz

SLAVE

FIFO

PACKET BUFFER AND

FRONT END CONTROL

REGISTERS

PACKET

FILTERING (e.g.

WST packets

30/31)

ANALOG

VIDEO TO

DATA BYTE

CONVERTER

(DATA

DEMODULATOR)

OSCILLATOR

AND TIMING

OSCOUT OSCGND

OSCIN

PACKET BUFFER RAM

2 kbyte

(45 packets)

35
44
31
32
10

33 34424323938 36 37

11

3

SDA

SCL

4

5

30 to 28
20 to 27

WR

(1)

16

15
14

V

DDAVSSAVDDXVDDDVSSD3

RESET

17 6

41 40 1

VPOIN0 HREF

VPOIN1

LLC

LLC2

RD

(1)

DMACK

(1)

DMARQ

CVBS0
CVBS1

V

SSD1

V

SSD2

data path
control

13

12

789 18 19

I

REF

BLACK

8

3

D7 to D0

(1)

A2 to A0

(1)

RDY

(1)

SEL1

SEL0

INT

CS1

DENB

CS0

(1) Multi-functional pins, see Chapter 7.

1998 Feb 05 5

Philips Semiconductors Objective specification

Multimedia video data acquisition circuit SAA5284

7 PINNING INFORMATION

7.1 Pinning

7.2 Pin description
Table 1 QFP44 package

The IC has a total of 44 pins; many of these are multi-functional due to the multiple host block modes of operation.

SYMBOL PIN I/O DESCRIPTION

RESET 1 I reset IC
HREF 2 I video horizontal reference signal (digital video mode only)
SDA 3 I/O serial data port for I

2

C-bus, open-drain
SCL 4 I serial clock input for I2C-bus
DENB 5 O data enable bar (for external buffers)
V

DDX

6 − +5 V supply
OSCOUT 7 O oscillator output
OSCIN 8 I oscillator input

Fig.2 Pin configuration.

(1) Multi-functional pin.

handbook, full pagewidth

1
2
3
4

5
6
7

8

9

10
11

33
32
31
30
29
28
27
26
25
24
23

12

13

14

15

16

17

18

19

20

21

22

44

43

42

41

40

39

38

37

36

35

34

SAA5284

MGG739

WR

(1)

RDY

(1)

INT
A2

(1)

A0

(1)

D0

(1)

D1

(1)

D2

(1)

D3

(1)

D4

(1)

RESET

HREF

SDA

SCL
DENB
V

DDX

OSCIN

OSCGND

SEL1

A1

(1)

LLC2

LLC

V

DDD

V

SSD3

VPOIN1

VPOIN0

DMARQ

CS0

RD

(1)

CS1

DMACK

(1)

I

REF

CVBS1

CVBS0

V

DDA

V

SSA

V

SSD1

D7

(1)

D6

(1)

D5

(1)

BLACK

V

SSD2

OSCOUT

SEL0

1998 Feb 05 6

Philips Semiconductors Objective specification

Multimedia video data acquisition circuit SAA5284

Note

1. These pins have two functions, depending on the interface mode.

OSCGND 9 − oscillator ground
SEL0 10 I parallel interface format select 0
SEL1 11 I parallel interface format select 1
BLACK 12 I/O video black level storage; connected to V

SSA

via 100 nF capacitor

I

REF

13 I reference current input; connected to V

SSA

via 27 kΩ resistor
CVBS1 14 I analog composite video input 1
CVBS0 15 I analog composite video input 0
V

DDA

16 − analog +5 V supply

V

SSA

17 − analog ground supply

V

SSD1

18 I digital ground supply 1

V

SSD2

19 I digital ground supply 2

D7

(1)

20 I/O data bus 7/video data output 7

D6

(1)

21 I/O data bus 6/video data output 6

D5

(1)

22 I/O data bus 5/video data output 5

D4

(1)

23 I/O data bus 4/video data output 4

D3

(1)

24 I/O data bus 3/video data output 3

D2

(1)

25 I/O data bus 2/video data output 2

D1

(1)

26 I/O data bus 1/video data output 1

D0

(1)

27 I/O data bus 0/video data output 0

A0

(1)

28 I address input 0/video data input 7

A1

(1)

29 I address input 1/video data input 6

A2

(1)

30 I address input 2/video data input 5
INT 31 O interrupt request
RDY

(1)

32 O ready/DTACK (data acknowledge)/VBI, open-drain
WR

(1)

33 I Intel bus Write/Motorola bus R/W/video data input 4
RD

(1)

34 I Intel bus Read/Motorola bus LDS/video data input 3
CS0 35 I chip select 0; active LOW
DMARQ 36 O DMA request
DMACK

(1)

37 I DMA acknowledge/video data input 2
VPOIN0 38 I video data input 0
VPOIN1 39 I video data input 1
V

SSD3

40 − digital ground supply 3
V

DDD

41 − digital +5 V supply
LLC 42 I full rate digital video clock input
LLC2 43 I half rate digital video clock input
CS1 44 I chip select 1; active LOW

SYMBOL PIN I/O DESCRIPTION

1998 Feb 05 7

Philips Semiconductors Objective specification

Multimedia video data acquisition circuit SAA5284

8 FUNCTIONAL DESCRIPTION

8.1 Power supply strategy

There are three separate +5 V (V

DD

) connections to the IC:

1. V

DDA

supplies the critical noise-sensitive analog
front-end sections: ADC and sync separator, to reduce
interference from the rest of the front-end

2. V

DDX

supplies all sections which take standing DC
current

3. V

DDD

supplies the rest of the logic.

8.2 Clocking strategy

The master frequency reference for the IC is a
12, 13.5, 15 or 16 MHz crystal oscillator. The tolerance on
the clock frequency is 500 × 10

−6

(1.5 kHz). Further

specifications of the crystal are given in Table 2.
If preferred, an external 12, 13.5, 15 or 16 MHz (±1.5 kHz)

frequency source may be connected to OSCIN instead of
the crystal.

8.3 Power-on reset

The RESET pin should be held HIGH for a minimum of two
clock cycles. The reset signal is passed through a Schmitt
trigger internally.

Direct addressed registers (i.e. those addressed using the
A0 to A2 pins) are set to 00H after power-up. All other
register bits are assumed to be in random states after
power-up.

8.4 Analog switch

Register bit selection between two video sources.

8.5 Analog video-to-data byte converter

This section comprises a line and field sync separator, a
video clamp, an ADC and a custom adaptive digital filter
with DPLL based timing circuit.

The analog video-to-data byte converter is specifically
designed to overcome the most commonly found types of
distortion of a broadcast video signal. It is also fully
multi-standard. The data type to be demodulated is
programmable on a line-by-line basis using 4 register bits
per line for lines 2 to 23 (PAL numbering),
fields 1 and 2, and 4 further bits for all lines combined.

8.6 Packet filtering

If using a slow (e.g. 80C51) microcontroller, it is necessary
to reduce the amount of data acquired by SAA5284 before
downloading to the microcontroller to avoid it being
swamped by unwanted data. Packet filtering is available
for this purpose. A common use of this would be to acquire
only packet 8/30 in 625-line WST. The packet filter
includes optional (8, 4) Hamming correction.

8.7 Packet buffer

This is a 2 kbyte RAM which acts as a buffer for storing
received packets. The first 44 bytes are reserved for
control information. The rest of the RAM is divided into
44-byte rows (or packets), each holding the data received
on one incoming CVBS line. In the case of a WST packet
received, the data stored consists of a Magazine and
Row-Address Group (2 bytes), followed by the 40 bytes of
packet data. When data in other formats than WST is
received, this is stored in the packet buffer in the same
way. In each case, the data is preceded by two information
bytes which record on which line and field the packet was
received, and what the data type is.

8.8 FIFO

FIFO hardware is provided to manage the ‘read’ address
for the host processor, i.e. data is read repeatedly from the
same 8-bit port, and appears byte-serially in the order of
reception. The read address can be reset to the start of the
packet buffer (the first 44-byte packet), back to the start of
the current packet, or incremented to the start of the next
packet.

Table 2 Crystal characteristics

SYMBOL PARAMETER MIN. TYP. MAX. UNIT

C1 series capacitance − 18.5 − fF
C2 parallel capacitance − 4.9 − pF

R

r

resonant resistance −−50 Ω

X

a

ageing −−5×10

−6

per year

X

j

adjustment tolerance −−25 × 10−6−

X

d

drift −−25 × 10−6−

1998 Feb 05 8

Philips Semiconductors Objective specification

Multimedia video data acquisition circuit SAA5284

8.9 Host interface

The SAA5284 has a multi-standard 8-bit I/O interface.
To reduce the amount of host I/O space used, the parallel
interface has only 3 address inputs (A0, A1 and A2).
An extended addressing (pointer) scheme and the data
FIFO are used to allow access to the full set of SAA5284
registers and the full span of the packet buffer.

As well as the 8 data I/O lines and 3 address lines, there
are the following control signals: RD (read LOW), WR
(write LOW), CS0 (chip select LOW), CS1(second chip
select LOW), INT (interrupt request), DMARQ (DMA
request), DMACK (DMA acknowledge) and RDY (ready).

In order to maintain compatibility with Motorola and Intel
type buses, two control signals SEL0 and SEL1 are
provided to configure the host interface. These signals
allow configuration of the host interface to work with the
Motorola or Intel style interfaces.

The host interface has a digital video mode. Digital video
mode may be used to allow the SAA5284 to pass decoded
VBI data into a system using the digital video bus.

8.10 Interrupt support

The host interface provides comprehensive support for
interrupt generation. The interrupt may be programmed to
occur when a particular number of packets of VBI data are
available in the cache RAM. The interrupts can be further
controlled to occur on a specific line in the TV frame.
The interrupts can also be self masking if required.

8.11 DMA support

Burst and demand mode DMA are supported. In burst
mode, the number of packets to transfer can be defined.
An interrupt can be generated when DMA is finished. This
can be self masking.

8.12 I

2

C-bus interface

The I2C-bus interface functions as a slave receiver or
transmitter at up to 400 kHz. The I2C-bus address is
selectable as 20H or 22H. All functionality is available
using the I2C-bus although with a slower data transfer
speed. It is possible to use the I2C-bus in all modes.

9 LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

10 QUALITY & RELIABILITY

In accordance with

“SNW-FQ-611-E”

.

SYMBOL PARAMETER MIN. MAX. UNIT

V

DD

supply voltage (all supplies) −0.3 +6.5 V

V

I(max)

input voltage (any input) −0.3 VDD+ 0.5 V

V

O(max)

output voltage (any output) −0.3 VDD+ 0.5 V

∆V

DDD−DDA−DDX

supply voltage difference between V

DDD

, V

DDA

and V

DDX

− 0.25 V

I

IOK

DC input or output diode current − 20 mA

I

O(max)

output current (any output) − 10 mA

T

stg

storage temperature −55 +125 °C

T

amb

operating ambient temperature −20 +70 °C

1998 Feb 05 9

Philips Semiconductors Objective specification

Multimedia video data acquisition circuit SAA5284

11 CHARACTERISTICS

T

amb

= −20 to +70 °C; VDD= 4.5 to 5.5 V; unless otherwise specified.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX.

UNIT

Power supply

V

DDn

supply voltage 4.5 5.0 5.5 V

I

DD(tot)

total supply current − 72 95 mA

I

DDD

digital supply current − 32 42 mA

I

DDA

analog supply current − 40 53 mA

Inputs CVBS0 and CVBS1

V

sync(p-p)

sync voltage
(peak-to-peak value)

0.1 0.3 0.6 V

V

burst(p-p)

colour burst voltage
(peak-to-peak value)

0 0.3 0.4 V

V

i(vid)(p-p)

video input voltage
(peak-to-peak value)

0.7 1.0 1.4 V

V

i(data)(p-p)

teletext data input voltage
(peak-to-peak value)

0.29 0.46 0.71 V

Z

source

source impedance −−250 Ω

V

i(sw)

input switching level of sync
separator

1.5 1.8 2.1 V

Z

i

input impedance 2.5 5.0 − kΩ

C

i

input capacitance −−10 pF

Input I

REF

R

IREF

external resistor to V

SSA

− 27 − kΩ

Inputs RESET, HREF, SEL0, SEL1, A0, A1, A2, WR, RD,

CS0, CS1, DMACK, VPOIN1, VPOIN0, LLC and LLC2

V

IL

LOW-level input voltage −0.3 − +0.8 V

V

IH

HIGH-level input voltage 2.0 − VDD+ 0.5 V

I

LI

input leakage current Vi= 0 to V

DD

−10 − +10 µA

C

i

input capacitance −−10 pF

Input SCL

V

IL

LOW-level input voltage −0.5 − +1.5 V

V

IH

HIGH-level input voltage 3.0 − VDD+ 0.5 V

I

LI

input leakage current Vi= 0 to V

DD

−10 − +10 µA

C

i

input capacitance − 10 pF

t

i(r)

input rise time V

IL(min)

to V

IH(max)

; f

i(SCL)

= 100 kHz 50 − 1000 ns

V

IL(min)

to V

IH(max)

; f

i(SCL)

= 400 kHz 50 − 300 ns

t

i(f)

input fall time V

IL(max)

to V

IH(min)

; f

i(SCL)

= 100 kHz 50 − 300 ns

V

IL(max)

to V

IH(min)

; f

i(SCL)

= 400 kHz 50 − 300 ns

f

i(SCL)

input clock frequency 0 − 400 kHz

C

L

load capacitance −−400 pF

1998 Feb 05 10

Philips Semiconductors Objective specification

Multimedia video data acquisition circuit SAA5284

Input/output SDA (open-drain)

V

IL

LOW-level input voltage −0.5 − +1.5 V

V

IH

HIGH-level input voltage 3.0 − VDD+ 0.5 V

I

LI

input leakage current VI=0toV

DD

−10 − +10 µA

C

i

input capacitance − 10 pF

t

i(r)

input rise time V

IL(min)

to V

IH(max)

; f

i(SCL)

= 100 kHz 50 − 1000 ns

V

IL(min)

to V

IH(max)

; f

i(SCL)

= 400 kHz 50 − 300 ns

t

i(f)

input fall time V

IL(max

)toV

IH(min)

; f

i(SCL)

= 100 kHz 50 − 300 ns

V

IL(max)

to V

IH(min)

; f

i(SCL)

= 400 kHz 50 − 300 ns

V

OL

LOW-level output voltage IOL= 3 mA 0 − 0.4 V

I

OL

= 6 mA 0 − 0.6 V

t

o(f)

output fall time between 3 and 1.5 V; IOL=3mA 50 − 250 ns

C

L

load capacitance −−400 pF

Input/output BLACK

C

BLACK

storage capacitance to V

SSA

− 100 − nF

Inputs/outputs D7 to D0

V

IL

LOW-level input voltage −0.3 − +0.8 V

V

IH

HIGH-level input voltage 2.0 − VDD+ 0.5 V

I

LI

input leakage current VIN= 0 to V

DD

−10 − +10 µA

C

i

input capacitance −−10 pF

V

OL

LOW-level output voltage IOL= +1.6 mA 0 − 0.4 V

V

OH

HIGH-level output voltage IOH= −0.2 mA 2.4 − V

DD

V

C

L

load capacitance −−tbf pF

t

o(r)

output rise time into C

L

0.6 to 2.2 V −−tbf ns

t

o(f)

output fall time into C

L

2.2 to 0.6 V −−tbf ns

Outputs INT, DENB and DMARQ

V

OL

LOW-level output voltage IOL= +1.6 mA 0 − 0.4 V

V

OH

HIGH-level output voltage IOH= −0.2 mA 2.4 − V

DD

V

C

L

load capacitance −−tbf pF

t

o(r)

output rise time into C

L

0.6 to 2.2 V −−tbf ns

t

o(f)

output fall time into C

L

2.2 to 0.6 V −−tbf ns
RDY (open-drain); note 1
V

OL

LOW-level output voltage IOL= +1.6 mA 0 − 0.4 V

C

L

load capacitance −−tbf pF

t

o(r)

output rise time into C

L

0.6 to 2.2 V −−tbf ns
t

o(f)

output fall time into C

L

2.2 to 0.6 V −−tbf ns

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX.

UNIT

1998 Feb 05 11

Philips Semiconductors Objective specification

Multimedia video data acquisition circuit SAA5284

Notes

1. ESD protection of this pin falls below the Philips General Quality Specification (GQS). Therefore it is recommended
that a diode is connected from pin RDY to V

DDD

.

2. The I2C-bus interface pins SDA and SCL may pull the data and clock lines below 3 V while the digital power supply
V

DDD

is in the range 0.4 to 0.8 V.

I2C-bus timings (see note 2 and Fig.8)
f

i(SCL)

SCL input clock frequency f

i(SCL)

= 100 kHz 0 − 100 kHz

f

i(SCL)

= 400 kHz 0 − 400 kHz

t

LOW

SCL LOW time f

i(SCL)

= 100 kHz 4.7 −− µs

f

i(SCL)

= 400 kHz 1.3 −− µs

t

HIGH

SCL HIGH time f

i(SCL)

= 100 kHz 4.0 −− µs

f

i(SCL)

= 400 kHz 0.6 −− µs

t

SU;DAT

data set-up time f

i(SCL)

= 100 kHz 250 −− ns

f

i(SCL)

= 400 kHz 100 −− ns

t

HD;DAT

data hold time f

i(SCL)

= 100 kHz 0 −− µs

f

i(SCL)

= 400 kHz 0 −− µs

t

SU;STO

set-up time STOP condition f

i(SCL)

= 100 kHz 4.7 −− µs

f

i(SCL)

= 400 kHz 0.6 −− µs

t

BUF

bus free time f

i(SCL)

= 100 kHz 4.7 −− µs

f

i(SCL)

= 400 kHz 1.3 −− µs

t

HD;STA

hold time START condition f

i(SCL)

= 100 kHz 4.0 −− µs

f

i(SCL)

= 400 kHz 0.6 −− µs

t

SU;STA

set-up time repeated START f

i(SCL)

= 100 kHz 4.7 −− µs

f

i(SCL)

= 400 kHz 0.6 −− µs

t

r

rise time (SDA and SCL) f

i(SCL)

= 100 kHz −−1000 ns

f

i(SCL)

= 400 kHz −−300 ns

t

f

fall time (SDA and SCL) f

i(SCL)

= 100 kHz −−300 ns

f

i(SCL)

= 400 kHz −−300 ns

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX.

UNIT

1998 Feb 05 12

Philips Semiconductors Objective specification

Multimedia video data acquisition circuit SAA5284

12 TIMING

Fig.3 Intel mode interface read cycle timing.

handbook, full pagewidth

MGK145

D7 to D0

A2 to A0

RD

RDY

CS0 or CS1

t

1

t

5

t

6

t

3

t

7

t

2

t

4

t

0

valid address

valid data

B

(2)

A

(1)

3-state3-state

(1) Event A occurs when RD + CS0 + CS1 = 0 (boolean).
(2) Event B occurs when RD + CS0 + CS1 = 1 (boolean).

Table 3 Intel-mode interface read cycle timing (12 MHz clock)

SYMBOL DESCRIPTION MIN. MAX. UNIT

t

0

minimum cycle time 333 833 ns

t

1

address set-up time before event A 0 − ns

t

2

address hold time after event B 0 − ns

t

3

data settling time 88 712 ns

t

4

data hold time after event B 0 − ns

t

5

time from event A until RDY goes LOW 83 170 ns

t

6

RDY LOW time 83 530 ns

t

7

event B to next event A time 83 − ns

1998 Feb 05 13

Philips Semiconductors Objective specification

Multimedia video data acquisition circuit SAA5284

Fig.4 Intel mode interface write cycle timing.

handbook, full pagewidth

MGK146

D7 to D0

A2 to A0

WR

RDY

CS0 or CS1

t

1

t

5

t

6

t

3

t

2

t

4

t

0

B

(2)

A

(1)

t

7

valid address

valid data

(1) Event A occurs when WR + CS0 + CS1 = 0 (boolean).
(2) Event B occurs when WR + CS0 + CS1 = 1 (boolean).

Table 4 Intel-mode interface write cycle timing (12 MHz clock)

Note

1. Legacy AT bus PCs may not satisfy this requirement as they are not ISA compatible. An application fix is available
in the

“SAA5284 Users Guide”

.

SYMBOL DESCRIPTION MIN. MAX. UNIT

t

0

minimum cycle time 333 833 ns

t

1

address set-up time 0 − ns

t

2

address hold time 0 − ns

t

3

data set-up time, note 1 0 − ns

t

4

data hold time 0 − ns

t

5

RDY set-up time 83 170 ns

t

6

RDY LOW time 83 530 ns

t

7

event B to next event A time 83 − ns

1998 Feb 05 14

Philips Semiconductors Objective specification

Multimedia video data acquisition circuit SAA5284

handbook, full pagewidth

MGK147

t

7

t

2

t

5

t

3

t

6

t

4

t

1

D7 to D0

RD

(1)

DMACK

DMARQ

valid data valid data

CS

(same signal

as DMACK)

Fig.5 Intel mode interface DMA cycle timing.

(1) Read data pipelined, so no RD LOW to data valid set-up time.

Table 5 Intel-mode interface DMA cycle timing (12 MHz clock)

Note

1. This timing will be up to 3 clock cycles for the first read in DMA transfer.

SYMBOL DESCRIPTION MIN. MAX. UNIT

t

1

DMARQ to DMACK 0 − ns

t

2

RD LOW to DMARQ LOW 0 212 ns

t

3

cycle time 252 − ns

t

4

DMACK to RD active − 0ns

t

5

data set-up time 0 90

(1)

ns

t

6

data hold time 83 − ns

t

7

data hold from DMACK HIGH 0 83 ns

1998 Feb 05 15

Philips Semiconductors Objective specification

Multimedia video data acquisition circuit SAA5284

Fig.6 Motorola mode interface read cycle timing.

(1) Event A occurs when LDS + CS0 + CS1 = 0 (boolean).
(2) Event B occurs when LDS + CS0 + CS1 = 1 (boolean).

handbook, full pagewidth

MGK148

D7 to D0

A2 to A0

LDS

A

(1)

B

(2)

DTACK

t

1

t

2

t

6

t

4

t

5

t

3

t

7

t

0

valid address

valid data 3-state3-state

R/W

CS1 or CS0

Table 6 Motorola-mode interface read cycle timing (12 MHz clock)

SYMBOL DESCRIPTION MIN. MAX. UNIT

t

0

minimum cycle time 333 833 ns

t

1

address set-up time before event A 0 − ns

t

2

address hold time after event B 0 − ns

t

3

data hold time from event B 0 − ns

t

4

data settling time 88 712 ns

t

5

data valid to DTACK LOW 83 170 ns

t

6

LDS HIGH to DTACK HIGH 83 212 ns

t

7

delay between cycles 83 − ns

1998 Feb 05 16

Philips Semiconductors Objective specification

Multimedia video data acquisition circuit SAA5284

Fig.7 Motorola mode interface write cycle timing.

handbook, full pagewidth

MGK149

D7 to D0

A2 to A0

LDS

A

(1)

B

(2)

DTACK

t

1

t

2

t

6

t

4

t

5

t

3

t

0

valid address

valid data 3-state3-state

R/W

CS1 or CS0

t

7

(1) Event A occurs when LDS + CS0 + CS1 = 0 (boolean).
(2) Event B occurs when LDS + CS0 + CS1 = 1 (boolean).

Table 7 Motorola-mode interface write cycle timing (12 MHz clock)

SYMBOL DESCRIPTION MIN. MAX. UNIT

t

0

minimum cycle time 333 417 ns

t

1

address set-up time before event A 0 − ns

t

2

address hold time after event B 0 − ns

t

3

data hold time from event B 0 − ns

t

4

data set-up time 0 − ns

t

5

DTACK set-up time − 212 ns

t

6

LDS HIGH to DTACK HIGH 83 212 ns

t

7

delay between cycles 83 − ns

1998 Feb 05 17

Philips Semiconductors Objective specification

Multimedia video data acquisition circuit SAA5284

Fig.8 I2C-bus timing diagram.

handbook, full pagewidth

MGG741

SCL

SDA

t

SU;STA

t

BUF

t

SU;DAT

t

HIGH

t

LOW

t

HD;DAT

t

r

t

f

t

SU;STO

t

HD;STA

Fig.9 Digital video mode interface timing.

handbook, full pagewidth

MGK150

VPOIN

VPOOUT

LLC

LLC2

t

0

t

1

t

4

t

2

t

3

CS0 or CS1

Table 8 Digital video mode interface timing with 13.5 MHz clock and 27 MHz LLC

SYMBOL DESCRIPTION MIN. TYP. MAX. UNIT

t

0

VPOIN set-up time 4 5 6 ns

t

1

VPOOUT set-up time 8 10 22 ns

t

2

CS HIGH to VPOOUT 3-state 6 10 25 ns

t

3

CS LOW to VPOOUT enabled 9 11 16 ns

t

4

clock qualifier set-up time − 1.1 − ns

1998 Feb 05 18

Philips Semiconductors Objective specification

Multimedia video data acquisition circuit SAA5284

13 APPLICATION INFORMATION

13.1 Hardware application circuit for ISA card

A typical application circuit diagram (for the ISA card
application) is shown in Fig.10.

13.2 Hardware application circuit for PCI application

This PCI application is based around the Philips SAA7146
video to PCI bridge IC. SAA7146 has a ‘Data Expansion
Bus Interface’ (DEBI) which is an Intel/Motorola style
16-bit parallel interface. This is used to facilitate
communications to SAA5284.

The application circuit diagram is shown in Fig.11.

13.3 Software application information

PC application software is available providing two levels of
interface. At a low level a VxD based driver offers generic
packet gathering and buffering. Full support is provided for
ISA based applications with facility for PCI based
applications. Higher level support is provided by a series
of DLLs. These perform normal teletext display generation
and page management.

1998 Feb 05 19

Philips Semiconductors Objective specification

Multimedia video data acquisition circuit SAA5284

Fig.10 Application circuit diagram for ISA card.

(1) Option of 13.5, 15 and 16 MHz or direct feed from external clock.
(2) A diode to V

DDD

is recommended for ESD protection.

(3) Pin DMACK must be connected to V

DDD

if DMA is not used.

handbook, full pagewidth

MGG742

75 Ω

75 Ω

27 kΩ

22
pF

100 nF

BLACK

I

REF

V

SSAVSSD3VSSD1VSSD2

V

SSA

= 0 V

V

SSD

= 0 V

V

SSD

= 0 V

supply decoupling

SEL1 SEL0 CS1

CVBS0

CVBS1

OSCIN

OSCOUT

OSCGND

SDA
SCL

HREF

LLC

LLC2
VPOIN1
VPOIN0

100 nF

CVBS0

CVBS1

100 nF

12 MHz

(1)

12

16 41 6

13

15

14

8

7

9

3
4
2
42
43
39
38

17 40 18 19 11 10

GND

ADDRESS

DECODER

e.g.

PLUS153

or

74 SERIES

LOGIC

V

CC

44

22
pF

V

SSA

= 0 V

V

DDA

= +5 V

V

DDA

V

DDDVDDX

V

DDD

= +5 V

V

SSA

= 0 V

D7
D6
D5

D4
D3
D2
D1
D0

D7
D6
D5

D4
D3
D2
D1
D0

A0
A1
A2

20
21
22

23
24
25
26
27

28
29
30

31
32
33
34
36
37

1
5

35

2

B9
B8
B7
B6
B5

n.c.

B4
B3
B2

1

INT
RDY

(2)

WR
RD
DMARQ
DMACK

(3)

3
4

5
6
7
8

19

11

B1

9

B0

I0

AEN

I1
I2
I3
I4
I5
I6
I7

A3
A4
A5
A6
A7
A8
A9

18
17

16
15
14
13
12

10 20

RESET
DENB

A0
A1
A2

IRQx
I/O RDY
IOW
IOR
DACKx

RESET
n.c.

CS0

SAA5284

V

SSD

= 0 V V

DDD

= 5 V

V

DDA

V

DDD

V

SSA

V

SSD

100

nF

100

nF

10

µF

10

µF

+5 V

0 V

1998 Feb 05 20

Philips Semiconductors Objective specification

Multimedia video data acquisition circuit SAA5284

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handbook, full pagewidth

MGG744

75 Ω

75 Ω

27 kΩ

22
pF

100 nF

BLACK

I

REF

V

SSAVSSD3VSSD1VSSD2

V

SSA

= 0 V

V

SSD

= 0 V

V

SSD

= 0 V

SEL1 SEL0 CS1

CVBS0

CVBS1

OSCIN

OSCOUT

OSCGND

SDA

supply decoupling

SCL

HREF

LLC

LLC2
VPOIN1
VPOIN0

100 nF

CVBS0

CVBS1

100 nF

12 MHz

(1)

12

16 41 6

13

15

14

8

7

9

3
4
2
42
43
39
38

17 40 18 19 11 10 44

22
pF

V

SSA

= 0 V

V

DDA

= +5 V

V

DDAVDDDVDDX

V

DDD

= +5 V

V

SSA

= 0 V

5 kΩ

V

DDD

D7
D6
D5
D4
D3
D2
D1
D0
A0
A1

A2

1Q
2Q

3Q

1D
2D

3D
4D

20
21
22
23
24
25
26
27
28
29

30

16
15

74HCT75

10

2
3

6
7

13 4

LE LE

31
32
33
34
36
37

1
5

INT
RDY

WR

RD
DMARQ
DMACK
RESET

n.c.
V

DDD

n.c.

DENB

SAA5284

XAD7
XAD6
XAD5
XAD4
XAD3
XAD2
XAD1
XAD0

DEBI PORT

XIRQ

RDY

WRN

RDN

RESET

23

SAA7145
SAA7146

115

116

117

118

35

CS0

ALE

114

124
123

125

126

129

130

131

132

V

DDA

V

DDD

V

SSA

V

SSD

100

nF

100

nF

10

µF

10

µF

+5 V

0 V

Fig.11 Application circuit diagram for PCI application.

(1) Option of 13.5, 15 and 16 MHz or LLC2 from the SAA7111 if in 13.5 MHz mode.

1998 Feb 05 21

Philips Semiconductors Objective specification

Multimedia video data acquisition circuit SAA5284

14 PACKAGE OUTLINE

UNIT A1A2A3b

p

cE

(1)

eH

E

LL

p

Zywv θ

REFERENCES

OUTLINE
VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC JEDEC EIAJ

mm

0.25

0.05

2.3

2.1

0.25

0.50

0.35

0.25

0.14

14.1

13.9

1

19.2

18.2

2.4

1.8

7
0

o
o

0.152.35 0.10.3

DIMENSIONS (mm are the original dimensions)

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

2.0

1.2

SOT205-1

95-02-04
97-08-01

D

(1) (1)(1)

14.1

13.9

H

D

19.2

18.2

E

Z

2.4

1.8

D

b

p

e

θ

E

A

1

A

L

p

detail X

L

(A )

3

B

11

y

c

D

H

b

p

E

H

A

2

v M

B

D

Z

D

A

Z

E

e

v M

A

X

1

44

34

33 23

22

12

133E01A

pin 1 index

w M

w M

0 5 10 mm

scale

QFP44: plastic quad flat package; 44 leads (lead length 2.35 mm); body 14 x 14 x 2.2 mm

SOT205-1

A

max.

2.60

1998 Feb 05 22

Philips Semiconductors Objective specification

Multimedia video data acquisition circuit SAA5284

15 SOLDERING

15.1 Introduction

There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.

This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our

“IC Package Databook”

(order code 9398 652 90011).

15.2 Reflow soldering

Reflow soldering techniques are suitable for all QFP
packages.

The choice of heating method may be influenced by larger
plastic QFP packages (44 leads, or more). If infrared or
vapour phase heating is used and the large packages are
not absolutely dry (less than 0.1% moisture content by
weight), vaporization of the small amount of moisture in
them can cause cracking of the plastic body. For more
information, refer to the Drypack chapter in our

“Quality

Reference Handbook”

(order code 9397 750 00192).

Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.

Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 50 and 300 seconds depending on heating
method. Typical reflow peak temperatures range from
215 to 250 °C.

15.3 Wave soldering

Wave soldering is not recommended for QFP packages.
This is because of the likelihood of solder bridging due to
closely-spaced leads and the possibility of incomplete
solder penetration in multi-lead devices.

CAUTION

Wave soldering is NOT applicable for all QFP
packages with a pitch (e) equal or less than 0.5 mm.

If wave soldering cannot be avoided, for QFP
packages with a pitch (e) larger than 0.5 mm, the
following conditions must be observed:

• A double-wave (a turbulent wave with high upward

pressure followed by a smooth laminar wave)
soldering technique should be used.

• The footprint must be at an angle of 45° to the board

direction and must incorporate solder thieves
downstream and at the side corners.

During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.

Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
6 seconds. Typical dwell time is 4 seconds at 250 °C.

A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.

15.4 Repairing soldered joints

Fix the component by first soldering two diagonally­opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.

1998 Feb 05 23

Philips Semiconductors Objective specification

Multimedia video data acquisition circuit SAA5284

16 DEFINITIONS

17 LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

18 PURCHASE OF PHILIPS I

2

C COMPONENTS

Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

Purchase of Philips I

2

C components conveys a license under the Philips’ I2C patent to use the
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.

Internet: http://www.semiconductors.philips.com

Philips Semiconductors – a worldwide company

© Philips Electronics N.V. 1997 SCA53
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.

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Printed in The Netherlands 655102/00/02/pp24 Date of release: 1998 Feb 05 Document order number: 9397 750 02768